Abstract: A light-emitting diode includes, a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer. The light-emitting diode also includes a transparent conductive layer including a first transparent conductive layer disposed on the second semiconductor layer and a second transparent conductive layer disposed on the first transparent conductive layer. The second transparent conductive layer has a conductivity different than the first transparent conductive layer.

Abstract: According to at least some embodiments of the present disclosure, a light-emitting diode (LED) chip includes a semiconductor material portion, a transparent conductive layer disposed above the semiconductor material portion, a current blocking layer disposed above the transparent conductive layer, one or more electrodes disposed above the current blocking layer, and a plurality of electron outflow channels that electrically interconnect at least one electrode and the semiconductor material portion across the transparent conductive layer and the current blocking layer.

Abstract: The present invention provides an electroluminescent device comprising a substrate (1) and stacked thereon in the order of mention a first transparent electrode (2), an electroluminescent stack (3), and a second electrode (4). Furthermore, the electroluminescent device comprises at least one additional hard layer (5) that is located underneath the second electrode and/or on top of the second electrode and that has a hardness larger than the hardness of the second electrode. Methods for the production of such electroluminescent devices are likewise provided.

Abstract: A semiconductor metallurgy includes a ratio of germanium and palladium that provides low contact resistance to both n-type material and p-type material. The metallurgy allows for a contact that does not include gold and is compatible with mass-production CMOS techniques. The ratio of germanium and palladium can be achieved by stacking layers of the materials and annealing the stack, or simultaneously depositing the germanium and palladium on the material where the contact is to be manufactured.

Abstract: An arrangement having a first and a second substrate is disclosed, wherein the two substrates are connected to one another by means of an SLID (Solid Liquid InterDiffusion) bond. The SLID bond exhibits a first metallic material and a second metallic material, wherein the SLID bond comprises the intermetallic Al/Sn-phase.

Abstract: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175-C is 2000 Pa or more.

Abstract: A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.

Abstract: A liquid crystal display device includes a gate electrode formed on a substrate; a active pattern and an ohmic contact pattern formed to overlap with the gate electrode with a gate insulating film therebetween; a source electrode formed on the active pattern and the ohmic contact; a drain electrode formed to oppose the source electrode; a pixel electrode overlapped with the drain electrode and directly contacted with the drain electrode; a common electrode formed to overlap with the pixel electrode with a passivation film therebetween and having a plurality of holes; and wherein the plurality of holes of the common electrode are only formed on a region in which the pixel electrode is formed.

Abstract: Embodiments of a low resistivity contact to a semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a semiconductor layer, a semiconductor contact layer having a low bandgap on a surface of the semiconductor layer, and an electrode on a surface of the semiconductor contact layer opposite the semiconductor layer. The bandgap of the semiconductor contact layer is in a range of and including 0 to 0.2 electron-volts (eV), more preferably in a range of and including 0 to 0.1 eV, even more preferably in a range of and including 0 to 0.05 eV. Preferably, the semiconductor layer is p-type. In one particular embodiment, the semiconductor contact layer and the electrode form an ohmic contact to the p-type semiconductor layer and, as a result of the low bandgap of the semiconductor contact layer, the ohmic contact has a resistivity that is less than 1×10?6 ohms·cm2.

Abstract: Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

Abstract: A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.

Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Abstract: A microelectronic device includes a non-polymeric substrate, an organic interlayer, and a indium tin oxide layer formed on the organic interlayer; the indium tin oxide layer including an ablated feature within said indium tin oxide layer, wherein said indium tin oxide layer is formed by an indium tin oxide solution that is laser ablated prior to sintering. Applicant respectfully submits that the above amendments bring the Abstract into compliance with MPEP §608.01 (b). Accordingly, Applicant respectfully requests reconsideration and withdrawal of the objection to the abstract.

Abstract: A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.

Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the, same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

Abstract: A microelectronic device includes a non-polymeric substrate, an organic interlayer, and a indium tin oxide layer formed on the organic interlayer.

Abstract: The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resistance of the ohmic contact is adjusted by the thicknesses of the three layers.

Abstract: A semiconductor device includes a lower electrode of a capacitor, a dielectric layer disposed on the lower electrode, and an upper electrode of the capacitor disposed on the dielectric layer. The upper electrode includes a doped poly-Si1-xGex layer. An interlayer insulating layer is disposed on the doped poly-Si1-xGex layer and has a contact hole partially exposing the doped poly-Si1-xGex layer. A metal contact plug is in the contact hole and an interconnection layer is disposed on the interlayer insulating layer and connected to the metal contact plug. Related interconnection structures and fabrication methods are also disclosed.

Abstract: A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

Abstract: A semiconductor apparatus includes a semiconductor integrated circuit including a conductive pattern; an insulating layer which is formed on the semiconductor integrated circuit to forms a plurality of base members having uneven heights; an opening which is formed through the insulating layer to expose a part of the conductive pattern; and a conductive layer which is formed on the insulating layer and the opening, the conductive layer is extending from the exposed portion of the conductive pattern to the top surface of the highest base member. An electrode is composed of the insulating layer, the opening and the conductive layer.

Abstract: A semiconductor chip and connection ends of corresponding external electrode terminals are encapsulated with a glass based sealing material, and the semiconductor chip includes a wide gap semiconductor element, and the electrodes of the semiconductor chip are connected to the end portions of the external electrode terminals by a silver based brazing member and/or pressure contact.

Abstract: Disclosed herein is a technique for forming a high quality ohmic contact utilizable in the fabrication of short-wavelength light emitting diodes (LEDs) emitting blue and green visible light and ultraviolet light, and laser diodes (LDs) using a gallium nitride (GaN) semiconductor. The ohmic contact is formed by depositing a nickel (Ni)-based solid solution on top of a p-type gallium nitride semiconductor. The ohmic contact thus formed has an excellent current-voltage characteristic and a low specific contact resistance due to an increased effective carrier concentration around the surface of the gallium nitride layer, as well as a high transmittance in the short-wavelength region.

Abstract: A lid material (1) according to the present invention comprises: a base layer (2) composed of a low thermal expansion metal; an intermediate metal layer (3) provided on one surface of the base layer (2) and composed of a low proof stress metal having a proof stress of not greater than 110 N/mm2; and a brazing material layer (4) provided on the intermediate metal layer (3) and composed of a silver brazing alloy mainly comprising silver. The intermediate metal layer (3) and the brazing material layer (4) are press- and diffusion-bonded to each other, and the brazing material layer (4) has a blistered area ratio of not greater than 0.5% as observed on an outer surface of the brazing material layer. The low proof stress metal is preferably oxygen-free copper. A lid produced from the lid material (1) exhibits an excellent bonding property when the lid is brazed to a case mainly composed of a ceramic material for an electronic component package.

Abstract: A method of reducing the specific contact resistivity of a metal to semiconductor interface between a metal contact and an InP semiconductor compound. The method includes the step of increasing the amount of the group V element (P) in the semiconductor compound so that the semiconductor compound is non-stoichiometric having an excess concentration of the group V element in an amount of at least 0.1% above stoichiometric levels.

Abstract: An electrode structure on a p-type III group nitride semiconductor layer includes first, second and third electrode layers successively stacked on the semiconductor layer. The first electrode layer includes at least one selected from a first metal group of Ti, Hf, Zr, V, Nb, Ta, Cr, W and Sc. The second electrode layer includes at least one selected from a second metal group of Ni, Pd and Co. The third electrode layer includes Au.

Abstract: A novel contact structure and method for a multilayer gettering contact metallization is provided utilizing a thin layer of a pure metal as the initial layer formed on a semiconductor cap layer. During formation of the contact structure, this thin metal layer reacts with the cap layer and the resulting reacted layer traps mobile impurities and self-interstitials diffusing within the cap layer and in nearby metal layers, preventing further migration into active areas of the semiconductor device. The contact metallization is formed of pure metal layers compatible with each other and with the underlying semiconductor cap layer such that depth of reaction is minimized and controllable by the thickness of the metal layers applied. Thin semiconductor cap layers, such as InGaAs cap layers less than 200 nm thick, may be used in the present invention with extremely thin pure metal layers of thickness 10 nm or less, thus enabling an increased level of integration for semiconductor optoelectronic devices.

Abstract: A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si—Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

Abstract: A composite Pt/Ti/WSi/Ni Ohmic contact has been fabricated by a physical deposition process which uses electron beam evaporation and dc-sputter deposition. The Ni based composite Ohmic contact on n-SiC is rapid thermally annealed (RTA) at 950° C. to 1000° C. for 30s to provide excellent current-voltage characteristics, an abrupt, void free contact-SiC interface, retention of the as-deposited contact layer width, smooth surface morphology and an absence of residual carbon within the contact layer and/or at the Ohmic contact-SiC interface. The annealed produced Ni2Si interfacial phase is responsible for the superior electrical integrity of the Ohmic contact to n-SiC. The effects of contact delamination due to stress associated with interfacial voiding has been eliminated. Wire bonding failure, non-uniform current flow and SiC polytype alteration due to extreme surface roughness have also been abolished.

Abstract: A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.

Abstract: A contact structure for group III-V and group II-VI compound semiconductor devices, generally used as a light emitting diode (LED), a laser diode (LD), or a photodiode (PD), comprising p-type and/or n-type conduction is disclosed. The contact structure comprises a stack of multiple layers of metals and transparent conducting oxide. The first layer of the contact structure is in direct contact to the semiconductor and comprises at least one of indium, tin, nickel, chromium and zinc, or an alloy or combination of layers thereof. The second layer of the structure is in direct contact to the first layer and comprises at least one of Indium Tin Oxide, Indium oxide, and Tin oxide, or a combination thereof. The optional third layer of the structure contacts the second layer and comprises at least one of Au, Al, Pt, Pd, Mo, Cr, Rh, Ti. The third layer may be a contact pad contacting a smaller portion of the second layer.

Abstract: The present invention provides a system for self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. This alloy of silver and silicon is the final contact material, and is composed of eutectic proportions of silicon and silver. Under eutectic proportions there is significantly more silver than silicon in the final contact material, thereby insuring good electrical conductivity of the final contact material.

Abstract: A p-type contact electrode device in a ZnSe-based II-VI compound semiconductor, which electrode device uses, as a contact layer, a BeTe layer having a high p-type doping and a low lattice mismatching with a GaAs substrate to prevent oxidation in air. The device 2 includes a contact layer 5 composed of p-BeTe and a cap layer 4 is composed of p-ZnSe. The cap layer 4 is positioned on the contact layer 5 and an electrode 3 sits atop the cap layer. Preferably, the thickness of the cap layer is 30 to 70 Å and the electrode is composed of gold or gold is dispersed in the cap layer.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.

Abstract: A silicon wafer has a B-stageable underfill material deposited on the active face of the wafer. The B-stageable underfill comprises a first composition with a lower curing temperature and a second composition with a higher curing temperature, characterized in that the first composition has been fully cured.

Abstract: A method of reducing the specific contact resistivity of a metal to semiconductor interface between a metal contact and an InP semiconductor compound. The method includes the step of increasing the amount of the group V element (P) in the semiconductor compound so that the semiconductor compound is non-stoichiometric having an excess concentration of the group V element in an amount of at least 0.1% above stoichiometric levels.

Abstract: The present invention is directed to an apparatus and method for connecting integrated circuits placed on opposite sides of a circuit board through utilization of conduction elements embedded in the circuit board and extending from one surface of the board to the other. Conductive traces extend along the surface of the circuit board from the conduction elements to the integrated circuits. The conductive traces may be formed from multiple conductive layers.

Abstract: There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer of a metallization layer. In one embodiment, the porous layer may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.

Abstract: A cross under metal wiring structure which may prevent “latch-up” from causing at a pnpn-structure is provided. The cross under metal wiring structure comprises a lower wiring provided on a topmost layer of the pnpn-structure isolated in an island by a groove, and an upper wiring connected to the lower wiring through a first contact hole opened in an insulating film covered the isolated pnpn-structure and to a layer just below the topmost layer through a second contact hole opened in the insulating film.

Abstract: A semiconductor device has a dielectric film made of a fluorine-added carbon film formed on a substrate, a metallic layer formed on the fluorine-added carbon film and an adhesive layer formed between the dielectric film and the metallic layer. The adhesive layer is made of a compound layer having carbon and the metal (or metal the same as the metal included in the metallic layer), to protect the metallic layer from being peeled-off from the fluorine-added carbon film.

Abstract: A semiconductor triode comprises a gate electrode provided on a channel layer, wherein there is interposed an insulating metal oxide layer between a top surface of the channel layer and the gate electrode.

Abstract: The disclosed semiconductor device comprises an ohmic contact between a semiconductor region made of n-conducting silicon carbide and a largely homogeneous ohmic contact layer (110), which adjoins the semiconductor region and is made of a material having a first and a second material component. A silicide formed from the first material component and the silicon of the silicon carbide and a carbide formed from the second material component and the carbon of the silicon carbide are contained in a junction region between the semiconductor region and the ohmic contact layer. The silicide and carbide formation take place at maximum 1000° C.

Abstract: A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1×1015 cm−3. Accordingly, when a gate oxide film is formed on the surface channel layer, an amount of silicon nitride produced in the gate oxide film and at the interface between the gate oxide film and the surface channel layer becomes extremely small. As a result, carrier traps are prevented from being produced by silicon nitride, resulting in stable FET characteristics and high reliability to the gate oxide film.

Abstract: Methods and structures of in-situ wafer scale polymer stud grid array (ISWS-PSGA) contact formation on integrated circuit devices, wherein a separate pre-manufactured PSGA substrate is not needed. The methods include injection molding of thermoplastics, transfer-molding of thermoset materials, lamination of polymer films with subsequent in-situ molding/embossing, and forming the PSGA structure directly on the semiconductor wafer. The ISWS-PSGA structure extends across the entire semiconductor wafer, with ISWS-PSGA metallized input/output studs disposed across each of the integrated circuit devices on the wafer. The polymer formed on the wafer surface to create the stud field is extended beyond the perimeter of the wafer, and the polymer film extension is used for temporary connection to an integrated circuit tester, or an integrated circuit test/burn-in system. The extension may further include studs for contacting the tester.

Abstract: Disclosed is a compound semiconductor field effect transistor. The compound semiconductor field effect transistor has a charge absorption layer and a semiconductor laminated structure. The charge absorption layer includes a compound semiconductor layer of a first conductive type formed in a part of a compound semiconductor substrate having a semi-insulating layer. The semiconductor laminated structure includes at least an active layer including a compound semiconductor layer of a second conductive type epitaxially grown so as to cover the charge absorption layer and a region of the semi-insulating surface where the charge absorption layer is not formed. A source electrode is formed on the semiconductor laminated structure, being electrically connected to the charge absorption layer.

Abstract: A pad metal film used to fit a conductor for external connection composed of a bump-like or wire-like conductor can be formed by reduced numbers of processes. A semiconductor device is so configured that a trench for interconnect with its diameter of about 50 &mgr;m and its depth of about 2 &mgr;m is formed on a protective insulating film, formed on a semiconductor substrate, with a thickness of 3 to 4 &mgr;m, and in the trench for interconnect is imbedded an uppermost-layered copper wiring through a first barrier metal film composed of a titanium nitride with a thickness of about 50 nm. Furthermore, approximately in the center region of the upper-layered copper wiring is imbedded a copper pad film through a second barrier metal film with a thickness of about 70 nm.

Abstract: A passive semiconductor device structure is made using planar lateral oxidation to define a buried oxidized semiconductor structure such as a passive waveguide, microlens or DBR mirror stack.

Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.

Abstract: A method of forming titanium nitride barrier layers that are highly conformal, have high step coverage and low resistivity through a two stage deposition process is described. Low temperature deposition of titanium nitride barrier layer provides material of high conformity and good step coverage but of high resistivity. High temperature deposition of titanium nitride barrier layer yields material of low resistivity. Thus, a titanium nitride barrier layer deposited in separate steps at low temperature and high temperature by the method of the present invention is particularly suited for use in modern devices of increasing density that are characterized by narrow and deep contact holes.