Of Specified Material Other Than Unalloyed Aluminum Patents (Class 257/741)
  • Patent number: 10748786
    Abstract: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 18, 2020
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Ronald Patrick Huemoeller, Michael G. Kelly, Curtis Zwenger
  • Patent number: 10727184
    Abstract: Described are example microelectronic devices including structures, such as build-up layers, formed of a non-homogeneous photoimageable dielectric material. The non-homogeneous photoimageable dielectric material includes two regions forming opposite surfaces of the material. A first region includes a first carbon content, and a second region located above the first region includes a second carbon content which is greater than that of the first region. The second region of the photoimageable dielectric material provides enhanced adhesion with metal that may be deposited above the material, such as a sputtered metal seed layer to facilitate subsequent deposition of an electroless metal over the non-homogeneous photoimageable dielectric material.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Siddharth K. Alur, Srinivas V. Pietambaram
  • Patent number: 10707184
    Abstract: A thermal bonding sheet includes a layer, in which hardness of the layer after being heated at a heating rate of 1.5° C./sec from 80° C. to 300° C. under pressure of 10 MPa, and then held at 300° C. for 2.5 minutes is in a range of 1.5 GPa to 10 GPa in measurement using a nanoindenter.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 7, 2020
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuki Sugo, Nao Kamakura
  • Patent number: 10668696
    Abstract: The present invention provides a bonding method (S1) which is capable of achieving a high adhesive force without carrying out any special treatment on the second member (14), even in a case where the first member (11) has a surface on which a gold thin film (12) is formed. The first member (11) is made of a material other than gold and has a surface on which the gold thin film (12) is formed. The bonding method (S1) includes the steps of: (S11) irradiating, with laser light, at least part of a specific region (12a) of the surface of the first member (11), so that a base of the thin film (12) is exposed in the at least part of the specific region (12a); and (S12) bonding the second member (14) to the specific region (12a) by use of an adhesive (13).
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 2, 2020
    Assignee: FUJIKURA LTD.
    Inventors: Shohei Kumeta, Gento Yoshino, Yohei Kasai, Akira Sakamoto
  • Patent number: 10657852
    Abstract: The present invention relates to a flexible transparent display sheet, and an image display apparatus including the same. The flexible transparent display sheet according to an embodiment of the present disclosure includes: a base disposed in a display area and a connection area; a metal layer formed on the base; an anti-oxide layer formed on a portion of the metal layer; a plurality of solders formed on a portion of the anti-oxide layer; a plurality of light emitters, each of which is connected to each of the plurality of solders; and an insulation layer disposed in the connection area and formed on the anti-oxide layer. Accordingly, a flexible transparent display sheet having an integrally formed power connector may be provided.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 19, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Jungwoon Park, Jeoungan Kim
  • Patent number: 10658508
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes forming a modified region in the epitaxial structure. The modified region has lower crystallinity than an inner portion of the epitaxial structure and extends along an entirety of an exposed surface of the epitaxial structure. The method also includes forming a semiconductor-metal compound region on the epitaxial structure. All or some of the modified region is transformed into the semiconductor-metal compound region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen
  • Patent number: 10643892
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: 10553478
    Abstract: Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: forming a doped metal layer within a contact opening in an inter-level dielectric (ILD) material on a conductive region, such that the doped metal layer overlies the conductive region, the doped metal layer including a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material, the interface liner formed only on sidewalls of the contact opening and in direct contact with the ILD material and only at an interface of the doped metal layer and the ILD material.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Moosung M. Chae
  • Patent number: 10535816
    Abstract: A via structure, a MRAM device using the via structure and a method for fabricating the MRAM device are provided. In the method for fabricating the MRAM device, at first, a first dielectric layer is deposited over a transistor. Then, a contact is formed in the first dielectric layer and electrically connected to the transistor. Thereafter, a metal nitride layer is deposited over the first dielectric layer and the contact. Then, an etch stop layer is deposited over the metal nitride layer. Thereafter, a second dielectric layer is deposited over the etch stop layer. Then, a via structure is formed in the second dielectric layer, the etch stop layer, and the metal nitride layer and landing on the contact. Thereafter, a memory stack is formed over the via structure.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Szu-Ping Tung, Szu-Hua Wu, Shing-Chyang Pan, Meng-Yu Wu
  • Patent number: 10460956
    Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Benjamin V. Fasano, Shidong Li
  • Patent number: 10444576
    Abstract: A drain layer lead line connecting an image signal line and a terminal of an IC driver is interrupted in the middle, and the gap is bridged by bridging ITO that is formed at the same time as pixel ITO. Thus, the difference in the length of the lead lines is adjusted such that the length of the bridging ITO in the lead line connected to the terminal in the center of the IC driver is longer than the length of the bridging ITO in the lead line connected to the terminal in the end of the IC driver to reduce the difference in the wiring resistance of the lead lines due to the difference in the length of the lead lines depending on the location.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 15, 2019
    Assignee: Japan Display Inc.
    Inventor: Takahiro Nagami
  • Patent number: 10431518
    Abstract: A radio frequency integrated circuit (RFIC) device and a method for fabricating same are disclosed. The RFIC device includes: a first semiconductor layer having a first surface, a second surface and a thickness of smaller than 3 ?m; a first dielectric layer on the first surface of the first semiconductor layer; a semiconductor component within the first semiconductor layer and the first dielectric layer; a second dielectric layer on the second surface of the first semiconductor layer, the second dielectric layer having a thickness of smaller than 1 ?m; and a sheet-like heat sink that is formed on the surface of the second dielectric layer opposite to the first semiconductor layer for dissipating heat from the semiconductor component. Efficient dissipation of heat from an RF transistor to a certain extent can be achieved by the RFIC device.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 1, 2019
    Assignee: NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventor: Xiaochuan Wang
  • Patent number: 10361400
    Abstract: An organic light emitting diode display including: a substrate; an organic light emitting diode on the substrate; a capping layer on the organic light emitting diode and including a high refractive layer including an inorganic material having a refractive index that is equal to or greater than about 1.7 and equal to or less than about 6.0; and a thin film encapsulation layer covering the capping layer and the organic light emitting diode, the inorganic material including at least one selected from the group consisting of CuI, thallium iodide (TlI), BaS, Cu2O, CuO, BiI, WO3, TiO2, AgI, CdI2, HgI2, SnI2, PbI2, BiI3, ZnI2, MoO3, Ag2O, CdO, CoO, Pr2O3, SnS, PbS, CdS, CaS, ZnS, ZnTe, PbTe, CdTe, SnSe, PbSe, CdSe, AlAs, GaAs, InAs, GaP, InP, AlP, AlSb, GaSb, and InSb.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won Jong Kim, Dong Chan Kim, Eung Do Kim, Dong Kyu Seo, Da Hea Im, Sang Hoon Yim, Yoon Hyeung Cho, Won Suk Han
  • Patent number: 10354986
    Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Pin Huang, Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai
  • Patent number: 10347594
    Abstract: A semiconductor device includes a wiring, a semiconductor chip above the wiring and a metal block above the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a lower electrode, an upper large electrode and an upper small electrode. The semiconductor chip includes a first portion and a second portion, the first portion being on an upper small electrode side with respect to a centroid of the semiconductor chip, the second portion being on an opposite side of the upper small electrode with respect to the centroid. The lower electrode is connected to the wiring via a lower solder layer. The lower solder layer includes a solder base material and metal particles. A volume ratio of the metal particles occupying the lower solder layer under the second portion is higher than a volume ratio of the metal particles occupying the lower solder layer under the first portion.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 9, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masayuki Kamiya
  • Patent number: 10332837
    Abstract: A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Takeshi Nogami
  • Patent number: 10249546
    Abstract: Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or other types of defects. Reverse decoration can preserve a defect and/or can improve defect detection. A portion of a layer may be removed from a device. A layer also may be added to the device, such as on the defect, and some of the layer may be removed.
    Type: Grant
    Filed: December 24, 2016
    Date of Patent: April 2, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Philip Measor, Robert Danen, Paul MacDonald
  • Patent number: 10224285
    Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 5, 2019
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, Eduardo M. Chumbes, Kelly P. Ip, Thomas E. Kazior
  • Patent number: 10204932
    Abstract: An array substrate and a manufacturing method thereof are provided. The array substrate includes a display area (02) and a fan-out area (01) disposed at the periphery of the display area (02), the manufacturing method comprising forming a line pattern (212) disposed in at least one of the display area (02) and the fan-out area (01), wherein forming a line pattern disposed in at least one of the display area and the fan-out area includes the following steps: forming a metal layer (210); forming an intermediate pattern (211) by performing a first patterning process on the metal layer; and forming the line pattern disposed in at least one of the display area (02) and the fan-out area (01) by performing a second patterning process on the intermediate pattern.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Lijuan Yang
  • Patent number: 10199504
    Abstract: Embodiments of the present invention disclose a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which relates to the field of display technology, and solves the problem that the adhesion of the electrode thin film with the adjacent thin film layer in the thin film transistor of the prior art is relatively bad. More specifically, an embodiment of the present invention provides a thin film transistor, comprising a gate, a source, a drain and a buffer layer, the buffer layer is located at one side or two sides of the gate, the source or the drain, the material of the buffer layer is a copper alloy material, the copper alloy material contains nitrogen element or oxygen element, the copper alloy material further contains aluminum element.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: February 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhengliang Li, Qi Yao, Zhanfeng Cao, Bin Zhang, Xiaolong He, Jincheng Gao, Xiangchun Kong, Wei Zhang
  • Patent number: 10177118
    Abstract: To miniaturize metal columns. A semiconductor device includes a metal column (14) that extends in a stretching direction; a polymer layer (16) that surrounds the metal column from a direction crossing the stretching direction; and a guide (12) that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture (20) containing metal particles (22) and polymers (24) in a guide (12); and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer (16) that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column (14) that stretches in a stretching direction of the guide from the metal particles.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 8, 2019
    Assignees: TOHOKU UNIVERSITY, TOSHIBA MEMORY CORPORATION
    Inventors: Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, Kang-Wook Lee
  • Patent number: 10164115
    Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Neville L. Dias, Chia-Hong Jan, Walid M. Hafez, Roman W. Olac-Vaw, Hsu-Yu Chang, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu
  • Patent number: 10137534
    Abstract: A bonding wire includes a Cu alloy core material, and a Pd coating layer formed on the Cu alloy core material. The bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir, and Pt. A concentration of the elements in total relative to the entire wire is 0.03% by mass or more and 2% by mass or less. When measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire axis direction has a proportion of 50% or more among crystal orientations in the wire axis direction. An average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 ?m or more and 1.3 ?m or less.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: November 27, 2018
    Assignees: Nippon Micrometal Corporation, Nippon Steel & Sumikin Materials Co., Ltd.
    Inventors: Takashi Yamada, Daizo Oda, Teruo Haibara, Ryo Oishi, Kazuyuki Saito, Tomohiro Uno
  • Patent number: 10101918
    Abstract: Systems and methods for generating hint information associated with a host command are disclosed. In one implementation, a processor of a host system determines whether the host system has initiated a procedure that will send a command to a non-volatile memory system. The processor analyzes at least one of metadata or payload data associated with the command to determine whether the processor is able to generate hint information associated with the at least one of metadata or payload data. The processor generates hint information based on the analysis of the at least one of metadata or payload data, sends the hint information to the non-volatile memory system, and sends the command to the non-volatile memory system.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 16, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Judah Gamliel Hahn, Joseph R. Meza, William L. Guthrie
  • Patent number: 10074472
    Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Wei-Ting Chen, Vincent Chen, Hao-Yi Tsai, Ming Hung Tseng, Hung-Yi Kuo, Chen-Hua Yu
  • Patent number: 10023715
    Abstract: Provided are: an elastomer structure containing carbon nanotubes; and a method for producing the elastomer structure. In a CNT elastomer having a mesh shaped carbon nanotube aggregate on a surface layer thereof, the mesh shaped carbon nanotube aggregate can impart a shape-retaining property to the elastomer. Therefore, the elastomer can be molded along the shape of a mold, and it becomes possible to mold a carbon nanotube elastomer having a fine dimension. The elastomer structure containing carbon nanotubes according to the present invention is provided with mesh shaped carbon nanotube aggregate which are embedded in a surface layer of the elastomer structure containing carbon nanotubes and are not protruded from the surface of the elastomer structure containing carbon nanotubes.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: July 17, 2018
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Kenji Hata, Atsuko Sekiguchi
  • Patent number: 10014285
    Abstract: A semiconductor device may include a first conductive pattern disposed in a first interlayer insulating film, a second conductive pattern disposed in a second interlayer insulating film positioned on the first interlayer insulating film, a through electrode partially penetrating through the first interlayer insulating film and the second interlayer insulating film. The through electrode electrically connects the first conductive pattern and the second conductive pattern. The device further includes a first pattern completely surrounding side surfaces of the through electrode, and a second pattern between the first pattern and the through electrode. The second pattern is separated from the first pattern and the through electrode. The device includes a third pattern connecting the first pattern and the second pattern.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: July 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Hyun Kim, Seung-Hoon Kim, Sang-Il Jung
  • Patent number: 10008407
    Abstract: A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Jin Lee, Byung-Hee Kim, Sang-Hoon Ahn, Woo-Kyung You, Jong-Min Baek, Nae-In Lee
  • Patent number: 9970113
    Abstract: A method for coating metallic surfaces with an aqueous composition, which contains an aqueous solution of a zinc salt, by flooding, spraying and/or immersion, wherein, for spraying or immersion, the initial temperature of the substrate lies in the range from 5 to 400° C., in that, for flooding, the initial temperature of the substrate lies in the range from 100 to 400° C. and in that an anticorrosive nanocrystalline zinc oxide layer is formed on the metallic surface. Corresponding aqueous composition, the nanocrystalline zinc oxide layer and the use of the coated substrates are also disclosed.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: May 15, 2018
    Assignee: Chemetall GmbH
    Inventors: Özlem Özcan, Guido Grundmeier, Peter Schubach
  • Patent number: 9941374
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Patent number: 9905763
    Abstract: The present disclosure relates to OLED and PV devices including transparent electrodes that are formed of conductive nanostructures and methods of improving light out-coupling in OLED and input-coupling in PV devices.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: February 27, 2018
    Assignee: CAM Holding Corporation
    Inventor: Florian Pschenitzka
  • Patent number: 9899376
    Abstract: An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: February 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaoju Wu, C. Matthew Thompson
  • Patent number: 9876094
    Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deok-Han Bae, Kyung-Soo Kim, Chul-Sung Kim, Woo-Cheol Shin, Hwi-Chan Jun
  • Patent number: 9864246
    Abstract: Disclosed are an array substrate and a display device which belong to the technical field of displays, and are intended to solve the technical problem of large width of the bezel of a liquid crystal display device. The array substrate is provided thereon with a fan-out zone which includes a plurality of conducting lines. At least one of the conducting lines includes a first metal wire and a second metal wire which are serially connected to each other. The second metal wire has a unit resistivity larger than that of the first metal wire. The conducting lines have different lengths, and the second metal wire in a shorter conducting line is longer than the second metal wire in a longer conducting line.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 9, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., LTd.
    Inventor: Yanfeng Fu
  • Patent number: 9859154
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The dielectric layer has a protection region and a lower portion that is between the protection region and the semiconductor substrate. The protection region contains more carbon than the dielectric layer. The semiconductor device structure also includes a conductive feature penetrating through the protection region, and a lower portion of the conductive feature is surrounded by the lower portion of the dielectric layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Kuan Lee, Hsin-Yen Huang, Hai-Ching Chen
  • Patent number: 9853005
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: December 26, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takehiko Maeda, Akira Yajima, Satoshi Itou, Fumiyoshi Kawashiro
  • Patent number: 9818716
    Abstract: A power module is fabricated, employing a clad metal that is formed by pressure-laminating aluminum and copper, in such a manner that the aluminum layer of the clad metal is bonded such as by ultrasonic bonding to the surface electrode of the power semiconductor chip and a wire is bonded to the copper layer thereof to establish electrical circuit. The clad metal is thermally treated in advance at a temperature higher than the operating temperature of the power semiconductor chip to sufficiently form intermetallic compounds at the interface between the aluminum layer and the copper layer for the intermetallic compounds so as not to grow in thickness after the bonding processes.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: November 14, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Yoshihisa Uchida, Shohei Ogawa, Soichi Sakamoto, Tatsunori Yanagimoto
  • Patent number: 9818644
    Abstract: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Yi Yang, Hsi-Wen Tien, Ming-Han Lee, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9795031
    Abstract: The present disclosure discloses a wiring board used to connect a driving chip and a display panel, a flexible display panel and a display device. Signal output ends on the driving chip and signal input ends on the display panel may be arranged in pairs; and the wiring board may include fanout lines each of which is configured to connect a pair of signal output end and the signal input end. The wiring board may include a substrate; a plurality of segments of first connection lines having first resistivity is arranged on a first surface of the substrate; a plurality of segments of second connection lines having second resistivity is arranged on a second surface of the substrate opposite to the first surface. At least parts of the fanout lines are formed by connecting the first connection lines and the second connection lines.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 17, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Song Song, Kazuyoshi Nagayama
  • Patent number: 9735079
    Abstract: A package substrate for chip/chips package wrapped by a molding compound is disclosed. The molding compound functions as a stiffener for the thin film package substrate. One embodiment discloses at least one redistribution layer (RDL) is prepared and the RDL is wrapped by a molding compound. The molding compound wraps four lateral sides and bottom side of the RDL. A top side of the RDL is made for a chip to mount and a bottom side of the RDL is planted a plurality of solder balls so that the bottom side of the chip package is adaptive to mount onto a system board in a later process.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 15, 2017
    Inventor: Dyi-Chung Hu
  • Patent number: 9735235
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 15, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 9728425
    Abstract: Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region, and the underfill material may comprise a non-visible light (NVL)-curable material. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: August 8, 2017
    Assignee: INTEL CORPORATION
    Inventors: Joshua D. Heppner, Serge Roux, Michael J. Baker, Javier A. Falcon
  • Patent number: 9607858
    Abstract: The invention provides a method of forming at least one Metal Germanide contact on a substrate for providing a semiconducting device (100) by providing a first layer (120) of Germanium (Ge) and a second layer of metal. The invention provides a step of reacting the second layer with the first layer with high energy density pulses for obtaining a Germanide metal layer (160A) having a substantially planar interface with the underlying first (Ge) layer.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: March 28, 2017
    Assignees: Laser Systems & Solutions of Europe (LASSE) Screen Semiconductor Solutions Co. Ltd., University College Cork—National University of Ireland, Cork
    Inventors: Ray Duffy, Maryam Shayesteh, Karim Huet
  • Patent number: 9601498
    Abstract: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: March 21, 2017
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Mitchell Meinhold, Steven L. Konsek, Thomas Rueckes, Max Strasburg, Frank Guo, X. M. Henry Huang, Ramesh Sivarajan
  • Patent number: 9570299
    Abstract: Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hong He, Ali Khakifirooz, Juntao Li
  • Patent number: 9553039
    Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three dimensional integration is offered by this scheme.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 24, 2017
    Assignee: AMS AG
    Inventors: Cathal Cassidy, Martin Schrems, Franz Schrank
  • Patent number: 9554460
    Abstract: A process for the manufacture of a reflective conductive film comprising: (i) a reflective polymeric substrate comprising a polymeric base layer and a polymeric binding layer, wherein the polymeric material of the base layer has a softening temperature TS-B, and the polymeric material of the binding layer has a softening temperature TS-HS; and (ii) a conductive layer comprising a plurality of nanowires, wherein said nanowires are bound by the polymeric matrix of the binding layer such that the nanowires are dispersed at least partially in the polymeric matrix of the binding layer, said process comprising the steps of providing a reflective polymeric substrate comprising a polymeric base layer and a polymeric binding layer; disposing said nanowires on the exposed surface of the binding layer; and heating the composite film to a temperature T1 wherein T1 is equal to or greater than TS?HS, and T1 is at least about 5° C. below TS-B.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: January 24, 2017
    Assignee: Dupont Teijin Films U.S. Limited Partnership
    Inventors: Tina Wright, Xavier Bories-Azeau
  • Patent number: 9524923
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a through silicon via hole, an interlayer dielectric, a liner layer and a conductor. The through silicon via hole is formed in the substrate. The interlayer dielectric is formed on the substrate. The interlayer dielectric defines an opening corresponding to the through silicon via hole. The interlayer dielectric comprises a bird beak portion near the through silicon via hole. The liner layer is formed on a bottom and a sidewall of the through silicon via hole. The conductor is filled in the through silicon via hole and the opening.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiao-Fei Han, Jun Qian, Ju-Bao Zhang
  • Patent number: 9515101
    Abstract: The present invention provides an array substrate and a method for manufacturing the same, and a display device. Wherein, after forming a pattern corresponding to a source/drain electrode layer, a transparent conducting layer is formed, and then a passivation layer is formed on the transparent conducting layer. Because the transparent conducting layer has a characteristic of anti-etching, it is hard to be damaged, so that the problem of damage of copper in the source/drain electrode layer is solved without increasing the process steps for forming the array substrate.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: December 6, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xuehui Zhang
  • Patent number: 9487864
    Abstract: Before depositing a metal capping layer on a metal interconnect in a damascene structure, a remote plasma is used to reduce native oxide formed on the metal interconnect. Accordingly, a remote plasma reducing chamber is integrated in a processing platform for depositing a metal capping layer.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Chi, Szu-Ping Tung, Huang-Yi Huang, Ching-Hua Hsieh