Of Specified Material Other Than Unalloyed Aluminum Patents (Class 257/741)
  • Patent number: 11456353
    Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: September 27, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Cih Kang, Hsih-Yang Chiu
  • Patent number: 11410928
    Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Mark Bohr, Mauro Kobrinsky, Marni Nabors
  • Patent number: 11328749
    Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Raju Ahmed, David A. Kewley, Dave Pratt, Yung-Ta Sung, Frank Speetjens, Gurpreet Lugani
  • Patent number: 11257790
    Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: February 22, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kurtis Leschkies, Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Jeffrey L. Franklin, Wei-Sheng Lei
  • Patent number: 11257779
    Abstract: A multilayer wiring board includes a first insulating layer, a second insulating layer stacked on the first insulating layer, a via conductor inside each of the first insulating layer and the second insulating layer, and a conductive bonding layer that bonds the via conductors to each other. The first insulating layer is directly bonded to the second insulating layer, and a relationship a1>b1 is satisfied, where a1 is a maximum diameter of the bonding layer and b1 is a maximum diameter of the via conductor at an interface with the bonding layer.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ryosuke Takada, Toshitaka Hayashi, Hiromasa Koyama
  • Patent number: 11247444
    Abstract: The present invention aims to provide a conductive layered body having excellent solvent resistance and scratch resistance as well as a low haze value and a significantly high light transmittance. The present invention relates to a conductive layered body including, as an outermost layer thereof, a conductive layer containing a conductive fibrous filler, wherein the conductive layered body has a Martens hardness of 150 to 3,000 N/mm2 as measured at an indentation depth of 100 nm from a surface, and a ratio, in atomic percentage, of a conductive material element constituting the conductive fibrous filler on an outermost surface-side surface of the conductive layer is 0.15 to 5.00 at %.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: February 15, 2022
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yoshimasa Ogawa, Yukimitsu Iwata, Yuji Shimizu, Eiji Ooishi, Shoichiro Ogumi, Norinaga Nakamura
  • Patent number: 11222676
    Abstract: Multi-period thin-film structures exhibiting giant magnetoresistance (GMR) are described. Techniques are also described by which narrow spacing and/or feature size may be achieved for such structures and other thin-film structures having an arbitrary number of periods.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 11, 2022
    Assignee: Integrated Magnetoelectronics Corp.
    Inventor: Edward Wuori
  • Patent number: 11217584
    Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layers. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: January 4, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Judson R. Holt, Jiehui Shu
  • Patent number: 11189597
    Abstract: A chip on film package including a flexible film, a first patterned circuit layer, one or more first chips, a second patterned circuit layer, and one or more second chips. The flexible film includes a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The one or more first chips are mounted on the first surface and electrically connected to the first patterned circuit layer. The second patterned circuit layer is disposed on the second surface. The one or more second chips are mounted on the second surface and electrically connected to the second patterned circuit layer.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: November 30, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Yu Liao, Teng-Jui Yu
  • Patent number: 11138360
    Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Hui-Zhong Zhuang, Meng-Hsueh Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Patent number: 11107695
    Abstract: Apparatus, systems, and methods for processing workpieces are provided. In one example implementation, a fluorine and oxygen plasma-based process can be used to smooth a roughened surface of a silicon and/or a silicon containing structure. The process can include generating species from a process gas using an inductive coupling element in a first chamber. The process can include introducing a fluorine containing gas and an oxygen containing gas with the species to create a mixture. The process can further include exposing the silicon and/or the silicon containing structure to the mixture such that the mixture at least partially etches a roughened portion to leave a smoother surface of the silicon and/or the silicon containing structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 31, 2021
    Assignees: Beijing E-Town Semiconductor Technology Co., Ltd., Mattson Technology, Inc.
    Inventors: Qi Zhang, Xinliang Lu, Hua Chung
  • Patent number: 11081425
    Abstract: A semiconductor package includes a base wafer including a first substrate and at least one first through via electrode extending through the first substrate, and a first semiconductor chip provided on the base wafer. The first semiconductor chip includes a second substrate; and at least one second through via electrode extending through the second substrate. The at least one second through via electrode is provided on the at least one first through via electrode to be electrically connected to the at least one first through via electrode. A first diameter of the at least one first through via electrode in a first direction is greater than a second diameter of the at least one second through via electrode in the first direction.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 3, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gun-Ho Chang, Seung-Duk Baek
  • Patent number: 11073733
    Abstract: A display panel including a fan-out wire, an electrostatic discharge device, a signal wire, and a first conductive via structure is provided. The electrostatic discharge device has a first electrode and a second electrode. The first conductive via structure is electrically connected to the fan-out wire, the first electrode of the electrostatic discharge device, and the signal wire.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: July 27, 2021
    Assignee: Au Optronics Corporation
    Inventor: Meng-Ting Hsieh
  • Patent number: 11049972
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an epitaxial structure over a semiconductor substrate. The method also includes generating and applying plasma on an entire exposed surface of the epitaxial structure to form a modified region in the epitaxial structure. The plasma is directly applied on the source/drain structure without being filtered out, and the plasma includes ions with different charges. The method further includes forming a metal layer on the modified region and heating the metal layer and the modified region to form a metal-semiconductor compound region.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 29, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen
  • Patent number: 11049846
    Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-hee Uh, Sung-min Kang, Jun-gu Kang, Seung-hee Go, Young-mok Kim
  • Patent number: 11043522
    Abstract: The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The structure includes a first interconnect layer within a first dielectric structure on a first substrate, and a second interconnect layer within a second dielectric structure on a second substrate. A bonding structure is between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends through the second substrate and between a top of the first interconnect layer and a bottom of the second interconnect layer. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region below the first region and having tapered sidewalls surrounded by the bonding structure.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang, Wei-Chih Weng, Yu-Yang Shen
  • Patent number: 11038344
    Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: June 15, 2021
    Assignee: Qualcomm Incorporated
    Inventors: John Jianhong Zhu, Xiangdong Chen, Haining Yang, Kern Rim
  • Patent number: 11031256
    Abstract: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 8, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Ronald Patrick Huemoeller, Michael G. Kelly, Curtis Zwenger
  • Patent number: 11011718
    Abstract: A solar cell includes elements, a connecting portion, and a transparent portion. The elements include first and second elements arrayed in a first direction. The transparent portion is located between the connecting portion and the second element. Each of the elements includes first and second electrode layers and a semiconductor layer interposed between the first and second electrode layers. Between the first element and the second element, their first electrode layers sandwich a first gap and their second electrode layers sandwich a second gap shifted in the first direction from the first gap. The connecting portion electrically connects the second electrode layer of the first element to the first electrode layer of the second element. The transparent portion is located between the second electrode layer of the first element and the first electrode layer of the second element at a position shifted in the first direction from the connecting portion.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 18, 2021
    Assignee: KYOCERA Corporation
    Inventor: Junji Aranami
  • Patent number: 11011887
    Abstract: A semiconductor laser diode is disclosed. In an embodiment a semiconductor laser diode includes a semiconductor layer sequence including an active layer having a main extension plane, configured to generate light in an active region during operation and configured to radiate the light via a light-outcoupling surface, wherein the active region extends from a rear surface opposite the light-outcoupling surface to the light-outcoupling surface along a longitudinal direction in the main extension plane and a continuous contact structure directly disposed on a surface of the semiconductor layer sequence, wherein the contact structure comprises in at least a first contact region a first electrical contact material in direct contact with the surface region and in at least a second contact region a second electrical contact material in direct contact with the surface region, and wherein the first and second contact regions adjoin one another.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 18, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Sven Gerhard, Christoph Eichler, Alfred Lell, Bernhard Stojetz
  • Patent number: 10968390
    Abstract: Provided are a composition for a semiconductor process, which comprises a first component comprising an inorganic acid or an organic acid; and a second component comprising a silicon compound represented by Formula 1, and a semiconductor process, which comprises selectively cleaning and/or removing an organic substance or an inorganic substance using the composition.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: April 6, 2021
    Assignee: SKC CO., LTD.
    Inventors: Byoungsoo Kim, Gyu An Jin, Jun Rok Oh
  • Patent number: 10950302
    Abstract: A resistive memory device including a substrate, an isolation structure, a word line, a source line, a bit line and a resistive memory is provided. The substrate includes a body region, and first, second and third doped regions, the first and second doped regions are spaced apart from each other by the body region. The isolation structure is disposed in the substrate, and the second doped region and the third doped region are spaced apart from each other by the isolation structure. The word line is disposed on the substrate, the first and second doped regions are located at opposite sides of the word line, and the first and third doped regions are located at the opposite sides of the word line. The source line is disposed on the substrate and electrically connected with the first doped region. The bit line and the resistive memory are disposed on the substrate, and the third doped region is electrically connected with the bit line via the resistive memory.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 16, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Chang-Hsuan Wu
  • Patent number: 10923451
    Abstract: Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Tianwei Sun, Jaynal A. Molla
  • Patent number: 10892187
    Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure provide an electronic device having a bridging via between a first metallization and a third metallization layer, the bridging via not contacting a second metallization layers. Methods of providing self-aligned bridging vias are also described.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 12, 2021
    Assignee: Micromaterials LLC
    Inventors: Regina Freed, Uday Mitra, Sanjay Natarajan
  • Patent number: 10861811
    Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chen-Shien Chen, Sheng-Yu Wu, Mirng-Ji Lii, Chita Chuang
  • Patent number: 10847634
    Abstract: Field effect transistor and methods of forming the same are disclosed. The field effect transistor includes a gate electrode, a contact etch stop layer (CESL), an inter layer dielectric (ILD) and a protection layer. The CESL includes SiCON and is disposed on a sidewall of the gate electrode. The IDL is laterally adjacent to the gate electrode. The protection layer covers the CESL and is disposed between the CESL and the ILD.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-En Cheng, Chun-Te Li, Kai-Hsuan Lee, Tien-I Bao, Wei-Ken Lin
  • Patent number: 10811502
    Abstract: A method for manufacturing a super-junction MOSFET entails forming a recessed shield electrode in a trench in a semiconductor layer of a substrate, the trench being lined with a first oxide layer. When the electrically conductive material forming the shield electrode is removed to recess the shield electrode, the first oxide layer on sidewalls of the trench is exposed. Removal of the first oxide layer from the sidewalls and from shield sidewalls of the electrode produces openings at a top part of the shield sidewalls. A second oxide layer is formed over the shield electrode and fills the openings. Part of the second oxide layer is removed to expose a top surface of the shield electrode. A gate dielectric is formed over the top surface of the shield electrode and conductive material is deposited over the gate dielectric in the trench to form a gate electrode of the MOSFET.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 20, 2020
    Assignee: NXP USA, Inc.
    Inventors: Vishnu Khemka, Tanuj Saxena, Ganming Qin, Raghuveer Vankayala Gupta, Mark Edward Gibson, Moaniss Zitouni
  • Patent number: 10811424
    Abstract: The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 10748786
    Abstract: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 18, 2020
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Ronald Patrick Huemoeller, Michael G. Kelly, Curtis Zwenger
  • Patent number: 10727184
    Abstract: Described are example microelectronic devices including structures, such as build-up layers, formed of a non-homogeneous photoimageable dielectric material. The non-homogeneous photoimageable dielectric material includes two regions forming opposite surfaces of the material. A first region includes a first carbon content, and a second region located above the first region includes a second carbon content which is greater than that of the first region. The second region of the photoimageable dielectric material provides enhanced adhesion with metal that may be deposited above the material, such as a sputtered metal seed layer to facilitate subsequent deposition of an electroless metal over the non-homogeneous photoimageable dielectric material.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Siddharth K. Alur, Srinivas V. Pietambaram
  • Patent number: 10707184
    Abstract: A thermal bonding sheet includes a layer, in which hardness of the layer after being heated at a heating rate of 1.5° C./sec from 80° C. to 300° C. under pressure of 10 MPa, and then held at 300° C. for 2.5 minutes is in a range of 1.5 GPa to 10 GPa in measurement using a nanoindenter.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 7, 2020
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuki Sugo, Nao Kamakura
  • Patent number: 10668696
    Abstract: The present invention provides a bonding method (S1) which is capable of achieving a high adhesive force without carrying out any special treatment on the second member (14), even in a case where the first member (11) has a surface on which a gold thin film (12) is formed. The first member (11) is made of a material other than gold and has a surface on which the gold thin film (12) is formed. The bonding method (S1) includes the steps of: (S11) irradiating, with laser light, at least part of a specific region (12a) of the surface of the first member (11), so that a base of the thin film (12) is exposed in the at least part of the specific region (12a); and (S12) bonding the second member (14) to the specific region (12a) by use of an adhesive (13).
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 2, 2020
    Assignee: FUJIKURA LTD.
    Inventors: Shohei Kumeta, Gento Yoshino, Yohei Kasai, Akira Sakamoto
  • Patent number: 10658508
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes forming a modified region in the epitaxial structure. The modified region has lower crystallinity than an inner portion of the epitaxial structure and extends along an entirety of an exposed surface of the epitaxial structure. The method also includes forming a semiconductor-metal compound region on the epitaxial structure. All or some of the modified region is transformed into the semiconductor-metal compound region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Cheng Chen, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen
  • Patent number: 10657852
    Abstract: The present invention relates to a flexible transparent display sheet, and an image display apparatus including the same. The flexible transparent display sheet according to an embodiment of the present disclosure includes: a base disposed in a display area and a connection area; a metal layer formed on the base; an anti-oxide layer formed on a portion of the metal layer; a plurality of solders formed on a portion of the anti-oxide layer; a plurality of light emitters, each of which is connected to each of the plurality of solders; and an insulation layer disposed in the connection area and formed on the anti-oxide layer. Accordingly, a flexible transparent display sheet having an integrally formed power connector may be provided.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 19, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Jungwoon Park, Jeoungan Kim
  • Patent number: 10643892
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: 10553478
    Abstract: Embodiments of the present disclosure may provide a method of forming an integrated circuit (IC) structure, the method including: forming a doped metal layer within a contact opening in an inter-level dielectric (ILD) material on a conductive region, such that the doped metal layer overlies the conductive region, the doped metal layer including a first metal doped with a second metal; and forming a contact to the conductive region within the contact opening of the ILD material by annealing the doped metal layer such that the second metal diffuses into the ILD material to form an interface liner directly between the annealed doped metal layer and the ILD material, the interface liner formed only on sidewalls of the contact opening and in direct contact with the ILD material and only at an interface of the doped metal layer and the ILD material.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Moosung M. Chae
  • Patent number: 10535816
    Abstract: A via structure, a MRAM device using the via structure and a method for fabricating the MRAM device are provided. In the method for fabricating the MRAM device, at first, a first dielectric layer is deposited over a transistor. Then, a contact is formed in the first dielectric layer and electrically connected to the transistor. Thereafter, a metal nitride layer is deposited over the first dielectric layer and the contact. Then, an etch stop layer is deposited over the metal nitride layer. Thereafter, a second dielectric layer is deposited over the etch stop layer. Then, a via structure is formed in the second dielectric layer, the etch stop layer, and the metal nitride layer and landing on the contact. Thereafter, a memory stack is formed over the via structure.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Szu-Ping Tung, Szu-Hua Wu, Shing-Chyang Pan, Meng-Yu Wu
  • Patent number: 10460956
    Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Benjamin V. Fasano, Shidong Li
  • Patent number: 10444576
    Abstract: A drain layer lead line connecting an image signal line and a terminal of an IC driver is interrupted in the middle, and the gap is bridged by bridging ITO that is formed at the same time as pixel ITO. Thus, the difference in the length of the lead lines is adjusted such that the length of the bridging ITO in the lead line connected to the terminal in the center of the IC driver is longer than the length of the bridging ITO in the lead line connected to the terminal in the end of the IC driver to reduce the difference in the wiring resistance of the lead lines due to the difference in the length of the lead lines depending on the location.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 15, 2019
    Assignee: Japan Display Inc.
    Inventor: Takahiro Nagami
  • Patent number: 10431518
    Abstract: A radio frequency integrated circuit (RFIC) device and a method for fabricating same are disclosed. The RFIC device includes: a first semiconductor layer having a first surface, a second surface and a thickness of smaller than 3 ?m; a first dielectric layer on the first surface of the first semiconductor layer; a semiconductor component within the first semiconductor layer and the first dielectric layer; a second dielectric layer on the second surface of the first semiconductor layer, the second dielectric layer having a thickness of smaller than 1 ?m; and a sheet-like heat sink that is formed on the surface of the second dielectric layer opposite to the first semiconductor layer for dissipating heat from the semiconductor component. Efficient dissipation of heat from an RF transistor to a certain extent can be achieved by the RFIC device.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 1, 2019
    Assignee: NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventor: Xiaochuan Wang
  • Patent number: 10361400
    Abstract: An organic light emitting diode display including: a substrate; an organic light emitting diode on the substrate; a capping layer on the organic light emitting diode and including a high refractive layer including an inorganic material having a refractive index that is equal to or greater than about 1.7 and equal to or less than about 6.0; and a thin film encapsulation layer covering the capping layer and the organic light emitting diode, the inorganic material including at least one selected from the group consisting of CuI, thallium iodide (TlI), BaS, Cu2O, CuO, BiI, WO3, TiO2, AgI, CdI2, HgI2, SnI2, PbI2, BiI3, ZnI2, MoO3, Ag2O, CdO, CoO, Pr2O3, SnS, PbS, CdS, CaS, ZnS, ZnTe, PbTe, CdTe, SnSe, PbSe, CdSe, AlAs, GaAs, InAs, GaP, InP, AlP, AlSb, GaSb, and InSb.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won Jong Kim, Dong Chan Kim, Eung Do Kim, Dong Kyu Seo, Da Hea Im, Sang Hoon Yim, Yoon Hyeung Cho, Won Suk Han
  • Patent number: 10354986
    Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Pin Huang, Hsien-Ming Tu, Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai
  • Patent number: 10347594
    Abstract: A semiconductor device includes a wiring, a semiconductor chip above the wiring and a metal block above the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a lower electrode, an upper large electrode and an upper small electrode. The semiconductor chip includes a first portion and a second portion, the first portion being on an upper small electrode side with respect to a centroid of the semiconductor chip, the second portion being on an opposite side of the upper small electrode with respect to the centroid. The lower electrode is connected to the wiring via a lower solder layer. The lower solder layer includes a solder base material and metal particles. A volume ratio of the metal particles occupying the lower solder layer under the second portion is higher than a volume ratio of the metal particles occupying the lower solder layer under the first portion.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 9, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masayuki Kamiya
  • Patent number: 10332837
    Abstract: A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Takeshi Nogami
  • Patent number: 10249546
    Abstract: Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or other types of defects. Reverse decoration can preserve a defect and/or can improve defect detection. A portion of a layer may be removed from a device. A layer also may be added to the device, such as on the defect, and some of the layer may be removed.
    Type: Grant
    Filed: December 24, 2016
    Date of Patent: April 2, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Philip Measor, Robert Danen, Paul MacDonald
  • Patent number: 10224285
    Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 5, 2019
    Assignee: Raytheon Company
    Inventors: Jeffrey R. LaRoche, Eduardo M. Chumbes, Kelly P. Ip, Thomas E. Kazior
  • Patent number: 10204932
    Abstract: An array substrate and a manufacturing method thereof are provided. The array substrate includes a display area (02) and a fan-out area (01) disposed at the periphery of the display area (02), the manufacturing method comprising forming a line pattern (212) disposed in at least one of the display area (02) and the fan-out area (01), wherein forming a line pattern disposed in at least one of the display area and the fan-out area includes the following steps: forming a metal layer (210); forming an intermediate pattern (211) by performing a first patterning process on the metal layer; and forming the line pattern disposed in at least one of the display area (02) and the fan-out area (01) by performing a second patterning process on the intermediate pattern.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Lijuan Yang
  • Patent number: 10199504
    Abstract: Embodiments of the present invention disclose a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which relates to the field of display technology, and solves the problem that the adhesion of the electrode thin film with the adjacent thin film layer in the thin film transistor of the prior art is relatively bad. More specifically, an embodiment of the present invention provides a thin film transistor, comprising a gate, a source, a drain and a buffer layer, the buffer layer is located at one side or two sides of the gate, the source or the drain, the material of the buffer layer is a copper alloy material, the copper alloy material contains nitrogen element or oxygen element, the copper alloy material further contains aluminum element.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: February 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhengliang Li, Qi Yao, Zhanfeng Cao, Bin Zhang, Xiaolong He, Jincheng Gao, Xiangchun Kong, Wei Zhang
  • Patent number: 10177118
    Abstract: To miniaturize metal columns. A semiconductor device includes a metal column (14) that extends in a stretching direction; a polymer layer (16) that surrounds the metal column from a direction crossing the stretching direction; and a guide (12) that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture (20) containing metal particles (22) and polymers (24) in a guide (12); and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer (16) that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column (14) that stretches in a stretching direction of the guide from the metal particles.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 8, 2019
    Assignees: TOHOKU UNIVERSITY, TOSHIBA MEMORY CORPORATION
    Inventors: Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, Kang-Wook Lee
  • Patent number: 10164115
    Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Neville L. Dias, Chia-Hong Jan, Walid M. Hafez, Roman W. Olac-Vaw, Hsu-Yu Chang, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu