Specified Wide Band Gap (1.5ev) Semiconductor Material Other Than Gaasp Or Gaalas Patents (Class 257/76)
  • Patent number: 11876129
    Abstract: Embodiments of the present application disclose a semiconductor structure and a manufacturing method for the semiconductor structure, which solve problems of complicated manufacturing process and poor stability and reliability of existing semiconductor structures. The semiconductor structure includes: a substrate; a channel layer and a barrier layer sequentially superimposed on the substrate, wherein the channel layer and the barrier layer are made of GaN-based materials and an upper surface of the barrier layer is Ga-face; and a p-type GaN-based semiconductor layer formed in a gate region of the barrier layer. An upper surface of the p-type GaN-based semiconductor layer is N-face.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: January 16, 2024
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11837656
    Abstract: To provide a nitride semiconductor device excellent in switching characteristics. A nitride semiconductor device includes: a gallium nitride layer having a first principal surface and a second principal surface located on an opposite side to the first principal surface and having a trench formed from the first principal surface to the second principal surface side; and a field effect transistor formed in the gallium nitride layer, wherein the trench has a first side surface and a second side surface inside the trench, the first side surface is a nitrogen face in the surface layer of which nitrogen atoms are located, the second side surface is a gallium face in the surface layer of which gallium atoms are located, and the field effect transistor has: a gate insulating film formed on the first side surface; and a gate electrode formed in the trench and covering the gate insulating film.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: December 5, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsunori Ueno, Yuki Ohuchi
  • Patent number: 11830940
    Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes: a substrate including a vertical interface; a channel layer disposed outside the vertical interface; and a channel supply layer disposed outside the channel layer; wherein at least one of a vertical two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 28, 2023
    Assignee: GUANGDONG ZHINENG TECHNOLOGIES, CO. LTD.
    Inventor: Zilan Li
  • Patent number: 11822162
    Abstract: A wideband terahertz modulator based on gradual openings, which belongs to the technical field of electromagnetic functional devices, includes: a semiconductor substrate; an epitaxial layer provided on the semiconductor substrate; a modulation units array, a positive voltage loading electrode and a negative voltage loading electrode which are provided on the epitaxial layer; wherein each modulation unit in the modulation units array comprises a disconnected H-shaped structure, a metal electrode located below an end of the opening of the disconnected H-shaped structure, and a semiconductor doped heterostructure located below the opening of the disconnected H-shaped structure; wherein in the disconnected H-shaped structures, adjacent modulation units have different opening positions; in a same row, the opening positions are linearly distributed and have a certain slope, and inclination slopes of the opening positions of two adjacent rows are opposite.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: November 21, 2023
    Assignee: University of Electronic Science and Technology of China
    Inventors: Yaxin Zhang, Shixiong Liang, Xilin Zhang, Ziqiang Yang Yang, Zhihong Feng
  • Patent number: 11726235
    Abstract: Embodiments are disclosed for an optical waveguide display configured for use with a near-eye display (NED) device. In an embodiment the waveguide display includes a light-transmissive substrate and an optical coupling element configured to input light rays to the substrate or output light rays from the substrate, the optical coupling element configured to deflect a plurality of wavelengths of an incident light ray collinearly for propagation within the light-transmissive substrate through total internal reflection (TIR). The optical coupling element can include a pattern of nano-structures that collectively form a metasurface on the substrate.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: August 15, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Eliezer Glik, Hagar Edelstain, Bernard C. Kress
  • Patent number: 11728388
    Abstract: A semiconductor device including an active structure on a substrate, the active structure including silicon germanium patterns and silicon patterns alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on sidewalls of the active structure that face in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source/drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction that is perpendicular to the first direction, wherein the silicon germanium patterns are silicon rich-silicon germanium.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keunhwi Cho, Byounghak Hong, Myunggil Kang
  • Patent number: 11716026
    Abstract: According to one configuration, an inductor device comprises: core material and one or more electrically conductive paths. The core material is magnetically permeable and surrounds (envelops) the one or more electrically conductive paths. Each of the electrically conductive paths extends through the core material of the inductor device from a first end of the inductor device to a second end of the inductor device. The magnetically permeable core material is operative to confine (guide, carry, convey, localize, etc.) respective magnetic flux generated from current flowing through a respective electrically conductive path. The core material stores the magnetic flux energy (i.e., first magnetic flux) generated from the current flowing through the first electrically conductive path.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: August 1, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Kennith K. Leong, Matthias J. Kasper, Luca Peluso, Gerald Deboy
  • Patent number: 11705512
    Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: July 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Yi-Chung Sheng, Sheng-Yuan Hsueh, Chih-Kai Kang, Guan-Kai Huang, Chien-Liang Wu
  • Patent number: 11677020
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1?x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1?x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1?x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 13, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu Kato, Yosuke Kajiwara, Akira Mukai, Aya Shindome, Hiroshi Ono, Masahiko Kuraguchi
  • Patent number: 11670710
    Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: June 6, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
  • Patent number: 11670687
    Abstract: A gallium nitride substrate comprising a first main surface and a second main surface opposite thereto, wherein the first main surface is a non-polar or semi-polar plane, a dislocation density measured by a room-temperature cathode luminescence method in the first main surface is 1×104 cm?2 or less, and an averaged dislocation density measured by a room-temperature cathode luminescence method in an optional square region sizing 250 ?m×250 ?m in the first main plan is 1×106 cm?2 or less.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: June 6, 2023
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yusuke Tsukada, Shuichi Kubo, Kazunori Kamada, Hideo Fujisawa, Tatsuhiro Ohata, Hirotaka Ikeda, Hajime Matsumoto, Yutaka Mikawa
  • Patent number: 11658235
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first region, and a first insulating layer. The first electrode includes a first electrode portion. The first region contains Ga and N. The first region includes a first subregion, a second subregion, and a third subregion. The first subregion and the third subregion contain at least one first element selected from the group consisting of Ar, B, P, N, and Fe. The first subregion is located between the first electrode portion and the second subregion in a first direction. The second subregion does not contain the first element, or concentration of the first element in the second subregion is lower than concentration of the first element in the first subregion and lower than concentration of the first element in the third subregion. The first insulating layer is provided between the first electrode and the first region.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: May 23, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Miki Yumoto, Hiroshi Ono
  • Patent number: 11646310
    Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: May 9, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Terry Alcorn, Daniel Namishia, Fabian Radulescu
  • Patent number: 11616167
    Abstract: A nitride semiconductor light-emitting element includes an n-type cladding layer including n-type AlGaN, and a multiple quantum well layer including a barrier layer that includes AlGaN and is located on the n-type cladding layer side, wherein the nitride semiconductor light-emitting element further comprises a trigger layer that is located between the n-type cladding layer and the barrier layer and comprises Si, wherein a plural V-pits starting from dislocations in the n-type cladding layer and ending in the multiple quantum well are formed in the n-type cladding layer and the multiple quantum well layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 28, 2023
    Assignee: Nikkiso Co., Ltd.
    Inventors: Cyril Pernot, Yusuke Matsukura, Yuta Furusawa, Mitsugu Wada
  • Patent number: 11605754
    Abstract: A transfer method includes providing a first light emitting diode on a first substrate, performing a partial laser liftoff of the first light emitting diode from the first substrate, laser bonding the first light emitting diode to the backplane after performing the partial laser liftoff, and separating the first substrate from the first light emitting diode after the laser bonding.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: March 14, 2023
    Assignee: NANOSYS, INC.
    Inventors: Timothy Gallagher, Anusha Pokhriyal
  • Patent number: 11600614
    Abstract: Various integrated circuits formed using gallium nitride and other materials are described. In one example, an integrated circuit includes a first integrated device formed over a first semiconductor structure in a first region of the integrated circuit, a second integrated device formed over a second semiconductor structure in a second region of the integrated circuit, and a passive component formed over a third region of the integrated circuit, between the first region and the second region. The third region comprises an insulating material, which can be glass in some cases. Further, the passive component can be formed over the glass in the third region. The integrated circuit is designed to avoid electromagnetic coupling between the passive component, during operation of the integrated circuit, and interfacial parasitic conductive layers existing in the first and second semiconductor structures, to improve performance.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: March 7, 2023
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Douglas Carlson, Timothy E. Boles, Wayne Mack Struble
  • Patent number: 11588047
    Abstract: The present disclosure discloses a semiconductor component and a method for forming the semiconductor component. The semiconductor component includes a substrate, a III-V layer, a doped III-V layer, a gate contact, a first field plate, and a second field plate. The gate contact has first and second sides away from the doped III-V layer. The first field plate has first and second sides, and the first side is closer to the second side of the gate contact than the second side. The second field plate has first and second sides, and the first side is closer to the second side of the gate contact than the second side. The first field plate is closer to the doped III-V layer than the second field plate and the first side and the second side of the gate contact.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: February 21, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Hao Li, Haoning Zheng, Anbang Zhang
  • Patent number: 11581310
    Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 11569182
    Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 31, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Daniel Piedra, James G. Fiorenza, Puneet Srivastava, Andrew Proudman, Kenneth Flanders, Denis Michael Murphy, Leslie P. Green, Peter R. Stubler
  • Patent number: 11555257
    Abstract: A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride. A normal line to the upper surface has an off-angle of 2.0° or less with respect to <0001> direction of the crystal of the nitride of the group 13 element.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: January 17, 2023
    Assignee: NGK INSULATORS, LTD.
    Inventors: Takayuki Hirao, Hirokazu Nakanishi, Mikiya Ichimura, Takanao Shimodaira, Masahiro Sakai, Takashi Yoshino
  • Patent number: 11552187
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: January 10, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Ming-Hua Chang, Shui-Yen Lu
  • Patent number: 11500275
    Abstract: A light emitting device includes: at least one semiconductor laser element; and a light-transmissive member including: an upper surface, a lower surface, and a light-transmissive region through which laser light emitted from the at least one semiconductor laser element is transmitted from the lower surface to the upper surface, wherein: at least the light-transmissive region is made of sapphire, the light-transmissive member includes an incident surface on which the laser light is incident, the incident surface being an a-plane of the sapphire, and the light-transmissive member is oriented such that a polarization direction of the laser light incident on the incident surface is parallel or perpendicular to a c-axis of the sapphire in a top view.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 15, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Kazuma Kozuru
  • Patent number: 11485906
    Abstract: An ?-sialon phosphor particle containing Eu. At least one minute recess is formed on a surface of the ?-sialon phosphor particle. The ?-sialon phosphor particle is preferably produced by undergoing a raw material mixing step, a heating step, a pulverizing step, and an acid treatment step.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 1, 2022
    Assignee: DENKA COMPANY LIMITED
    Inventors: Tomohiro Nomiyama, Yusuke Takeda, Marina Takamura, Tatsuya Okuzono, Masaru Miyazaki, Shintaro Watanabe
  • Patent number: 11456377
    Abstract: The semiconductor device includes: a substrate; a semiconductor layer disposed on one side of the substrate, the semiconductor layer including a channel layer and a barrier layer, and a two-dimensional electron gas being formed at an interface between the channel layer and the barrier layer; a source, a gate, and a drain disposed on one side of the semiconductor layer away from the substrate; and at least two drain junction terminals located on the side of the semiconductor layer away from the substrate and disposed at intervals between the gate and the drain, the at least two drain junction terminals being electrically connected to the drain respectively. In the embodiments of the present application, the on-resistance of the device can be reduced while the current collapse phenomenon is eliminated, thereby improving the long-term reliability of the device.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 27, 2022
    Assignee: GPOWER SEMICONDUCTOR INC.
    Inventor: Chuanjia Wu
  • Patent number: 11450527
    Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Willy Rachmady, Marc C. French, Seung Hoon Sung, Jack T. Kavalieros, Matthew V. Metz, Ashish Agrawal
  • Patent number: 11444193
    Abstract: A drift layer and a source region have a first conductivity type. A base region has a second conductivity type. A first trench penetrates the source region and the base region. A gate electrode is provided in the first trench through a gate insulation film. A first relaxation region is disposed below the first trench, and has the second conductivity type. A source pad electrode is electrically connected to the first relaxation region. A gate pad electrode is disposed in a non-element region. An impurity region is disposed in the non-element region, is provided on the drift layer, and has the first conductivity type. A second trench penetrates the impurity region. A second relaxation region is disposed below the second trench, and has the second conductivity type.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 13, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takaaki Tominaga, Yutaka Fukui
  • Patent number: 11437773
    Abstract: A wavelength conversion device including a cavity that includes an RAMO4 crystal having a single crystal represented by a first general formula of RAMO4, a laser crystal, and a mirror, in which in the first general formula, R represents one or a plurality of trivalent elements selected from the group consisting of Sc, In, Y, and lanthanoid elements, A represents one or a plurality of trivalent elements selected from the group consisting of Fe (III), Ga, and Al, and M represents one or a plurality of divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn, and Cd.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: September 6, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoya Ryoki, Kentaro Miyano, Hiroshi Ohno, Akihiko Ishibashi, Masaki Nobuoka
  • Patent number: 11430929
    Abstract: A light emitting device including a first light emitting part including a first n-type semiconductor layer, a first active layer, and a first p-type semiconductor layer, a second light emitting part disposed on a first surface of the first light emitting part, and including a second n-type semiconductor layer, a second active layer, and a second p-type semiconductor layer, the second n-type semiconductor layer having a first surface and a second surface opposing the first surface, a third light emitting part disposed on a first surface of the second light emitting part, and including a third n-type semiconductor layer, a third active layer, and a third p-type semiconductor layer, a first contact structure contacting the first surface of the second n-type semiconductor layer, and a second contact structure contacting the second surface of the second n-type semiconductor layer.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 30, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Chang Yeon Kim
  • Patent number: 11424356
    Abstract: A transistor having: a semiconductor; a first electrode in contact with the semiconductor; a second electrode in contact with the semiconductor; and a control electrode, disposed between the first electrode and the second electrode, for controlling a flow of carriers in a channel in the semiconductor between the first electrode and the second electrode. A first electric field is produced in the channel in response to an electrical voltage applied between the first electrode and the second electrode. A field plate, comprising a resistive material, is disposed over the channel. A voltage source is connected across portions of the resistive field plate material for producing second electric field across such portions of the resistor, such second electric field being coupled into the channel to modify one or more peaks of the first electric field in the channel.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 23, 2022
    Assignee: Raytheon Company
    Inventors: Brian Thomas Appleton, Jr., Casey Alan Howsare
  • Patent number: 11417523
    Abstract: Methods of forming a p-type IV-doped III-VI semiconductor are provided which comprise exposing a substrate to a vapor composition comprising a group III precursor comprising a group III element, a group VI precursor comprising a group VI element, and a group IV precursor comprising a group IV element, under conditions to form a p-type IV-doped III-VI semiconductor via metalorganic chemical vapor deposition (MOCVD) on the substrate. Embodiments make use of a flow ratio defined as a flow rate of the group VI precursor to a flow rate of the group III precursor wherein the flow ratio is below an inversion flow ratio value for the IV-doped III-VI semiconductor.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 16, 2022
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 11417799
    Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of: providing a substrate, and forming a plurality of die sized semiconductor structures on the substrate. The method also includes the steps of providing a receiving plate having an elastomeric polymer layer, placing the substrate and the receiving plate in physical contact with an adhesive force applied by the elastomeric polymer layer, and performing a laser lift-off (LLO) process by directing a uniform laser beam through the substrate to the semiconductor layer at an interface with the substrate to lift off the semiconductor structures onto the elastomeric polymer layer. During the laser lift-off (LLO) process the elastomeric polymer layer functions as a shock absorber to reduce momentum transfer, and as an adhesive surface to hold the semiconductor structures in place on the receiving plate.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 16, 2022
    Assignees: SemiLEDs Corporation, Shin-Etsu Chemical Co., Ltd.
    Inventors: Chen-Fu Chu, Shih-Kai Chan, Yi-Feng Shih, David Trung Doan, Trung Tri Doan, Yoshinori Ogawa, Kohei Otake, Kazunori Kondo, Keiji Ohori, Taichi Kitagawa, Nobuaki Matsumoto, Toshiyuki Ozai, Shuhei Ueda
  • Patent number: 11410950
    Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 9, 2022
    Assignee: Infineon Technologies AG
    Inventors: Gert Pfahl, Daniel Bolowski, Marian Sebastian Broll, Michael Kreuz, Evelyn Napetschnig, Holger Schulze, Stefan Woehlert
  • Patent number: 11404407
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer above the substrate, a Schottky barrier material on the epitaxial layer, a Schottky metal contact extending into the Schottky barrier material, a fin structure that extends in a first direction, a first angled implant in a first side of the fin structure that has an orientation that is orthogonal to the first direction, and a second angled implant in a second side of the fin structure that has an orientation that is orthogonal to the first direction. The second side is opposite to the first side. A first cathode region and a second cathode region are coupled by parts of the first angled implant and the second angled implant that extend in the first direction.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Paul Fischer, Walid Hafez
  • Patent number: 11387397
    Abstract: A method for making light emitting device LED arrays includes the steps of providing a plurality of LEDs having a desired configuration (e.g., VLED, FCLED, PLED); attaching the LEDs to a carrier substrate and to a temporary substrate; forming one or more metal layers and one or more insulator layers configured to electrically connect the LEDs to form a desired circuitry; and separating the LEDs along with the layered metal layers and insulator layers that form the desired circuitry from the carrier substrate and the temporary substrate.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: July 12, 2022
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: David Trung Doan, Trung Tri Doan
  • Patent number: 11380801
    Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2 eV?1 to about 5e11 cm?2 eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 5, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Jianheng Li, Lai Zhao, Yujia Zhai, Soo Young Choi
  • Patent number: 11380806
    Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11380767
    Abstract: A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: July 5, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
  • Patent number: 11373873
    Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: June 28, 2022
    Assignee: Power Integrations, Inc.
    Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
  • Patent number: 11362137
    Abstract: The disclosure relates to an optoelectronic device comprising: a plurality of separate first electrodes that extend longitudinally in parallel to an axis A1, each first electrode being formed of a longitudinal conductive portion and a conductive nucleation strip, the longitudinal conductive portion having an electrical resistance lower than that of the conductive nucleation strip; a plurality of diodes; at least one intermediate insulating layer covering the first electrodes; and a plurality of separate second electrodes in the form of transparent conductive strips that extend longitudinally in contact with second doped portions, and are electrically insulated from the first electrodes by means of the intermediate insulating layer, parallel to an axis A2, the axis A2 not being parallel to axis A1.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 14, 2022
    Assignee: Aledia
    Inventors: Vincent Beix, Erwan Dornel
  • Patent number: 11362174
    Abstract: A method of manufacturing semiconductor device of an embodiment includes performing a first ion implantation implanting at least one element selected from a group consisting of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zinc (Zn), cadmium (Cd), silicon (Si), germanium (Ge), and tin (Sn) into a nitride semiconductor layer; performing a second ion implantation implanting nitrogen (N) into the nitride semiconductor layer; performing a third ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a covering layer on a surface of the nitride semiconductor layer after the first ion implantation, the second ion implantation, and the third ion implantation; performing a first heat treatment after forming the covering layer; removing the covering layer after the first heat treatment; and performing a second heat treatment after removing the covering layer.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 14, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu
  • Patent number: 11355593
    Abstract: A semiconductor device comprises: a nitride semiconductor layer; an oxide insulating film formed to contact the nitride semiconductor layer; and a gate electrode formed to contact the oxide insulating film and made of metal nitride in a crystal orientation including at least one of the (200) orientation and the (220) orientation.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 7, 2022
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takatomi Izumi, Junya Nishii, Yuhei Ikemoto
  • Patent number: 11342439
    Abstract: A semiconductor device and a semiconductor structure are disclosed. The semiconductor device includes a substrate, a first III-V compound layer, a second III-V compound layer, a source, a drain and a gate stack structure. The first III-V compound layer is disposed on the substrate. The second III-V compound layer is disposed on the first III-V compound layer. The source and the drain are disposed on opposite sidewall boundaries of the second III-V compound layer. The gate stack structure is disposed on the second III-V compound layer. The gate stack structure includes a first gate and a second gate. The first gate is disposed on the second III-V compound layer. The second gate is disposed on and electrically isolated from the first gate. The second gate is electrically coupled to the source.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 24, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Vivek Ningaraju, Po-An Chen
  • Patent number: 11342438
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 24, 2022
    Inventors: Steven R. J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Patent number: 11342443
    Abstract: An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 24, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Abhishek Banerjee
  • Patent number: 11328924
    Abstract: Provided is a method for manufacturing a semiconductor wafer and a semiconductor wafer. The method includes: disposing a sacrificial layer on a first surface and a second surface of a patterned substrate, the patterned substrate comprising the first surface and the second surface having different normal directions; exposing the first surface by removing the first portion of the sacrificial layer disposed on the first surface; growing an original nitride buffer layer on the first surface and the second portion of the sacrificial layer; partially lifting off the second portion of the sacrificial layer disposed on the second surface such that at least one sub-portion of the second portion of the sacrificial layer remains on the second surface of the patterned substrate; and growing an epitaxial layer on the original nitride buffer layer, where a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: May 10, 2022
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Kaixuan Chen, Zhiwei Lin, Liyan Huo, Xiangjing Zhuo, Gang Yao, Aimin Wang
  • Patent number: 11322310
    Abstract: A photochemical electrode includes: an electrically conductive layer; and a photoexcitation material layer provided over the electrically conductive layer and including a photoexcitation material, wherein the photoexcitation material layer is one of a first photoexcitation material layer in which a potential of the conduction band minimum decreases from a second surface opposite to a first surface on the side of the electrically conductive layer toward the first surface and a second photoexcitation material layer in which a potential of the valence band maximum decreases from the second surface toward the first surface.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: May 3, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Yoshihiko Imanaka, Hideyuki Amada, Toshio Manabe, Toshihisa Anazawa, Sachio Ido, Naoki Awaji
  • Patent number: 11316041
    Abstract: A semiconductor device (1) includes a substrate (2), an electron transit layer (4) disposed on the substrate (2), and an electron supply layer (5) disposed on the electron supply layer (4). The electron transit layer (4) includes a conductive path forming layer (43) in contact with the electron supply layer (5), a first semiconductor region (first nitride semiconductor layer) (41) containing an acceptor-type impurity, and a second semiconductor region (second nitride semiconductor layer) (42) disposed at a position closer to the conductive path forming layer (43) than the first semiconductor region (41) and containing an acceptor-type impurity. The first semiconductor region (41) has a higher acceptor density than the second semiconductor region (42).
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 26, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Taketoshi Tanaka
  • Patent number: 11316007
    Abstract: An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer. The nucleation layer is disposed on the substrate, and the nucleation layer consists of a plurality of regions in a thickness direction, wherein a chemical composition of the region is Al(1?x)InxN, where 0?x?1. The buffer layer is disposed on the nucleation layer, and a thickness of the nucleation layer is less than a thickness of the buffer layer. The nitride layer is disposed on the buffer layer, wherein a roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 26, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen-Lun Huang, Ying-Ru Shih
  • Patent number: 11316018
    Abstract: A compound semiconductor substrate includes a SiC (silicon carbide) layer, a AlN (aluminum nitride) buffer layer formed on the SiC layer, an Al (aluminum) nitride semiconductor layer formed on the AlN buffer layer, a composite layer formed on the Al nitride semiconductor layer, a GaN (gallium nitride) layer as an electron transition layer formed on the composite layer, and an Al nitride semiconductor layer as a barrier layer formed on the GaN layer. The composite layer includes C—GaN layers stacked in a vertical direction, and an AlN layer formed between the C—GaN layers.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 26, 2022
    Assignee: Air Water Inc.
    Inventors: Mitsuhisa Narukawa, Sumito Ouchi, Hiroki Suzuki, Keisuke Kawamura
  • Patent number: RE49167
    Abstract: A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 9, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Van Mieczkowski, Jonathan Young, Qingchun Zhang, John Williams Palmour