Specified Wide Band Gap (1.5ev) Semiconductor Material Other Than Gaasp Or Gaalas Patents (Class 257/76)
  • Patent number: 11569182
    Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 31, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Daniel Piedra, James G. Fiorenza, Puneet Srivastava, Andrew Proudman, Kenneth Flanders, Denis Michael Murphy, Leslie P. Green, Peter R. Stubler
  • Patent number: 11555257
    Abstract: A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride. A normal line to the upper surface has an off-angle of 2.0° or less with respect to <0001> direction of the crystal of the nitride of the group 13 element.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: January 17, 2023
    Assignee: NGK INSULATORS, LTD.
    Inventors: Takayuki Hirao, Hirokazu Nakanishi, Mikiya Ichimura, Takanao Shimodaira, Masahiro Sakai, Takashi Yoshino
  • Patent number: 11552187
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: January 10, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Ming-Hua Chang, Shui-Yen Lu
  • Patent number: 11500275
    Abstract: A light emitting device includes: at least one semiconductor laser element; and a light-transmissive member including: an upper surface, a lower surface, and a light-transmissive region through which laser light emitted from the at least one semiconductor laser element is transmitted from the lower surface to the upper surface, wherein: at least the light-transmissive region is made of sapphire, the light-transmissive member includes an incident surface on which the laser light is incident, the incident surface being an a-plane of the sapphire, and the light-transmissive member is oriented such that a polarization direction of the laser light incident on the incident surface is parallel or perpendicular to a c-axis of the sapphire in a top view.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 15, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Kazuma Kozuru
  • Patent number: 11485906
    Abstract: An ?-sialon phosphor particle containing Eu. At least one minute recess is formed on a surface of the ?-sialon phosphor particle. The ?-sialon phosphor particle is preferably produced by undergoing a raw material mixing step, a heating step, a pulverizing step, and an acid treatment step.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 1, 2022
    Assignee: DENKA COMPANY LIMITED
    Inventors: Tomohiro Nomiyama, Yusuke Takeda, Marina Takamura, Tatsuya Okuzono, Masaru Miyazaki, Shintaro Watanabe
  • Patent number: 11456377
    Abstract: The semiconductor device includes: a substrate; a semiconductor layer disposed on one side of the substrate, the semiconductor layer including a channel layer and a barrier layer, and a two-dimensional electron gas being formed at an interface between the channel layer and the barrier layer; a source, a gate, and a drain disposed on one side of the semiconductor layer away from the substrate; and at least two drain junction terminals located on the side of the semiconductor layer away from the substrate and disposed at intervals between the gate and the drain, the at least two drain junction terminals being electrically connected to the drain respectively. In the embodiments of the present application, the on-resistance of the device can be reduced while the current collapse phenomenon is eliminated, thereby improving the long-term reliability of the device.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 27, 2022
    Assignee: GPOWER SEMICONDUCTOR INC.
    Inventor: Chuanjia Wu
  • Patent number: 11450527
    Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Willy Rachmady, Marc C. French, Seung Hoon Sung, Jack T. Kavalieros, Matthew V. Metz, Ashish Agrawal
  • Patent number: 11444193
    Abstract: A drift layer and a source region have a first conductivity type. A base region has a second conductivity type. A first trench penetrates the source region and the base region. A gate electrode is provided in the first trench through a gate insulation film. A first relaxation region is disposed below the first trench, and has the second conductivity type. A source pad electrode is electrically connected to the first relaxation region. A gate pad electrode is disposed in a non-element region. An impurity region is disposed in the non-element region, is provided on the drift layer, and has the first conductivity type. A second trench penetrates the impurity region. A second relaxation region is disposed below the second trench, and has the second conductivity type.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 13, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takaaki Tominaga, Yutaka Fukui
  • Patent number: 11437773
    Abstract: A wavelength conversion device including a cavity that includes an RAMO4 crystal having a single crystal represented by a first general formula of RAMO4, a laser crystal, and a mirror, in which in the first general formula, R represents one or a plurality of trivalent elements selected from the group consisting of Sc, In, Y, and lanthanoid elements, A represents one or a plurality of trivalent elements selected from the group consisting of Fe (III), Ga, and Al, and M represents one or a plurality of divalent elements selected from the group consisting of Mg, Mn, Fe (II), Co, Cu, Zn, and Cd.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: September 6, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoya Ryoki, Kentaro Miyano, Hiroshi Ohno, Akihiko Ishibashi, Masaki Nobuoka
  • Patent number: 11430929
    Abstract: A light emitting device including a first light emitting part including a first n-type semiconductor layer, a first active layer, and a first p-type semiconductor layer, a second light emitting part disposed on a first surface of the first light emitting part, and including a second n-type semiconductor layer, a second active layer, and a second p-type semiconductor layer, the second n-type semiconductor layer having a first surface and a second surface opposing the first surface, a third light emitting part disposed on a first surface of the second light emitting part, and including a third n-type semiconductor layer, a third active layer, and a third p-type semiconductor layer, a first contact structure contacting the first surface of the second n-type semiconductor layer, and a second contact structure contacting the second surface of the second n-type semiconductor layer.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 30, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Chang Yeon Kim
  • Patent number: 11424356
    Abstract: A transistor having: a semiconductor; a first electrode in contact with the semiconductor; a second electrode in contact with the semiconductor; and a control electrode, disposed between the first electrode and the second electrode, for controlling a flow of carriers in a channel in the semiconductor between the first electrode and the second electrode. A first electric field is produced in the channel in response to an electrical voltage applied between the first electrode and the second electrode. A field plate, comprising a resistive material, is disposed over the channel. A voltage source is connected across portions of the resistive field plate material for producing second electric field across such portions of the resistor, such second electric field being coupled into the channel to modify one or more peaks of the first electric field in the channel.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 23, 2022
    Assignee: Raytheon Company
    Inventors: Brian Thomas Appleton, Jr., Casey Alan Howsare
  • Patent number: 11417799
    Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of: providing a substrate, and forming a plurality of die sized semiconductor structures on the substrate. The method also includes the steps of providing a receiving plate having an elastomeric polymer layer, placing the substrate and the receiving plate in physical contact with an adhesive force applied by the elastomeric polymer layer, and performing a laser lift-off (LLO) process by directing a uniform laser beam through the substrate to the semiconductor layer at an interface with the substrate to lift off the semiconductor structures onto the elastomeric polymer layer. During the laser lift-off (LLO) process the elastomeric polymer layer functions as a shock absorber to reduce momentum transfer, and as an adhesive surface to hold the semiconductor structures in place on the receiving plate.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 16, 2022
    Assignees: SemiLEDs Corporation, Shin-Etsu Chemical Co., Ltd.
    Inventors: Chen-Fu Chu, Shih-Kai Chan, Yi-Feng Shih, David Trung Doan, Trung Tri Doan, Yoshinori Ogawa, Kohei Otake, Kazunori Kondo, Keiji Ohori, Taichi Kitagawa, Nobuaki Matsumoto, Toshiyuki Ozai, Shuhei Ueda
  • Patent number: 11417523
    Abstract: Methods of forming a p-type IV-doped III-VI semiconductor are provided which comprise exposing a substrate to a vapor composition comprising a group III precursor comprising a group III element, a group VI precursor comprising a group VI element, and a group IV precursor comprising a group IV element, under conditions to form a p-type IV-doped III-VI semiconductor via metalorganic chemical vapor deposition (MOCVD) on the substrate. Embodiments make use of a flow ratio defined as a flow rate of the group VI precursor to a flow rate of the group III precursor wherein the flow ratio is below an inversion flow ratio value for the IV-doped III-VI semiconductor.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 16, 2022
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 11410950
    Abstract: A semiconductor substrate has a bond pad. The bond pad includes a layer of an aluminum alloy having a chemical composition including at least 0.3% by weight of at least one of Zn, Mg, Sc, Zr, Ti, Ag and/or Mn, with the balance being at least Al and incidental impurities.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 9, 2022
    Assignee: Infineon Technologies AG
    Inventors: Gert Pfahl, Daniel Bolowski, Marian Sebastian Broll, Michael Kreuz, Evelyn Napetschnig, Holger Schulze, Stefan Woehlert
  • Patent number: 11404407
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer above the substrate, a Schottky barrier material on the epitaxial layer, a Schottky metal contact extending into the Schottky barrier material, a fin structure that extends in a first direction, a first angled implant in a first side of the fin structure that has an orientation that is orthogonal to the first direction, and a second angled implant in a second side of the fin structure that has an orientation that is orthogonal to the first direction. The second side is opposite to the first side. A first cathode region and a second cathode region are coupled by parts of the first angled implant and the second angled implant that extend in the first direction.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Paul Fischer, Walid Hafez
  • Patent number: 11387397
    Abstract: A method for making light emitting device LED arrays includes the steps of providing a plurality of LEDs having a desired configuration (e.g., VLED, FCLED, PLED); attaching the LEDs to a carrier substrate and to a temporary substrate; forming one or more metal layers and one or more insulator layers configured to electrically connect the LEDs to form a desired circuitry; and separating the LEDs along with the layered metal layers and insulator layers that form the desired circuitry from the carrier substrate and the temporary substrate.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: July 12, 2022
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: David Trung Doan, Trung Tri Doan
  • Patent number: 11380801
    Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2 eV?1 to about 5e11 cm?2 eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 5, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Jianheng Li, Lai Zhao, Yujia Zhai, Soo Young Choi
  • Patent number: 11380806
    Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11380767
    Abstract: A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: July 5, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
  • Patent number: 11373873
    Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: June 28, 2022
    Assignee: Power Integrations, Inc.
    Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
  • Patent number: 11362174
    Abstract: A method of manufacturing semiconductor device of an embodiment includes performing a first ion implantation implanting at least one element selected from a group consisting of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zinc (Zn), cadmium (Cd), silicon (Si), germanium (Ge), and tin (Sn) into a nitride semiconductor layer; performing a second ion implantation implanting nitrogen (N) into the nitride semiconductor layer; performing a third ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a covering layer on a surface of the nitride semiconductor layer after the first ion implantation, the second ion implantation, and the third ion implantation; performing a first heat treatment after forming the covering layer; removing the covering layer after the first heat treatment; and performing a second heat treatment after removing the covering layer.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 14, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Shimizu
  • Patent number: 11362137
    Abstract: The disclosure relates to an optoelectronic device comprising: a plurality of separate first electrodes that extend longitudinally in parallel to an axis A1, each first electrode being formed of a longitudinal conductive portion and a conductive nucleation strip, the longitudinal conductive portion having an electrical resistance lower than that of the conductive nucleation strip; a plurality of diodes; at least one intermediate insulating layer covering the first electrodes; and a plurality of separate second electrodes in the form of transparent conductive strips that extend longitudinally in contact with second doped portions, and are electrically insulated from the first electrodes by means of the intermediate insulating layer, parallel to an axis A2, the axis A2 not being parallel to axis A1.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 14, 2022
    Assignee: Aledia
    Inventors: Vincent Beix, Erwan Dornel
  • Patent number: 11355593
    Abstract: A semiconductor device comprises: a nitride semiconductor layer; an oxide insulating film formed to contact the nitride semiconductor layer; and a gate electrode formed to contact the oxide insulating film and made of metal nitride in a crystal orientation including at least one of the (200) orientation and the (220) orientation.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 7, 2022
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takatomi Izumi, Junya Nishii, Yuhei Ikemoto
  • Patent number: 11342443
    Abstract: An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 24, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Abhishek Banerjee
  • Patent number: 11342438
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 24, 2022
    Inventors: Steven R. J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Patent number: 11342439
    Abstract: A semiconductor device and a semiconductor structure are disclosed. The semiconductor device includes a substrate, a first III-V compound layer, a second III-V compound layer, a source, a drain and a gate stack structure. The first III-V compound layer is disposed on the substrate. The second III-V compound layer is disposed on the first III-V compound layer. The source and the drain are disposed on opposite sidewall boundaries of the second III-V compound layer. The gate stack structure is disposed on the second III-V compound layer. The gate stack structure includes a first gate and a second gate. The first gate is disposed on the second III-V compound layer. The second gate is disposed on and electrically isolated from the first gate. The second gate is electrically coupled to the source.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 24, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Vivek Ningaraju, Po-An Chen
  • Patent number: 11328924
    Abstract: Provided is a method for manufacturing a semiconductor wafer and a semiconductor wafer. The method includes: disposing a sacrificial layer on a first surface and a second surface of a patterned substrate, the patterned substrate comprising the first surface and the second surface having different normal directions; exposing the first surface by removing the first portion of the sacrificial layer disposed on the first surface; growing an original nitride buffer layer on the first surface and the second portion of the sacrificial layer; partially lifting off the second portion of the sacrificial layer disposed on the second surface such that at least one sub-portion of the second portion of the sacrificial layer remains on the second surface of the patterned substrate; and growing an epitaxial layer on the original nitride buffer layer, where a crystal surface of the epitaxial layer grows along a normal direction of the patterned substrate.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: May 10, 2022
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Kaixuan Chen, Zhiwei Lin, Liyan Huo, Xiangjing Zhuo, Gang Yao, Aimin Wang
  • Patent number: 11322310
    Abstract: A photochemical electrode includes: an electrically conductive layer; and a photoexcitation material layer provided over the electrically conductive layer and including a photoexcitation material, wherein the photoexcitation material layer is one of a first photoexcitation material layer in which a potential of the conduction band minimum decreases from a second surface opposite to a first surface on the side of the electrically conductive layer toward the first surface and a second photoexcitation material layer in which a potential of the valence band maximum decreases from the second surface toward the first surface.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: May 3, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Yoshihiko Imanaka, Hideyuki Amada, Toshio Manabe, Toshihisa Anazawa, Sachio Ido, Naoki Awaji
  • Patent number: 11316007
    Abstract: An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer. The nucleation layer is disposed on the substrate, and the nucleation layer consists of a plurality of regions in a thickness direction, wherein a chemical composition of the region is Al(1?x)InxN, where 0?x?1. The buffer layer is disposed on the nucleation layer, and a thickness of the nucleation layer is less than a thickness of the buffer layer. The nitride layer is disposed on the buffer layer, wherein a roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 26, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen-Lun Huang, Ying-Ru Shih
  • Patent number: 11316041
    Abstract: A semiconductor device (1) includes a substrate (2), an electron transit layer (4) disposed on the substrate (2), and an electron supply layer (5) disposed on the electron supply layer (4). The electron transit layer (4) includes a conductive path forming layer (43) in contact with the electron supply layer (5), a first semiconductor region (first nitride semiconductor layer) (41) containing an acceptor-type impurity, and a second semiconductor region (second nitride semiconductor layer) (42) disposed at a position closer to the conductive path forming layer (43) than the first semiconductor region (41) and containing an acceptor-type impurity. The first semiconductor region (41) has a higher acceptor density than the second semiconductor region (42).
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 26, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Taketoshi Tanaka
  • Patent number: 11316018
    Abstract: A compound semiconductor substrate includes a SiC (silicon carbide) layer, a AlN (aluminum nitride) buffer layer formed on the SiC layer, an Al (aluminum) nitride semiconductor layer formed on the AlN buffer layer, a composite layer formed on the Al nitride semiconductor layer, a GaN (gallium nitride) layer as an electron transition layer formed on the composite layer, and an Al nitride semiconductor layer as a barrier layer formed on the GaN layer. The composite layer includes C—GaN layers stacked in a vertical direction, and an AlN layer formed between the C—GaN layers.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 26, 2022
    Assignee: Air Water Inc.
    Inventors: Mitsuhisa Narukawa, Sumito Ouchi, Hiroki Suzuki, Keisuke Kawamura
  • Patent number: 11309455
    Abstract: A layer of a crystal of a nitride of a group 13 element selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof includes an upper surface and a bottom surface. The upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part, and the high-luminance light-emitting part has a portion extending along an m-plane of the crystal of the nitride of the group 13 element, when the upper surface is observed by cathode luminescence. The upper surface has an arithmetic average roughness Ra of 0.05 nm or more and 1.0 nm or less.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 19, 2022
    Assignee: NGK INSULATORS, LTD.
    Inventors: Takayuki Hirao, Hirokazu Nakanishi, Mikiya Ichimura, Takanao Shimodaira, Masahiro Sakai, Takashi Yoshino
  • Patent number: 11302783
    Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Jan Ropohl
  • Patent number: 11302690
    Abstract: The present invention provides a nitride semiconductor device capable of forming a half-bridge circuit and suppressing changes in current collapse characteristics. A first transistor of the present invention includes a first nitride semiconductor layer, and a first gate electrode, a first source electrode and a first drain electrode formed thereon. The second transistor includes a second nitride semiconductor layer, and a second gate electrode, a second source electrode and a second drain electrode formed thereon. The source electrode is electrically connected to a lower region of a first region on the substrate, the second source electrode is electrically connected to a lower region of a second region on the substrate, and a first insulating region is disposed between a portion corresponding to the first region on the substrate and a portion corresponding to the second region on the substrate.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: April 12, 2022
    Assignee: ROHM Co., Ltd.
    Inventor: Hirotaka Otake
  • Patent number: 11296206
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 5, 2022
    Inventors: Steven R. J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Patent number: 11296220
    Abstract: A semiconductor device of an embodiment includes: a nitride semiconductor layer including a first GaN region of n-type, a second GaN region of n-type on the first GaN region, a third GaN region of p-type on the first GaN region, a fourth GaN region of p-type sandwiching the second GaN region with the third GaN region, a fifth GaN region of p-type on the third GaN region, a sixth GaN region of p-type sandwiching the second GaN region with the fifth GaN region, a seventh GaN region of n-type on the fifth GaN region, an eighth GaN region of n-type on the sixth GaN region, a trench between the seventh GaN region and the eighth GaN region, the trench having an inclination angle of less than 90 degrees; a gate insulating layer including an aluminum nitride film in the trench; a gate electrode; a first electrode; and a second electrode.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 5, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi
  • Patent number: 11296195
    Abstract: A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 5, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Wen-Chia Liao
  • Patent number: 11296060
    Abstract: An LED pixel device is disclosed. The LED pixel device includes a first light-transmitting substrate, a second light-transmitting substrate overlying the first light-transmitting substrate, a third light-transmitting substrate overlying the second light-transmitting substrate, a first light-emitting cell underlying the first light-transmitting substrate, a second light-emitting cell interposed between the first light-transmitting substrate and the second light-transmitting substrate, and a third light-emitting cell interposed between the second light-transmitting substrate and the third light-transmitting substrate. The first light-emitting cell, the second light-emitting cell, and the third light-emitting cell emit light of different wavelengths.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: April 5, 2022
    Assignee: LUMENS CO., LTD.
    Inventors: Seunghyun Oh, Sungsik Jo, Junghyun Park, Byeonggeon Kim
  • Patent number: 11289627
    Abstract: A light emitting device includes a light emitting element having an upper emission face, a lower face and a lateral face(s); a reflecting member having an upper face, a lower face and inner and outer lateral faces, wherein the inner lateral face(s) is disposed on the lateral face side of the light emitting element; a wavelength conversion member having an upper emission face, a lower face and a lateral face(s), wherein the lower face is disposed on the upper emission face of the light emitting element and on the upper face of reflecting member; and a cover member having inner and outer lateral faces, wherein the inner lateral face(s) completely covers the lateral face(s) of the wavelength conversion member. The cover member contains a reflecting substance and a coloring substance, and the body color of the wavelength conversion member and body color of the cover member are the same or similar in color.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 29, 2022
    Assignee: Nichia Corporation
    Inventor: Toru Hashimoto
  • Patent number: 11289592
    Abstract: A structure to increase the breakdown voltage of the high electron mobility transistor is provided to solve the problem of function loss under a high voltage state. The structure includes a substrate, a conducting layer located on the substrate, a gate insulating layer and an electric-field-dispersion layer. The upper portion of the conducting layer is an electron supply layer, and the lower portion of the conducting layer is an electron tunnel layer. The gate insulating layer is laminated on the electron supply layer. The electric-field-dispersion layer is laminated on the gate insulating layer. The dielectric constant of the electric-field-dispersion layer is smaller than that of the gate insulating layer. A gate electrode is located between the electric-field-dispersion layer and the gate insulating layer. A source and a drain electrodes are respectively electrically connected to the electric-field-dispersion layer, the gate insulating layer, the electron supply layer, and the electron tunnel layer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: March 29, 2022
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Yu-Ching Tsao, Yu-Lin Tsai, Po-Hsun Chen, Yu-Shan Lin, Wen-Chung Chen
  • Patent number: 11257676
    Abstract: A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is ½ relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is ½ of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is ½ relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 22, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hideaki Matsuyama, Shinya Takashima, Katsunori Ueno, Ryo Tanaka, Masaharu Edo, Daisuke Mori, Hirotaka Suda, Hideaki Teranishi, Chizuru Inoue
  • Patent number: 11257941
    Abstract: A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: February 22, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 11257918
    Abstract: A semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; an ohmic electrode above the substrate; and a contact layer in contact with at least a part of the ohmic electrode, the contact layer containing silicon and chlorine. The second nitride semiconductor layer has a wider band gap than the first nitride semiconductor layer. A two-dimensional electron gas channel is formed in the first nitride semiconductor layer at a heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer. A silicon concentration has a higher peak value than a chlorine concentration in the contact layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 22, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kanda, Hideyuki Okita, Manabu Yanagihara, Takeshi Harada
  • Patent number: 11257940
    Abstract: A High Mobility Electron Transistor (HEMT) and a capacitor co-formed on an integrated circuit (IC) share at least one structural feature, thereby tightly integrating the two components. In one embodiment, the shared feature may be a 2DEG channel of the HEMT, which also functions in lieu of a base metal layer of a conventional capacitor. In another embodiment, a dialectic layer of the capacitor may be formed in a passivation step of forming the HEMT. In another embodiment, a metal contact of the HEMT (e.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor. In these embodiments, one or more processing steps required to form a conventional capacitor are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: February 22, 2022
    Assignee: Cree, Inc.
    Inventors: Evan Jones, Jeremy Fisher
  • Patent number: 11251295
    Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n? type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: February 15, 2022
    Assignee: Odyssey Semiconductor, Inc.
    Inventors: James R. Shealy, Richard J. Brown
  • Patent number: 11244607
    Abstract: The present disclosure provides a protection circuit for protecting a light emitting element, a pixel unit including the protection circuit, a display panel, and a driving method of the protection circuit. The protection circuit for protecting the light emitting element includes: a bonding protection sub-circuit including a sacrificial metal region, configured to electrically couple the sacrificial metal region to an anode pad and a cathode pad on the backplane for bonding the light emitting element during a period of bonding the light emitting element to the backplane.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: February 8, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Han Yue, Hsuanwei Mai
  • Patent number: 11245382
    Abstract: A method of manufacture and structure for an acoustic resonator device having a hybrid piezoelectric stack with a strained single crystal layer and a thermally-treated polycrystalline layer. The method can include forming a strained single crystal piezoelectric layer overlying the nucleation layer and having a strain condition and piezoelectric layer parameters, wherein the strain condition is modulated by nucleation growth parameters and piezoelectric layer parameters to improve one or more piezoelectric properties of the strained single crystal piezoelectric layer. Further, the method can include forming a polycrystalline piezoelectric layer overlying the strained single crystal piezoelectric layer, and performing a thermal treatment on the polycrystalline piezoelectric layer to form a recrystallized polycrystalline piezoelectric layer. The resulting device with this hybrid piezoelectric stack exhibits improved electromechanical coupling and wide bandwidth performance.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: February 8, 2022
    Assignee: AKOUSTIS, INC.
    Inventors: Shawn R. Gibb, Craig Moe, Jeff Leathersich, Steven Denbaars, Jeffrey B. Shealy
  • Patent number: 11233053
    Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta
  • Patent number: 11232950
    Abstract: The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: January 25, 2022
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.O.C.
    Inventors: Jheng Hao Fang, Yu Li Tsai, Hsueh-Hui Yang, Chih Hung Wu, Hwen Fen Hong
  • Patent number: RE49167
    Abstract: A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 9, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Van Mieczkowski, Jonathan Young, Qingchun Zhang, John Williams Palmour