Specified Wide Band Gap (1.5ev) Semiconductor Material Other Than Gaasp Or Gaalas Patents (Class 257/76)
  • Patent number: 10811397
    Abstract: Some embodiments of the disclosure provide for a lighting system including a substrate. The lighting system includes several blue light emitting diodes (LEDs) supported by the substrate. The lighting system includes at least one red LED supported by the substrate. The lighting system includes a light conversion material covering the blue LEDs and the at least one red LED.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: October 20, 2020
    Assignee: BRIDGELUX INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Peng Chen
  • Patent number: 10811268
    Abstract: According to one embodiment, a substrate processing apparatus comprises a chamber for a substrate that has a target film thereon. The apparatus includes a first gas introducing unit to introduce a precursor gas into the chamber, a second gas introducing unit that introduces a etching gas for etching the target film into the chamber, and a controller configured to control the first gas introducing unit and the second gas introducing unit to cause the first gas and the second gas to be alternately introduced to the chamber.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 20, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Kasahara, Shinichi Ito, Seiji Morita, Ryosuke Yamamoto, Ryuichi Saito
  • Patent number: 10804387
    Abstract: A vertical transistor is provided that includes a base structure and a superlattice structure overlying the base structure. The superlattice structure comprises a multichannel ridge having sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. The vertical transistor also includes a source region that overlies the base structure and is in contact with a first end of the superlattice structure, a floating drain that overlies the base structure and is in contact with a second end of the superlattice structure, and a drain. When the vertical transistor is in an ‘ON’ state, current flows from the source region through the channels of the multichannel ridge to the floating drain, which funnels the current to the drain through at least a portion of the base structure.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 13, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Josephine Bea Chang, Robert S. Howell, Matthew R. King
  • Patent number: 10804358
    Abstract: A compound semiconductor device includes: a compound semiconductor area in which a compound semiconductor plug is embedded and formed; and an ohmic electrode provided on the compound semiconductor plug, wherein the compound semiconductor plug includes, in a side surface portion that is as an interface with the compound semiconductor area, a high concentration dopant layer containing a dopant whose concentration is higher than that of other portions.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 13, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Yuichi Minoura
  • Patent number: 10793681
    Abstract: A hydrosilylation curable polysiloxane comprising at least one of units of formula (I) and units of formula (II), wherein Ar is C6-C20 aryl, R1 is C2-C20 alkenyl, and R2, R3, R4 and R5 independently are C1-C20 hydrocarbyl.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: October 6, 2020
    Assignee: Dow Silicones Corporation
    Inventors: Steven Swier, Haruhiko Furukawa, Michitaka Suto, Kazuhiro Nishijima, Atsushi Sugie
  • Patent number: 10797152
    Abstract: An electronic device can include a channel layer; an access region having an aluminum content substantially uniform or increasing with distance from the channel layer; and a gate dielectric layer overlying and contacting the channel layer. A process of forming an electronic device can include providing a substrate and a channel layer of a III-V semiconductor material over the substrate; forming a masking feature over the channel layer; and forming an access region over the channel layer. In an embodiment, the channel layer can include GaN, and the access region has an aluminum content that is substantially uniform or increases with distance from the channel layer. In another embodiment, the process can include removing at least a portion the masking feature and forming a gate dielectric layer over the channel layer. A dielectric film of the masking feature or the gate dielectric layer contacts the channel layer.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Abhishek Banerjee, Piet Vanmeerbeek, Peter Moens, Marnix Tack
  • Patent number: 10790143
    Abstract: A semiconductor structure, a high electron mobility transistor (HEMT), and a method for fabricating a semiconductor structure are provided. The semiconductor structure includes a substrate, a flowable dielectric material pad layer, a reflow protection layer, and a GaN-based semiconductor layer. The substrate has a pit exposed from a top surface of the substrate. The flowable dielectric material pad layer is formed in the pit, and a top surface of the flowable dielectric material pad layer is below the top surface of the substrate. The reflow protection layer is formed on the substrate and the top surface of the flowable dielectric material pad layer. The GaN-based semiconductor layer is disposed over the substrate.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 29, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yung-Fong Lin, Cheng-Tao Chou
  • Patent number: 10790344
    Abstract: A display device and a method of manufacturing the same are provided. A display device includes: a substrate, a semiconductor layer on the substrate, a gate insulating pattern on the semiconductor layer, a plurality of gate electrodes on the gate insulating pattern, and a thin-film transistor spaced apart from the gate insulating pattern, the thin-film transistor including: a source electrode contacting the top surface of the semiconductor layer, a source-drain electrode adjacent to the source electrode, a first of the plurality of gate electrodes being between the source-drain electrode and the source electrode, and a drain electrode adjacent to the source-drain electrode, a second of the plurality of gate electrodes being between the drain electrode and the source-drain electrode.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 29, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: Hongsuk Kim
  • Patent number: 10790374
    Abstract: Implementations of an ohmic contact for a gallium nitride (GaN) device may include: a first layer including aluminum coupled directly with the GaN device; the GaN having a heterostructure with an undoped GaN channel and a semi-insulating aluminum gallium nitride (AlGaN) barrier, all the foregoing operatively coupled with a substrate; a second layer including titanium coupled over the first layer; and a third layer including an anti-diffusion material coupled with the second layer. A passivation layer may be coupled between the AlGaN barrier and the first layer of the ohmic contact. The passivation layer may surround the ohmic contact.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 29, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Aurore Constant, Peter Coppens
  • Patent number: 10784179
    Abstract: A method for fabricating a semiconductor device includes sequentially laminating a separation layer and a first substrate layer on a sacrificial substrate, and forming a heat dissipation plate comprising a first region and a second region on the first substrate layer. The method further includes removing the sacrificial substrate and the separation layer, and patterning the first substrate layer to form a first substrate exposing the heat dissipation plate in the second region and contacting the heat dissipation plate in the first region, and forming a first element on the first substrate. The method still further includes forming a plurality of conductive pads disposed on the heat dissipation plate in the second region and a first line connecting at least one of the plurality of conductive pads to the first element, and forming a second element on the conductive pads in the second region.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: September 22, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyung Seok Lee, Zin-Sig Kim, Sung-Bum Bae
  • Patent number: 10784336
    Abstract: A gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes a heterogeneous structure, a doped GaN layer, an insulating layer, an undoped GaN layer, and a gate metal layer. The heterogeneous structure includes a channel layer and a barrier layer on the channel layer. The doped GaN layer is disposed on the barrier layer, the insulating layer is disposed on both sides of the top portion of the doped GaN layer, and the undoped GaN layer is disposed between the doped GaN layer and the insulating layer. The gate metal layer is disposed on the doped GaN layer and covers the insulating layer and the undoped GaN layer. The undoped GaN layer can protect the underlying doped GaN layer, and the insulating layer has the effect of preventing gate leakage.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 22, 2020
    Assignee: Excelliance MOS Corporation
    Inventors: Chu-Kuang Liu, Hung-Kun Yang
  • Patent number: 10784140
    Abstract: An electronic device can include a semiconductor material and a semiconductor layer overlying the semiconductor material, wherein the semiconductor layer has a greater bandgap energy as compared to the semiconductor material. The electronic device can include a component having a high electrical field region and a low electrical field region. Within the high electrical field region, the semiconductor material is not present. In another embodiment, the component may not be present. In another aspect, a process can include providing a substrate and a semiconductor layer overlying the substrate; removing a first portion of the substrate to define a first trench; forming a first insulating layer within the first trench; removing a second portion of the substrate adjacent to first insulating layer to define second trench; and forming a second insulating layer within the second trench.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 22, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ali Salih, Gordon M. Grivna
  • Patent number: 10784145
    Abstract: A wafer composite is provided which includes an auxiliary substrate, a donor substrate and a sacrificial layer formed between the auxiliary substrate and the donor substrate. Functional elements of the semiconductor component are formed in a component layer, including at least one partial layer of the donor substrate. The auxiliary substrate is then separated from the component layer by heat input into the sacrificial layer.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Berger, Wolfgang Lehnert, Gerhard Metzger-Brueckl, Guenther Ruhl, Roland Rupp
  • Patent number: 10770381
    Abstract: In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: September 8, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Ali Salih, Prasad Venkatraman
  • Patent number: 10763348
    Abstract: The invention provides a product and a manufacturing process for a high power semiconductor device. The semiconductor device comprises a GaN/AlGaN epilayer structure on an SOI substrate with a thick, uninterrupted GaN layer for use in high-power applications.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: September 1, 2020
    Assignee: Agency for Science, Technology and Research
    Inventors: Krishna Kumar Manippady, Surani Bin Dolmanan, Kaixin Vivian Lin, Hui Ru Tan, Sudhiranjan Tripathy
  • Patent number: 10763110
    Abstract: A method of forming doped regions by diffusion in gallium nitride materials includes providing a substrate structure including a gallium nitride layer and forming a mask on the gallium nitride layer. The mask exposes one or more portions of a top surface of the gallium nitride layer. The method also includes depositing a magnesium-containing gallium nitride layer on the one or more portions of the top surface of the gallium nitride layer and concurrently with depositing the magnesium-containing gallium nitride layer, forming one or more magnesium-doped regions in the gallium nitride layer by diffusing magnesium into the gallium nitride layer through the one or more portions. The magnesium-containing gallium nitride layer provides a source of magnesium dopants. The method further includes removing the magnesium-containing gallium nitride layer and removing the mask.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: September 1, 2020
    Assignee: QROMIS, INC.
    Inventors: Ozgur Aktas, Vladimir Odnoblyudov, Cem Basceri
  • Patent number: 10756086
    Abstract: A method of manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. The second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fu-Chun Huang, Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Alexander Kalnitsky
  • Patent number: 10756096
    Abstract: Disclosed are structures with a complementary field effect transistor (CFET) and a buried metal interconnect that electrically connects a source/drain region of a lower-level transistor of the CFET with another device. The structure can include a memory cell with first and second CFETs, where each CFET includes a pull-up transistor stacked on and having a common gate with a pull-down transistor and each pull-down transistor has a common source/drain region with a pass-gate transistor. The metal interconnect connects a lower-level source/drain region of the first CFET (i.e., the common source/drain region of first pass-gate and pull-up transistors) to the common gate of the second CFET (i.e., to the common gate of second pull-down and pull-up transistors). Formation methods include forming an interconnect placeholder during lower-level source/drain region formation.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bipul C. Paul, Ruilong Xie
  • Patent number: 10749313
    Abstract: A method for manufacturing a semiconductor element includes: providing a nitride semiconductor layer; performing plasma treatment to at least part of a surface of the nitride semiconductor layer in an oxygen-containing atmosphere while applying bias power; after the performing of the plasma treatment, heat treating the nitride semiconductor layer in an oxygen-containing atmosphere; forming a protective film on a region of the surface of the nitride semiconductor layer where the plasma treatment was performed; and forming an electrode in a region of the surface of the nitride semiconductor layer where the protective film was not formed.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 18, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Eiji Muramoto, Akinori Kishi
  • Patent number: 10749075
    Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer; a plurality of first trenches penetrating the second semiconductor layer and the active layer to expose the first semiconductor layer; a second trench penetrating the second semiconductor layer and the active layer to expose the first semiconductor layer, wherein the second trench is disposed near an outmost edge of the active layer, and surrounds the active layer and the plurality of first trenches; a patterned metal layer formed on the second semiconductor layer and formed in one of the plurality of first trenches or the second trench; and a first pad portion and a second pad portion both formed on the second semiconductor layer and electrically connecting the second semiconductor layer and the first semiconductor layer respectively.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 18, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Tsung-Hsun Chiang, Bo-Jiun Hu, Wen-Hung Chuang, Yu-Ling Lin
  • Patent number: 10741666
    Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 11, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Wei Chou, Hsin-Chih Lin
  • Patent number: 10734485
    Abstract: The main purpose of the present invention is to provide: a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a technique required for the production of the substrate. This invention provides: a method for manufacturing an M-plane GaN substrate comprising; forming a mask pattern having a line-shaped opening parallel to an a-axis of a C-plane GaN substrate on an N-polar plane of the C-plane GaN substrate, growing a plane-shape GaN crystal of which thickness direction is an m-axis direction from the opening of the mask pattern by an ammonotharmal method, and cutting out the M-plane GaN substrate from the plane-shape GaN crystal.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 4, 2020
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yusuke Tsukada, Shuichi Kubo, Kazunori Kamada, Hideo Fujisawa, Tatsuhiro Ohata, Hirotaka Ikeda, Hajime Matsumoto, Yutaka Mikawa
  • Patent number: 10734303
    Abstract: An electronic device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The electronic device also includes a buffer layer coupled to the support structure, a contact layer coupled to the buffer layer, and a field-effect transistor (FET) coupled to the contact layer.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
  • Patent number: 10734549
    Abstract: A method of improving high-current density efficiency of an LED, said method comprising: (a) preparing a series of LEDs having decreasing defect densities, wherein each LED of said series has a peak IQE of at least 50%, and wherein each LED of said series has the same epitaxial structure; (b) determining an increase in IQEs at high-current density between at least two LEDs of said series; (c) preparing at least an additional LED of said series by reducing defect density relative to the previously obtained lowest defect density; and (d) reiterating steps (b) and (c) until said increase is at least 3% between two LEDs of said series having a decrease X in defect densities.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: August 4, 2020
    Assignee: ECOSENSE LIGHTING, INC.
    Inventors: Aurelien J. F. David, Christophe Hurni, Nathan Young
  • Patent number: 10733348
    Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: August 4, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
  • Patent number: 10727305
    Abstract: A semiconductor device includes a nitride semiconductor stacked structure that includes a channel layer containing GaN and a barrier layer containing In and further includes a cap layer that contains GaN on the outermost surface but does not contain Al. The cap layer has a Ga/N ratio that varies along a thicknesswise direction.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 28, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 10727167
    Abstract: This power semiconductor device is provided with: a substrate; and a semiconductor element which is bonded onto the substrate using a sinterable metal bonding material. The semiconductor element comprises: a base; a first conductive layer that is provided on a first surface of the base, said first surface being on the substrate side; and a second conductive layer that is provided on a second surface of the base, said second surface being on the reverse side of the first surface. The thickness of the first conductive layer is from 0.5 times to 2.0 times (inclusive) the thickness of the second conductive layer.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takayuki Yamada, Noriyuki Besshi, Yuya Muramatsu, Masaru Fuku, Dai Nakajima
  • Patent number: 10714607
    Abstract: According to an embodiment of the present invention, a high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a carrier transit layer on the buffer layer; a carrier supply layer on the carrier transit layer; a gate electrode on the carrier supply layer; and a source and a drain adjacent to two sides of the gate electrode. Preferably, the carrier supply layer comprises a concentration gradient of aluminum (Al).
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Kuan-Hung Liu
  • Patent number: 10714608
    Abstract: According to one embodiment, a semiconductor device includes first and second regions, a first insulating portion, and first, second, and third electrodes. The first region includes first and second partial regions, and a third partial region between the first and second partial regions. The second region includes fourth and fifth partial regions. The fourth partial region overlaps the first partial region. The fifth partial region overlaps the second partial region. The first insulating portion includes first, second, and third insulating regions. The first insulating region is provided between the second insulating region and the third partial region and between the third insulating region and the third partial region. The first electrode is electrically connected to the fourth partial region. The second electrode is away from the first electrode and is electrically connected to the fifth partial region. The third electrode is provided between the first and second electrodes.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: July 14, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Patent number: 10707373
    Abstract: There is provided a self-supporting polycrystalline gallium nitride substrate having excellent characteristics such as high luminous efficiency and high conversion efficiency when used for devices, such as light emitting devices and solar cells. The self-supporting polycrystalline gallium nitride substrate is composed of gallium nitride-based single crystal grains having a specific crystal orientation in a direction approximately normal to the substrate, and has a top surface and a bottom surface. The crystal orientations of individual gallium nitride-based single crystal grains as determined from inverse pole figure mapping by electron backscatter diffraction (EBSD) analysis on the top surface are distributed at various tilt angles from the specific crystal orientation, in which the average tilt angle thereof is 0.1° or more and less than 1° and the cross-sectional average diameter DT of the gallium nitride-based single crystal grains at the outermost surface exposed on the top surface is 10 ?m or more.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: July 7, 2020
    Assignee: NGK Insulators, Ltd.
    Inventors: Morimichi Watanabe, Kei Sato, Yoshitaka Kuraoka, Katsuhiro Imai, Tsutomu Nanataki
  • Patent number: 10707339
    Abstract: According to one embodiment, a semiconductor device includes first to third regions, and first to third electrodes. The first region includes a first partial region, a second partial region, and a third partial region between the first and second partial regions. A direction from the first partial region toward the first electrode is aligned with a first direction. A direction from the second partial region toward the second electrode is aligned with the first direction. A second direction from the first electrode toward the second electrode crosses the first direction. A direction from the third partial region toward the third electrode is aligned with the first direction. At least a portion of the third region is provided between the first and second electrodes in the second direction. At least a portion of the second region is provided between the third and first regions.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: July 7, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Hisashi Yoshida
  • Patent number: 10707310
    Abstract: According to one embodiment, a semiconductor device includes first to third regions, and first to third electrodes. The first region includes a first partial region, a second partial region, and a third partial region between the first and second partial regions. A direction from the first partial region toward the first electrode is aligned with a first direction. A second direction from the first electrode toward the second electrode crosses the first direction. A direction from the third partial region toward the third electrode is aligned with the first direction. A position of the third electrode is between a position of the first electrode and a position of the second electrode in the second direction. At least a portion of the second region is provided between the first and second electrodes. At least a portion of the third region is provided between the first and second regions.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: July 7, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeya Kimura, Hisashi Yoshida
  • Patent number: 10707436
    Abstract: The present disclosure relates to an illumination device which is realized by an organic light emitting element having a plurality of stacks and which achieves an improvement in relation to the efficiency difference among wavelengths by changing a light emitting layer structure of a predetermined stack.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 7, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Jin-A You, Chang-Oh Kim, Jae-Min Moon, Ju-Hyuk Kwon
  • Patent number: 10700189
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a dopant holding layer, a source/drain pair, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer and the dopant holding layer are disposed over the barrier layer. The source/drain pair are disposed over the substrate and on both sides of the compound semiconductor layer. The gate is disposed over the compound semiconductor layer.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: June 30, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Chih-Yen Chen
  • Patent number: 10692839
    Abstract: GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon substrate. A back-side of a silicon substrate may be processed to adapt substrates of standardized diameters and thicknesses to GOS applications. Bowing and/or warping during high temperature epitaxial growth processes may be mitigated by pre-processing silicon substrate so as to pre-stress the substrate in a manner than counterbalances stress induced by the III-N material and/or improve a substrate's ability to absorb stress. III-N devices fabricated on an engineered GOS substrate may be integrated together with silicon MOS devices fabricated on a separate substrate. Structures employed to improve substrate resilience and/or counterbalance the substrate stress induced by the III-N material may be further employed for interconnecting the III-N and silicon MOS devices of a 3D IC.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Peter G. Tolchinsky, Robert S. Chau
  • Patent number: 10686054
    Abstract: A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Patent number: 10685932
    Abstract: A semiconductor substrate (1) has a front surface and a back surface that are opposite each other. A first metal layer (2) is formed on the front surface of the semiconductor substrate (1). A second metal layer (3) for soldering is formed on the first metal layer (2). A third metal layer (5) is formed on the back surface of the semiconductor substrate (1). A fourth metal layer (6) for soldering is formed on the third metal layer (5). The second metal layer (3) has a larger thickness than that of the fourth metal layer (6). The first, third, and fourth metal layers (2,5,6) are not divided in a pattern. The second metal layer (3) is divided in a pattern and has a plurality of metal layers electrically connected to each other via the first metal layer (2).
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 16, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Sho Suzuki, Tsuyoshi Osaga
  • Patent number: 10685841
    Abstract: A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure an
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: June 16, 2020
    Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tohru Nakamura, Tomoyoshi Mishima, Hiroshi Ohta, Yasuhiro Yamamoto, Fumimasa Horikiri
  • Patent number: 10680093
    Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 9, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jungwoo Joh, Naveen Tipirneni, Chang Soo Suh, Sameer Pendharkar
  • Patent number: 10672917
    Abstract: The present disclosure provides a schottky barrier rectifier, comprising: a communication layer; a drift layer provided on a side of the communication layer and forming a heterojunction structure together with the communication layer; anode metal provided on a side of the drift layer away from the communication layer; and cathode metal provided on a side of the communication layer away from the drift layer. The drift layer is provided with a first area, which extends in a direction of thickness thereof, between a surface of the drift layer away from the communication layer and a surface thereof close to the communication layer, the first are a containing a first metal element and the content of the first metal element in the first area changing in the direction of thickness. The rectifier of the present disclosure uses polarized charges formed by a heterojunction, and thus the breakdown voltage of devices may be improved.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 2, 2020
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Yi Pei, Qiang Liu
  • Patent number: 10665666
    Abstract: A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10665710
    Abstract: A disclosed compound semiconductor device includes a channel layer configured to generate carriers; a spacer layer of Aly1Ga1-y1N (0.20<y1?0.70) formed on the channel layer; and a barrier layer of Inx2Aly2 Ga1-x2-y2N (0?x2?0.15 and 0.20?y2<0.70) formed on the spacer layer, where y1 and y2 satisfy a relationship of y1>y2.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: May 26, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Atsushi Yamada, Junji Kotani
  • Patent number: 10665463
    Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 26, 2020
    Assignee: Power Integrations, Inc.
    Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
  • Patent number: 10651307
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fifth layers, and an insulating portion. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The second layer includes first and second semiconductor regions. The third layer is provided between the third partial region and the third electrode. The fourth layer is provided between the third partial region and the third layer. The fifth layer includes first and second intermediate regions. The third layer is provided between the first and second intermediate regions. The insulating portion includes a first insulating region provided between the third layer and the third electrode.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 12, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Masahiko Kuraguchi, Shinya Nunoue
  • Patent number: 10651304
    Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: May 12, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Ferdinando Iucolano
  • Patent number: 10636836
    Abstract: A semiconductor light-emitting device comprises: an insulating base, a current diffusion layer, light-emitting structure layers and an insulating layer. The current diffusion layer includes: a first electrode connecting part, a second electrode connecting part, N contact parts and N+1 flat parts. N+1 light-emitting structure layers are correspondingly disposed on the N+1 flat parts, and each of the N+1 light-emitting structure layers includes: a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked on a corresponding flat part. N grooves are formed on a side of the second semiconductor layer away from the active layer, depth of the N grooves is less than the thickness of the second semiconductor layer, and the N contact parts correspond to the N grooves.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: April 28, 2020
    Assignee: Enkris Semiconductor, Inc.
    Inventors: Liyang Zhang, Kai Cheng
  • Patent number: 10629720
    Abstract: A III-nitride vertical field effect transistor comprises a base plate; a mask layer overlaying said base plate and having opening windows for partial exposure of said base plate; a drain grown epitaxially onto regions of said base plate exposed by the opening windows of said mask layer; an insulation layer grown epitaxially onto said drain; a source grown epitaxially onto said insulation layer; a vertical nitride stack grown epitaxially onto the side faces of said drain, said insulation layer and said source, overlaying said mask layer and providing at least one vertical conducting channel to connect said source to said drain; a current flowing from said source to said drain through a conducting channel can be modulated by an electrical voltage that is applied to the side face of said vertical nitride stack. There are preferably also electrodes and edge terms.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: April 21, 2020
    Inventor: Quanzhong Jiang
  • Patent number: 10622456
    Abstract: The present application provides a semiconductor device and a method for manufacturing the same. The method includes: sequentially forming a buffer layer and a barrier layer on a substrate, wherein a two-dimensional electron gas is formed between the buffer layer and the barrier layer; etching a source region and a drain region of the barrier layer to form a trench on the buffer layer, and doped layers are formed on the trench; forming a passivation layer on the barrier layer and the doped layers, and etching the passivation layer to expose a portion of the barrier layer, wherein the portion of the barrier layer is in contact with the doped layers; and doping ions into a portion of the buffer layer in contact with the portion of the buffer layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: April 14, 2020
    Assignee: SUZHOU HANHUA SEMICONDUCTOR CO., LTD.
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Patent number: 10615280
    Abstract: There is disclosed in an example, a gallium nitride (GaN) field effect transistor (FET) having a gate, a drain, and a source, having: a doped GaN buffer layer; a first epitaxy layer above the buffer layer, the first epitaxy layer having a first doping profile (for example, doped, or p-type doping); and a second epitaxy layer above the first epitaxy layer, the second epitaxy layer having a second doping profile (for example, undoped, or n-type doping).
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Mark Armstrong, Han Wui Then
  • Patent number: 10601300
    Abstract: An integrated DC-DC converter device includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Efficient Power Conversion Corporation
    Inventors: David C. Reusch, Jianjun Cao, Alexander Lidow