Specified Wide Band Gap (1.5ev) Semiconductor Material Other Than Gaasp Or Gaalas Patents (Class 257/76)
  • Patent number: 11222849
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Kuei-Ming Chen
  • Patent number: 11222968
    Abstract: The present disclosure provides a semiconductor device comprising a substrate; a first III-V compound layer over the substrate; a second III-V compound layer on the first III-V compound layer; a third III-V compound layer on the second III-V compound layer; a source region on the third III-V compound layer; a drain region on the third III-V compound layer; a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; and a gate region on the first dielectric layer, wherein a bottom of the gate region is higher than a top surface of the first dielectric layer; the second lateral distance is larger than the first lateral distance.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Po-Chih Chen, Jiun-Lei Yu, Yao-Chung Chang, Chun-Lin Tsai
  • Patent number: 11201210
    Abstract: A semiconductor device of an embodiment includes a SiC layer including a first trench, a second trench having first and second regions, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region, a p-type fourth SiC region between the first trench and the first SiC region, and a p-type fifth SiC region between the second trench and the first SiC region and having a first portion and a second portion, a gate electrode in the first trench, a first electrode in the second trench, and a second electrode. A distance between the first trench and the first region is greater than a distance between the first trench and the second region, the first portion is separated from the fourth SiC region, the second portion contacts the fourth SiC region, the first region contacts the first portion, and the second region contacts the second portion.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: December 14, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinya Kyogoku, Katsuhisa Tanaka, Ryosuke Iijima
  • Patent number: 11195943
    Abstract: The present invention relates to an epitaxial structure of Ga-face group III nitride, its active device, and its gate protection device. The epitaxial structure of Ga-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-AlyGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-AlyGaN buffer layer, and an i-AlxGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 7, 2021
    Inventor: Chih-Shu Huang
  • Patent number: 11189718
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first conductive part, first and second insulating layers. The third electrode includes first and second portions. The first portion is between the first electrode and the second electrode. The first semiconductor layer includes first, second, third, fourth and fifth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor layer includes first and second semiconductor regions. The first conductive part is electrically connected to the first electrode. The first insulating layer includes a first insulating portion. The second insulating layer includes first and second insulating regions.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: November 30, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Patent number: 11189768
    Abstract: A light emitting device, according to the present embodiment, has a light emitting panel, a flexible wiring substrate, a mold resin and a protective tape. The light emitting panel has a first substrate, which is transparent to light, a plurality of conductor patterns, which are formed on a surface of the first substrate, a plurality of light emitting elements, which are connected to any of the conductor patterns, and a resin layer, which holds the light emitting elements on the first substrate. The flexible wiring substrate has a circuit pattern that is electrically connected with an exposed part of the conductor patterns. The mold resin covers the exposed part of the conductor patterns and an exposed part of the circuit pattern. The protective tape covers the mold resin, and is wound around a joint part of the light emitting panel and the flexible wiring substrate.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 30, 2021
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventors: Naoki Takojima, Kairi Makita, Fumio Ueno
  • Patent number: 11189719
    Abstract: Apparatus and circuits including transistors with different gate stack materials and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a channel layer formed over the substrate; a first transistor formed over the channel layer, wherein the first transistor comprises a first source region, a first drain region, a first gate structure, and a first polarization modulation portion under the first gate structure; and a second transistor formed over the channel layer, wherein the second transistor comprises a second source region, a second drain region, a second gate structure, and a second polarization modulation portion under the second gate structure, wherein the first polarization modulation portion is made of a material different from that of the second polarization modulation portion.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 11177420
    Abstract: An optical coupling structure is disposed on a light output surface of a semiconductor LED to facilitate coupling of light emitted by the semiconductor LED through the light output surface. The optical coupling structures comprise light scattering particles and/or air voids embedded in or coated with a thin layer of a material that has an index of refraction close to or matching the index of refraction of the material forming the light output surface of the semiconductor LED.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 16, 2021
    Assignee: Lumileds LLC
    Inventors: Antonio Lopez-Julia, Jens Meyer
  • Patent number: 11177376
    Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Sanaz K. Gardner, Marko Radosavljevic, Seung Hoon Sung, Benjamin Chu-Kung, Robert S. Chau
  • Patent number: 11177378
    Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jungwoo Joh, Naveen Tipirneni, Chang Soo Suh, Sameer Pendharkar
  • Patent number: 11171227
    Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: November 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • Patent number: 11164851
    Abstract: Over a flexible substrate are deposited stacked pixel layers including a bottom layer of LEDs forming blue pixels, a middle layer of LEDs forming green pixels, and a top layer of LEDs forming red pixels. Each LED die comprises an LED portion and an integrated transistor portion. Applying a voltage to a control terminal of the transistor portion energizes the LED portion. The pixels are substantially transparent, due to the LEDs being microscopic and the pixel areas being much larger, to allow light from the underlying layers to pass through. The three layers of pixels are aligned so that a combination of a single top red pixel, a single underlying green pixel, and a single underlying blue pixel form a single multi-color pixel. The different layers have transparent column and row lines.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: November 2, 2021
    Assignee: Nthdegree Technologies Worldwide, Inc.
    Inventors: William Johnstone Ray, Michael LeFebvre, Darin Wagner, Richard A. Blanchard
  • Patent number: 11158702
    Abstract: A gallium nitride high electron mobility transistor and a formation method therefor are provided. The transistor includes: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; and a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas. The high electron mobility transistor has a higher breakdown voltage.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 26, 2021
    Assignee: Shanghai Simgui Technology Co., Ltd.
    Inventors: Chen Li, Fawang Yan, Feng Zhang, Beiji Zhao, Chunxue Liu
  • Patent number: 11158666
    Abstract: A multi-wavelength light-emitting diode epitaxial structure comprises of a substrate and at least three light-emitting elements, wherein the light-emitting elements are sequentially stacked on the substrate. For each two adjacent light-emitting elements, the light-emitting element disposed closer to the light-exiting surface has a higher bandgap than that of the light-emitting element disposed farther from the light-exiting surface. Each of the light-emitting elements comprises of an active layer and two cladding layers disposed on two opposite sides of the active layer, and each active layer includes a multiple quantum well structure. Cladding layers of different refractive indexes are arranged incrementally from the substrate to the light-exiting surface. Any given two adjacent cladding layers from two light-emitting elements have a combined thickness of 1 ?m or less. The emission wavelengths of the light-emitting elements are ultraviolet or infrared bands.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: October 26, 2021
    Assignee: EPILEDS TECHNOLOGIES, INC.
    Inventors: Jiun-Wei Tu, Wei-Yu Tseng, Tetsuya Gouda
  • Patent number: 11152364
    Abstract: A semiconductor structure includes a substrate having a first region and a second region, an epitaxial layer above the substrate, a first device on the first region, a second device on the second region and an isolation structure on the substrate. The first device includes a first gate electrode, a first source electrode and a first drain electrode disposed at two opposite sides of the first gate electrode. A dielectric layer disposed on the epitaxial layer covers the first gate electrode. The second device includes a second gate electrode disposed on the dielectric layer, second source and drain electrodes disposed at two opposite sides of the second gate electrode. The second source electrode is electrically connected to the first drain electrode. Also, the portions of the epitaxial layer respectively disposed in the first and second regions are isolated from each other by the isolation structure.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 19, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Shin-Cheng Lin
  • Patent number: 11152531
    Abstract: A method of manufacturing a semiconductor device includes: providing a first member comprising: a first substrate, a semiconductor layer disposed on the first substrate and defining a first recess, and a first metal layer disposed above at least a portion other than the first recess, the first member defining a second recess in a region of a surface of the first member including a region directly above the first recess; providing a second member comprising: a second substrate, a second metal layer on or above the second substrate, a third metal layer on the second metal layer, and a fourth metal layer on the third metal layer; and bonding the first member and the second member together by heating the first metal layer and the fourth metal layer while facing each other. The third metal layer impedes interdiffusion between the second metal layer and the fourth metal layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 19, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Eiji Muramoto
  • Patent number: 11152474
    Abstract: A semiconductor device is provided, including a substrate, a gate electrode, a first dielectric layer, a source field plate, a second dielectric layer, a source electrode and a drain electrode. The gate electrode is disposed on the substrate. The first dielectric layer is disposed on the gate electrode and has a first recess and a second recess. The source field plate is disposed on the first dielectric layer and extends into the first recess and the second recess. The second dielectric layer is disposed on the source field plate. The source electrode is disposed on the second dielectric layer and electrically connected to the source field plate. The drain electrode is disposed on the second dielectric layer. The first recess and the second recess are located between the gate electrode and the drain electrode.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 19, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Chih-Yen Chen
  • Patent number: 11145644
    Abstract: A power device includes a substrate including a drift layer and having a first region and a second region, the drift layer having impurities of a first type; a switch formed in the first region; a diode formed in the second region; a metal structure formed over a surface of the substrate, the metal structure having a first thickness over the first region of the substrate and a second thickness over the second region of the substrate, the first thickness and second thickness having at least 3 um in thickness difference; and a zone provided in the drift layer in the second region of the substrate, the zone having impurities of a second type that is different from the first type.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 12, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takumi Hosoya, Hiromichi Inenaga, Seiji Miyoshi
  • Patent number: 11145579
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: October 12, 2021
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Patent number: 11145742
    Abstract: A process of forming a nitride semiconductor device is disclosed. The process includes steps of: (a) forming insulating films on a semiconductor stack, where the insulating films include a first silicon nitride (SiN) film, a silicon oxide (SiO2) film, and a second SiN film; (b) forming an opening in the insulating films; (c) widening the opening in the SiO2 film; (d) forming a recess in the semiconductor stack using the insulating films as a mask; (e) growing a doped region within the recess and simultaneously depositing the nitride semiconductor material constituting the doped region on the second SiN film; and (f) removing the nitride semiconductor material deposited on the second SiN film and the second SiN film by removing the SiO2 film.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 12, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Tomohiro Yoshida
  • Patent number: 11145791
    Abstract: A light-emitting device is provided, which includes a first semiconductor structure, an active structure, a second semiconductor structure, and a first blocking layer. The first semiconductor structure has a first conductivity type. The active structure is on the first semiconductor structure and has a first dopant. The second semiconductor structure is on the active structure and has a second conductivity type different from the first conductivity type. The first blocking layer is between the second semiconductor structure and the active structure. The first blocking layer has the first dopant with a first doping concentration decreasing along a depth direction from the second semiconductor structure to the first semiconductor structure.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 12, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-Chang Lee, Meng-Yang Chen
  • Patent number: 11139414
    Abstract: The invention relates to an AlInGaN alloy based superluminescent diode, comprising a gallium nitride bulk substrate, a lower cladding layer with n-type electrical conductivity. Further it includes a lower light-guiding layer with n-type electrical conductivity, a light emitting layer, an electron blocking layer with p-type electrical conductivity, an upper light-guiding layer, an upper cladding layer with p-type electrical conductivity, and a subcontact layer with p-type electrical conductivity. The gallium nitride bulk substrate has a spatially varying surface misorientation in the relation to the crystallographic plane M in range of 0° to 10°.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 5, 2021
    Assignees: TOPGAN SP. Z O.O.
    Inventors: Kafar Anna, Szymon Stanczyk, Anna Nowakowska-Siwinska, Marcin Sarzynski, Tadeusz Suski, Piotr Perlin
  • Patent number: 11127878
    Abstract: A method of depositing a coating layer comprising gallium nitride on a substrate comprising the steps of: (a) providing the substrate having a plurality of side walls and valleys; (b) forming a first layer of gallium nitride deposited on the substrate, by reacting gaseous trimethylgallium and ammonia at a temperature ranging from 400 to 500° C., such that the first layer is formed on the side walls and the valleys; and (c) forming a second layer of gallium nitride deposited on top of the first layer, by reacting gaseous trimethylgallium and ammonia at a temperature ranging from 1000 to 1200° C., to obtain the coating layer comprising the first layer of gallium nitride and the second layer of gallium nitride at a thickness ranging from 3.0 to 4.5 ?m.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: September 21, 2021
    Assignee: Universiti Malaya
    Inventors: Ahmad Shuhaimi Bin Abu Bakar, Mohd Adreen Shah Bin Azman Shah
  • Patent number: 11127743
    Abstract: A transistor including a carrier transit layer that includes a compound semiconductor and a carrier supply layer in contact with the carrier transit layer. The carrier supply layer includes a compound semiconductor of a different type from the carrier transit layer. The transistor includes a gate electrode provided on the carrier supply layer, and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: September 21, 2021
    Assignee: SONY CORPORATION
    Inventors: Shigeru Kanematsu, Katsuhiko Takeuchi, Masashi Yanagita, Shinichi Wada
  • Patent number: 11121249
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane and includes a trench located on a first plane side and has a first region and a second region, a first silicon carbide region of an n-type, a second silicon carbide region of a p-type between the first silicon carbide region and the first plane, a third silicon carbide region of the n-type between the second silicon carbide region and the first plane, and a fourth silicon carbide region of the p-type between the second region and the first silicon carbide region; a gate electrode in the first region; a first electrode on the first plane side of the silicon carbide layer, a part of the first electrode is located in the second region and is in contact with the third and the fourth silicon carbide region; and a second electrode.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 14, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinya Kyogoku, Katsuhisa Tanaka, Ryosuke Iijima
  • Patent number: 11107950
    Abstract: A light emitting chip includes a first-type semiconductor layer, a light emitting layer, and a second-type semiconductor layer which are disposed in such order, a passivation layer, and a current spreading layer. The second-type semiconductor layer and the light emitting layer cooperate to form a mesa structure which partially exposes the first-type semiconductor layer. The mesa structure has a lateral surface over which the passivation layer is disposed. The current spreading layer is disposed in contact with the second-type semiconductor layer. A distance between peripheries of a contact surface of the current spreading layer and a top surface of the second-type semiconductor layer is not greater than 5 ?m. A method for producing the chip is also disclosed.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: August 31, 2021
    Assignee: Xiamen San'an Optoelectronics Co., Ltd.
    Inventors: Yu-Tsai Teng, Yan Feng, Shuo Yang, Chung-Ying Chang, Shutian Qiu
  • Patent number: 11101378
    Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 24, 2021
    Assignee: Raytheon Company
    Inventors: Kiuchul Hwang, Brian D. Schultz, John Logan, Christos Thomidis
  • Patent number: 11090903
    Abstract: Devices, systems and techniques are described for producing and implementing articles and materials having nanoscale and microscale structures that exhibit superhydrophobic, superoleophobic or omniphobic surface properties and other enhanced properties. In one aspect, a surface nanostructure can be formed by adding a silicon-containing buffer layer such as silicon, silicon oxide or silicon nitride layer, followed by metal film deposition and heating to convert the metal film into balled-up, discrete islands to form an etch mask. The buffer layer can be etched using the etch mask to create an array of pillar structures underneath the etch mask, in which the pillar structures have a shape that includes cylinders, negatively tapered rods, or cones and are vertically aligned. In another aspect, a method of fabricating microscale or nanoscale polymer or metal structures on a substrate is made by photolithography and/or nano imprinting lithography.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 17, 2021
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Sungho Jin, Chulmin Choi
  • Patent number: 11088299
    Abstract: A crystal of a group 13 nitride has an upper surface and lower surface and is composed of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof. When the upper surface of the layer of the crystal of the group 13 nitride is observed by cathode luminescence, the upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part. A half value width of reflection at the (0002) plane of a X-ray rocking curve on the upper surface is 3000 seconds or less and 20 seconds or more.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 10, 2021
    Assignee: NGK INSULATORS, LTD.
    Inventors: Takayuki Hirao, Hirokazu Nakanishi, Mikiya Ichimura, Takanao Shimodaira, Masahiro Sakai, Takashi Yoshino
  • Patent number: 11075262
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a semiconductor member, and a first crystal member. A direction from the first electrode toward the second electrode is aligned with a first direction. A position in the first direction of the third electrode is between positions in the first direction of the first electrode and the second electrode. The semiconductor member includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The semiconductor member includes a first region, and first and second partial regions. The first region is between the first and second electrodes in the first direction. A second direction from the first region toward the third electrode crosses the first direction. The first crystal member is provided between the first and third electrodes in the second direction.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 27, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeya Kimura, Hisashi Yoshida, Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 11069843
    Abstract: A light-emitting device includes: a light-emitting element; a first light-diffusion layer disposed laterally to the light-emitting element and constituting a first portion of lateral surfaces of the light-emitting device; a second light-diffusion layer disposed above the light-emitting element and the first light-diffusion layer and constituting a second portion of the lateral surfaces of the light-emitting device; a light-control portion disposed between the first light-diffusion layer and the second light-diffusion layer and configured to reflect a portion of light emitted from the light-emitting element; and a first light-reflection layer disposed on the second light-diffusion layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: July 20, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Toru Hashimoto
  • Patent number: 11050355
    Abstract: According to one configuration, an inductor device comprises: core material and one or more electrically conductive paths. The core material is magnetically permeable and surrounds (envelops) the one or more electrically conductive paths. Each of the electrically conductive paths extends through the core material of the inductor device from a first end of the inductor device to a second end of the inductor device. The magnetically permeable core material is operative to confine (guide, carry, convey, localize, etc.) respective magnetic flux generated from current flowing through a respective electrically conductive path. The core material stores the magnetic flux energy (i.e., first magnetic flux) generated from the current flowing through the first electrically conductive path.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: June 29, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Kennith K. Leong, Matthias J. Kasper, Luca Peluso, Gerald Deboy
  • Patent number: 11049863
    Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 29, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Ting Ho, Ying-Chiao Wang, Yu-Ching Chen, Hui-Ling Chuang, Kuei-Hsuan Yu
  • Patent number: 11043563
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 22, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih Lin, Chang-Xiang Hung, Chia-Ching Huang, Yung-Hao Lin, Chia-Hao Lee
  • Patent number: 11043613
    Abstract: A light emitting diode (LED) device includes a light emitting epitaxial layer having opposite first and second surfaces and a plurality of microlenses formed on the first surface. The light emitting epitaxial layer includes a first type semiconductor layer defining the first surface, a second type semiconductor layer defining the second surface, and a light emitting layer disposed between the first and second type semiconductor layers and spaced apart from the first and second surfaces. The microlenses are formed on the first surface and formed of a light transmissible substrate for epitaxial growth of the light emitting epitaxial layer. A method for manufacturing the light emitting diode device is also disclosed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 22, 2021
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Zhibai Zhong, Jinjian Zheng, Lixun Yang, Chia-En Lee, Chen-Ke Hsu, Junyong Kang
  • Patent number: 11034056
    Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include intentional or imposed wafer shapes that are configured to reduce manufacturing problems associated with deformation, bowing, or sagging of such wafers due to gravitational forces or from preexisting crystal stress. Intentional or imposed wafer shapes may comprise SiC wafers with a relaxed positive bow from silicon faces thereof. In this manner, effects associated with deformation, bowing, or sagging for SiC wafers, and in particular for large area SiC wafers, may be reduced. Related methods for providing SiC wafers with relaxed positive bow are disclosed that provide reduced kerf losses of bulk crystalline material. Such methods may include laser-assisted separation of SiC wafers from bulk crystalline material.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: June 15, 2021
    Assignee: Cree, Inc.
    Inventors: Simon Bubel, Matthew Donofrio, John Edmond, Ian Currier
  • Patent number: 11038045
    Abstract: A semiconductor device includes a back barrier layer formed over a substrate, a first electron transit layer formed over the back barrier layer, an opening formed in the first electron transit layer and the back barrier layer, a second electron transit layer formed over the first electron transit layer, a side surface of the first electron transit layer at a side surface within the opening, a side surface of the back barrier layer at a side surface within the opening, and a surface of the back barrier layer at a bottom surface within the opening, an electron supply layer formed over the second electron transit layer, a drain electrode formed over the electron supply layer within the opening, and a gate electrode formed to cover a side surface of the electron supply layer at a side surface within the opening from an edge part of the opening.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: June 15, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Toshihiro Ohki
  • Patent number: 11038048
    Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 15, 2021
    Inventors: Jun-De Jin, Chan-Hong Chern
  • Patent number: 11038030
    Abstract: A Field Effect Transistor (FET) having a source, drain, and gate disposed laterally along a surface of a semiconductor and a field plate structure: having one end connected to the source; and having a second end disposed between the gate and the drain and separated from the drain by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 15, 2021
    Assignee: Raytheon Company
    Inventors: Christopher J. MacDonald, Kenneth A. Wilson, Kamal Tabatabaie Alavi, Adrian D. Williams
  • Patent number: 11031493
    Abstract: The present invention proposes a set of impurity doping configurations for GaN buffer in an AlGaN/GaN HEMT device to improve breakdown characteristics of the device. The breakdown characteristics depend on a unique mix of donor and acceptor traps and using carbon as a dopant increases both donor and acceptor trap concentrations, resulting in a trade-off in breakdown voltage improvement and device performance. A modified silicon and carbon co-doping is proposed, which enables independent control over donor and acceptor trap concentrations in the buffer, thus potentially improving breakdown characteristics of the device without adversely affecting the device performance.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 8, 2021
    Inventors: Mayank Shrivastava, Vipin Joshi
  • Patent number: 11024626
    Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 11011678
    Abstract: A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface of the crystal layer of the group 13 nitride includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part, observed by cathode luminescence. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 18, 2021
    Assignee: NGK INSULATORS, LTD.
    Inventors: Takayuki Hirao, Hirokazu Nakanishi, Mikiya Ichimura, Takanao Shimodaira, Masahiro Sakai, Takashi Yoshino
  • Patent number: 11005003
    Abstract: A semiconductor chip and a method for producing a semiconductor chip are disclosed. In an embodiment an electronic semiconductor chip includes a growth substrate with a growth surface, which is formed by a planar region having a plurality of three-dimensional surface structures on the planar region, a nucleation layer composed of oxygen-containing AlN directly disposed on the growth surface and a nitride-based semiconductor layer sequence disposed on the nucleation layer, wherein the semiconductor layer sequence is selectively grown from the planar region such that a growth of the semiconductor layer sequence on surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by an oxygen content of the nucleation layer.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: May 11, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Werner Bergbauer, Thomas Lehnhardt, Jürgen Off, Joachim Hertkorn
  • Patent number: 11003052
    Abstract: A mobile device including: at least an imaging element; and a light-emitting device that irradiates a subject in accordance with imaging of the imaging element, in which the light-emitting device includes a semiconductor light-emitting element, and the difference of the normalized spectral power distribution at a wavelength of 580 nm and a value B representing a difference between normalized spectral power distributions in a wavelength range from 540 nm to 610 nm and a wavelength range from 610 nm to 680 nm are appropriate values. By providing a wavelength control element, it is possible to improve the color reproducibility and the like of a captured image. The mobile device achieves both sensitivity improvement and color reproducibility in a trade-off relationship.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: May 11, 2021
    Assignee: CITIZEN ELECTRONICS CO., LTD.
    Inventors: Jo Kinoshita, Yuki Suto, Munetaka Itami, Kouichi Fukasawa, Makoto Arai
  • Patent number: 10998188
    Abstract: There is provided a gallium nitride laminated substrate including: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 4, 2021
    Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tomoyoshi Mishima, Hiroshi Ohta, Fumimasa Horikiri, Masatomo Shibata
  • Patent number: 10985205
    Abstract: A display panel and a method for manufacturing the display panel are provided. The method includes providing a first substrate, forming a buffer layer including at least one first buffer layer on a first side of the first substrate; forming a LED structure including a first LED structure on a side of the buffer layer facing away from the first substrate, forming a planarization layer covering the LED structure on a side of the LED structure facing away from the buffer layer, forming an electrode structure connected to the LED units on a side of the planarization layer facing away from the LED structure, and forming a control circuit on a side of the electrode structure facing away from the LED structure, where the control circuit is electrically connected to the electrode structure and configured to control operation states of the LED units.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: April 20, 2021
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Jujian Fu
  • Patent number: 10978367
    Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 13, 2021
    Assignee: PANASONIC INTELLECTUAL PROPRETY MANAGEMENT CO., LTD.
    Inventors: Chiaki Kudou, Takashi Hasegawa, Kouichi Saitou
  • Patent number: 10971610
    Abstract: A high electron mobility transistor (HEMT) includes a substrate; a buffer layer over the substrate, a GaN layer over the buffer layer, a first AlGaN layer over the GaN layer, a first AlN layer over the AlGaN layer, and a p-GaN layer over the first AlN layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Chun-Liang Hou, Wen-Jung Liao
  • Patent number: 10964802
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third layers, and a first insulating layer. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The first insulating layer includes first and second inter-layer regions. The second layer includes first and second intermediate regions. The first intermediate region is provided between the first partial region and the first inter-layer region. The second intermediate region is provided between the second partial region and the second inter-layer region. The third layer includes first to third nitride regions. The first inter-layer region is between the first intermediate region and the first nitride region. The second inter-layer region is between the second intermediate region and the second nitride region.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 30, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira Mukai, Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Patent number: 10964535
    Abstract: A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: March 30, 2021
    Assignee: QROMIS, INC.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens