Diamond Or Silicon Carbide Patents (Class 257/77)
  • Patent number: 11990553
    Abstract: A merged PiN Schottky (MPS) diode includes a substrate, a first epitaxial layer of a first conductivity type, doped regions of a second conductivity type, a second epitaxial layer of the first conductivity type, and a Schottky metal layer. The first epitaxial layer is disposed on the first surface of the substrate. The doped regions are disposed in a surface of the first epitaxial layer, wherein the doped regions consist of first portions and second portions, the first portions are electrically floating, and the second portions are electrically connected to a top metal. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein trenches are formed in the second epitaxial layer to expose the second portions of the doped regions. The Schottky metal layer is conformally deposited on the second epitaxial layer and the exposed second portions of the doped regions.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: May 21, 2024
    Assignee: LEAP Semiconductor Corp.
    Inventors: Wei-Fan Chen, Kuo-Chi Tsai
  • Patent number: 11990543
    Abstract: A semiconductor device includes a vertical transistor and a body diode. Various improvements to the semiconductor device allow for improved performance of the body diode, in particular to reduced snappiness and increased softness.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: May 21, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Kijeong Han, Sei-Hyung Ryu, Daniel Jenner Lichtenwalner
  • Patent number: 11985897
    Abstract: A semiconductor device includes a semiconductor layer, a first electrode on a first surface of the semiconductor layer, a plurality of second electrodes on a second surface of the semiconductor layer, a control electrode between the first electrode and each of the plurality of second electrodes and electrically insulated from the semiconductor layer and each of the plurality of second electrodes, and a resin layer partially covering the second surface of the semiconductor layer and having a plurality of openings through which the respective second electrodes are at least partially exposed. Each of the plurality of openings has rounded corners. The device further includes a sensor element above the second surface of the semiconductor layer and covered by a first part of the resin layer surrounded by the openings.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: May 14, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Emiko Adachi, Yukie Nishikawa, Kotaro Zaima
  • Patent number: 11984498
    Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 14, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11984474
    Abstract: There is disclosed a structure in a wide band gap material such as silicon carbide wherein there is a buried grid and shields covering at least one middle point between two adjacent parts of the buried grid, when viewed from above. Advantages of the invention include easy manufacture without extra lithographic steps compared with standard manufacturing process, an improved trade-off between the current conduction and voltage blocking characteristics of a JBSD comprising the structure.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 14, 2024
    Assignee: II-VI ADVANCED MATERIALS, LLC
    Inventor: Hossein Elahipanah
  • Patent number: 11975613
    Abstract: A variable-gauge train control apparatus for a variable-gauge train having a gauge variable in a gauge conversion section includes: a plurality of main motors that transmits driving force to axles and wheels; a plurality of inverters that outputs voltage to at least one of the main motors; and voltage control units that control the individual output voltages of the plurality of inverters. Each of the voltage control units corresponds to one of the inverters and, when at least one of the axles to be subjected to the driving force controlled by the corresponding one inverter is within the gauge conversion section, controls the speed of the associated main motors by using, as a speed command value, a train speed converted into a rotational frequency.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 7, 2024
    Assignees: MITSUBISHI ELECTRIC CORPORATION, KYUSHU RAILWAY COMPANY
    Inventors: Kohei Fujitani, Shinsuke Kadoi, Tsuyoshi Morimitsu, Yuichi Mimura, Soichiro Watanabe
  • Patent number: 11978789
    Abstract: Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 7, 2024
    Assignee: HRL LABORATORIES, LLC
    Inventor: Biqin Huang
  • Patent number: 11973027
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Yu Chou, Jr-Hung Li, Liang-Yin Chen, Su-Hao Liu, Tze-Liang Lee, Meng-Han Chou, Kuo-Ju Chen, Huicheng Chang, Tsai-Jung Ho, Tzu-Yang Ho
  • Patent number: 11967651
    Abstract: A silicon carbide power diode device has a silicon carbide substrate on which a silicon carbide epitaxial layer with an active region is provided. A Schottky metal layer is on the active region, and a first electrode layer is on the Schottky metal layer. A first ohmic contact is on the silicon carbide substrate, and a second electrode layer is on the first ohmic contact. The active region of the silicon carbide epitaxial layer has a plurality of first P-type regions, a plurality of second P-type regions, and N-type regions. The first P-type regions and the second P-type regions lacking an ohmic contact are spaced apart with dimensions of the second P-type regions being minimized and the N-type regions being maximized for given dimensions of the first P-type region. Second ohmic contacts are located between the first P-type region and the Schottky metal layer.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: April 23, 2024
    Assignee: XIAMEN SANAN INTEGRATED CIRCUIT CO., LTD.
    Inventors: Yonghong Tao, Zhidong Lin, Zhigao Peng
  • Patent number: 11967441
    Abstract: The present invention relates to a metal wiring, to be formed on a flexible substrate, including a sintered body of silver particles. The sintered body constituting the metal wiring has a volume resistivity of 20 ??·cm or less, hardness of 0.38 GPa or less, and a Young's modulus of 7.0 GPa or less. A conductive sheet provided with the metal wiring can be produced by applying/calcinating, on a substrate, a metal paste containing, as a solid content, silver particles having prescribed particle size and particle size distribution, and further containing, as a conditioner, an ethyl cellulose having a number average molecular weight of 10,000 or more and 90,000 or less. The metal wiring of the present invention is excellent in bending resistance with change in electrical characteristics suppressed even through repetitive bending deformation.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: April 23, 2024
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventors: Hiroki Sato, Yuusuke Ohshima, Shigeyuki Ootake
  • Patent number: 11961904
    Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 16, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Siemieniec, Wolfgang Jantscher, David Kammerlander
  • Patent number: 11955543
    Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; a gate electrode extending in a first direction; a silicon carbide layer between the first electrode and the second electrode and including a first silicon carbide region of a first conductive type having a first region facing the gate electrode and a second region in contact with the first electrode, a second silicon carbide region of a second conductive type, and a third silicon carbide region of a second conductive type, the first region being interposed between the second silicon carbide region and the third silicon carbide region. A first width of the first region in a second direction perpendicular to the first direction is 0.5 ?m or more than and 1.2 ?m or less. A second width of the second region in the second direction 0.5 ?m or more than and 1.5 ?m or less.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: April 9, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroshi Kono
  • Patent number: 11948976
    Abstract: A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Koichi Murata
  • Patent number: 11949014
    Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first, second, third and fourth fin structures over a substrate. The first and the second fin structures have a first and a second sidewall surfaces respectively. The third and the fourth fin structure have a third and a fourth sidewall surfaces respectively. The first and the second sidewall surfaces extend along a first direction. The third and the fourth sidewall surfaces extend along a second direction different from the first direction. A first and a second isolation structures are over the substrate and surrounding the first and the second fin structure and surrounding the third and the fourth fin structures respectively. A distance between top portions of the third and the fourth sidewall surfaces is greater than that between top portions of the first and the second sidewall surfaces.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Barn Chen, Ting-Huang Kuo, Shiu-Ko Jangjian, Chi-Cherng Jeng
  • Patent number: 11948796
    Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 2, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Chen-Ying Wu, Abhishek Dube, Chia Cheng Chin, Saurabh Chopra
  • Patent number: 11942538
    Abstract: In the direction from the first main surface toward the second main surface through each of the second impurity region and the fourth impurity region, a concentration profile of an n-type impurity has a second relative maximum value and a fourth relative maximum value located closer to the first main surface than a position where the second relative maximum value is exhibited. The fourth relative maximum value is larger than the third relative maximum value, the third relative maximum value is larger than the second relative maximum value, and the second relative maximum value is larger than the first relative maximum value.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: March 26, 2024
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Yu Saitoh
  • Patent number: 11942537
    Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n? type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: March 26, 2024
    Assignee: Odyssey Semiconductor, Inc.
    Inventors: James R. Shealy, Richard J. Brown
  • Patent number: 11942401
    Abstract: This disclosure relates to a discrete half bridge semiconductor device including a first cascode arrangement and a second cascode arrangement. Each of the first cascode and second cascode arrangements include a high voltage FET device die and a low voltage FET device die; and the source of the high voltage FET device die is mounted on and connected to a drain of the low voltage FET device die. The source of the low voltage FET device die and gate of the high voltage FET device die are connected to a drain terminal of the high voltage FET device die of the second cascode arrangement at a common connection pad.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: March 26, 2024
    Assignee: Nexperia B.V.
    Inventors: Dilder Chowdhury, Ricardo Lagmay Yandoc, Saurabh Pandey
  • Patent number: 11935919
    Abstract: A method for manufacturing a semiconductor device includes forming, on first and second impurity layers on a termination region side, an insulating layer, forming a first metal film and a second metal film in this order on the insulating layer and a drift layer, performing dry etching on the first and second metal films all together so that a position of a first end of a metallized layer, which is a remaining part of the first metal film, in the interface region on the termination region side and a position of a second end of an electrode, which is a remaining part of the second metal film, in the interface region on the terminal region side are the same in plan view. The first and second ends are closer to the active region than an end of the second impurity layer on the termination region side in plan view.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: March 19, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Yasushi Takaki, Kensuke Taguchi, Kosuke Miyazaki
  • Patent number: 11935744
    Abstract: A method for manufacturing a nitride semiconductor device includes the steps of growing a GaN channel layer on an SiC substrate using a vertical MOCVD furnace set at a first temperature using H2 as a carrier gas, and TMG and NH3 as raw materials, holding the SiC substrate having the grown GaN channel layer in the MOCVD furnace set at a second temperature higher than the first temperature using H2 as a carrier gas, the MOCVD furnace being supplied with NH3, and growing an InAlN layer on the GaN channel layer using the MOCVD furnace set at a third temperature lower than the first temperature using N2 as a carrier gas, and TMI, TMA, and NH3 as raw materials.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 19, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Isao Makabe, Ken Nakata
  • Patent number: 11929420
    Abstract: A semiconductor device includes a semiconductor layer structure that comprises silicon carbide, a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a base gate dielectric layer that is on the semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer opposite the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. A dielectric constant of the capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: March 12, 2024
    Assignee: Wolfspeed, Inc.
    Inventor: Daniel J. Lichtenwalner
  • Patent number: 11929343
    Abstract: There is provided a novel Cu bonding wire that achieves a favorable FAB shape and achieve a favorable bond reliability of the 2nd bonding part even in a rigorous high-temperature environment. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of 90 atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: March 12, 2024
    Assignee: NIPPON MICROMETAL CORPORATION
    Inventors: Daizo Oda, Motoki Eto, Takashi Yamada, Teruo Haibara, Ryo Oishi
  • Patent number: 11923463
    Abstract: This disclosure provides a diode including a semiconductor region having at least one two-dimensional carrier channel of a first conductivity type. The diode also includes a plurality of sidewalls exposed in the semiconductor region defining at least one trench extending through the at least one two-dimensional carrier channel and a material of a second conductivity type, the second conductivity type being the other of the n-type and the p-type conductivity, disposed on the plurality of sidewalls and in contact with the at least one two-dimensional carrier channel. The diode also includes an anode material in contact with at least a portion of the semiconductor region and in contact with at least a portion of the material of the second conductivity type, and a cathode material in contact with the at least one two-dimensional carrier channel.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: March 5, 2024
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: Yuhao Zhang, Ming Xiao
  • Patent number: 11923450
    Abstract: There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions comprising an access region and a JFET region defining the length of the MOS channel, and wherein the access region and the JFET region are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel is defined by simultaneous creating n-type regions on both sides of the channel using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 5, 2024
    Assignee: II-VI ADVANCED MATERIALS, LLC
    Inventors: Adolf Schoner, Sergey Reshanov, Nicolas Thierry-Jebali, Hossein Elahipanah
  • Patent number: 11916112
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as a device surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, a main surface insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface continuous to the side surface of the SiC semiconductor layer, and a boundary modified layer including a first region that is modified to be of a property differing from the SiC monocrystal and a second region that is modified to be of a property differing from the insulating material, and being formed across the side surface of the SiC semiconductor layer and the insulating side surface of the main surface insulating layer.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 27, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Yasuhiro Kawakami, Yuki Nakano, Masaya Ueno, Seiya Nakazawa, Sawa Haruyama, Yasunori Kutsuma
  • Patent number: 11908929
    Abstract: A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: February 20, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11908955
    Abstract: A Schottky barrier diode 1 includes: a semiconductor substrate made of gallium oxide; a drift layer made of gallium oxide; an anode electrode brought into Schottky contact with an upper surface of the drift layer; and a cathode electrode brought into ohmic contact with a lower surface of the semiconductor substrate. A ring-shaped outer peripheral trench is formed in the upper surface of the drift layer, and the anode electrode is partly filled in the outer peripheral trench. A ring-shaped back surface trench is formed in the lower surface of the semiconductor substrate such that the bottom thereof reaches the drift layer. This limits a current path to the area surrounded by the back surface trench, thereby mitigating electric field concentration in the vicinity of the bottom of the outer peripheral trench.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: February 20, 2024
    Assignee: TDK CORPORATION
    Inventors: Jun Arima, Minoru Fujita, Jun Hirabayashi
  • Patent number: 11901181
    Abstract: A method for removing a portion of a crystalline material (e.g., SiC) substrate includes joining a surface of the substrate to a rigid carrier (e.g., >800 ?m thick), with a subsurface laser damage region provided within the substrate at a depth relative to the surface. Adhesive material having a glass transition temperature above 25° C. may bond the substrate to the carrier. The crystalline material is fractured along the subsurface laser damage region to produce a bonded assembly including the carrier and a portion of the crystalline material. Fracturing of the crystalline material may be promoted by (i) application of a mechanical force proximate to at least one carrier edge to impart a bending moment in the carrier; (ii) cooling the carrier when the carrier has a greater coefficient of thermal expansion than the crystalline material; and/or (iii) applying ultrasonic energy to the crystalline material.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: February 13, 2024
    Assignee: WOLFSPEED, INC.
    Inventors: Matthew Donofrio, John Edmond, Hua-Shuang Kong, Elif Balkas
  • Patent number: 11901432
    Abstract: An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N? drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: February 13, 2024
    Assignee: GENESIC SEMICONDUCTOR INC.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11901478
    Abstract: A method of transferring multiple semiconductor devices from a first substrate to a second substrate comprises the steps of forming the multiple semiconductor devices adhered on the first substrate, wherein the multiple semiconductor devices comprises a first semiconductor device and a second semiconductor device, and the first semiconductor device and the second semiconductor device have a first gap between thereof; separating the first semiconductor device and the second semiconductor device from the first substrate; sticking the first semiconductor device and the second semiconductor device to a surface of the second substrate, wherein the first semiconductor device and the second semiconductor device have a second gap between thereof; wherein the first gap and the second gap are different.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 13, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Hao-Min Ku, You-Hsien Chang, Shih-I Chen, Fu-Chun Tsai, Hsin-Chih Chiu
  • Patent number: 11901407
    Abstract: A semiconductor device having an improved junction termination extension region is provided. The disclosure particularly relates to diodes having such an improved junction termination extension. The semiconductor device includes an active area extending in a first direction, and a junction termination extension, ‘JTE’, region of a first charge type surrounding the active area. The JTE region includes a plurality of field relief sub-regions that each surround the active area and that are mutually spaced apart in a direction perpendicular to a circumference of the active area. The plurality of field relief sub-regions includes a first group of field relief sub-regions, and for each field relief sub-region of the first group, a plurality of field relief elements of a second charge type is provided therein, which field relief elements are mutually spaced apart in a circumferential direction with respect to the active area.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: February 13, 2024
    Assignee: Nexperia B.V
    Inventors: Romain Esteve, Tim Böttcher
  • Patent number: 11894440
    Abstract: Disclosed a silicon carbide MOSFET device and manufacturing method thereof. The method includes: forming a patterned first barrier layer on an upper surface of the substrate; forming a base region of a second doping type extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask; forming a source region of the first doping type in the substrate; forming a contact region of the second doping type in the substrate; and forming a gate structure, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer. The method of the present disclosure not only reduces one photoetching process and saves cost, but also realizes a short channel and reduces an on-resistance of the device.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: February 6, 2024
    Assignee: HANGZHOU SILICON-MAGIC SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Jiakun Wang, Hui Chen
  • Patent number: 11888032
    Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies AG
    Inventors: Caspar Leendertz, Thomas Basler, Paul Ellinghaus, Rudolf Elpelt, Michael Hell, Jens Peter Konrath, Shiqin Niu, Dethard Peters, Konrad Schraml, Bernd Leonhard Zippelius
  • Patent number: 11888056
    Abstract: A silicon carbide MOS-gated semiconductor device comprises a silicon carbide substrate, a drift layer, a first doped region, a second doped region, a plurality of third doped regions, a gate insulating layer, a gate electrode, an interlayer dielectric layer, and a metal layer. The gate electrode comprises a gate bus region and an active region. The active region comprises a plurality of gate electrode openings. The two adjacent gate electrode openings have a minimum width (Wg) which is satisfied the following formula: Wg>Wjfet+2×Lch+2×Lx Lch represents a channel length of channel regions, Wjfet represents a minimum width of JFET regions, and Lx represents a minimum overlapping length between the gate electrode and the second doped region.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 30, 2024
    Assignee: FAST SIC SEMICONDUCTOR INCORPORATED
    Inventor: Cheng-Tyng Yen
  • Patent number: 11881479
    Abstract: The present invention provides a nitride semiconductor device, including an insulating substrate, a substrate over the first surface of the insulating substrate, a first lateral transistor over a first region of the substrate, wherein the first lateral transistor includes a first nitride semiconductor layer formed over the substrate, and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer, and a second lateral transistor over a second region of the substrate, wherein the second lateral transistor includes a second nitride semiconductor layer formed over the substrate, and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer, and a separation trench formed over a third region, wherein the third region is between the first region and the second region.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: January 23, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Hirotaka Otake
  • Patent number: 11874303
    Abstract: A power semiconductor module includes: an electrically insulative frame having opposite mounting sides and a border wall that defines a periphery of the frame; a substrate seated in the frame; power semiconductor dies attached to the substrate; signal pins attached to the substrate and electrically connected to the power semiconductor dies; a busbar attached to the substrate and extending through the border wall; a receptacle in the border wall configured to receive a current sensor module and that exposes part of the busbar, the exposed part of the busbar having an opening; and a rotation bar jutting out from a sidewall of the receptacle and onto the exposed part of the busbar without obstructing the opening in the busbar, wherein the rotation bar forms an axis of rotation within the receptacle. A power electronic assembly that incorporates the power semiconductor module and corresponding method of production are also described.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: January 16, 2024
    Assignee: Infineon Technologies AG
    Inventors: Tomas Manuel Reiter, Christoph Koch, Dietmar Spitzer
  • Patent number: 11876116
    Abstract: A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n1), b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions (p2) on the first layer (n1), if necessary with aid of removing parts of the added semiconductor material to form separated second regions (p2) on the first layer (n1), and c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer (n1) to form first regions (p1). It is possible to manufacture a grid with rounded corners as well as an upper part with a high doping level.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: January 16, 2024
    Assignee: II-VI DELAWARE, INC.
    Inventors: Adolf Schoner, Sergey Reshanov, Nicolas Thierry-Jebali, Hossein Elahipanah
  • Patent number: 11869969
    Abstract: A semiconductor device includes a semiconductor substrate, an epitaxial layer disposed on the semiconductor substrate, a cell zone including multiple unit cells disposed in the epitaxial layer opposite to the semiconductor substrate, a transition zone having a doped region and surrounding the cell zone, a source electrode unit disposed on the epitaxial layer opposite to the semiconductor substrate, and multiple gate electrode units. Each unit cell includes a well region, a source region disposed in the well region, and a well contact region extending through the source region to contact the well region. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: January 9, 2024
    Assignee: HUNAN SAN'AN SEMICONDUCTOR CO., LTD.
    Inventors: Yonghong Tao, Wenbi Cai, Zhigao Peng, Lijun Li, Yuanxu Guo
  • Patent number: 11869983
    Abstract: A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 11869940
    Abstract: A feeder design is manufactured as a structure in a SiC semiconductor material comprising at least two p-type grids in an n-type SiC material (3), comprising at least one epitaxially grown p-type region, wherein an Ohmic contact is applied on the at least one epitaxially grown p-type region, wherein an epitaxially grown n-type layer is applied on at least a part of the at least two p-type grids and the n-type SiC material (3) wherein the at least two p-type grids (4, 5) are applied in at least a first and a second regions at least close to the at least first and second corners respectively and that there is a region in the n-type SiC material (3) between the first and a second regions without any grids.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: January 9, 2024
    Assignee: II-VI DELAWARE, INC.
    Inventors: Hossein Elahipanah, Nicolas Thierry-Jebali, Adolf Schoner, Sergey Reshanov
  • Patent number: 11869840
    Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: January 9, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Dethard Peters, Roland Rupp
  • Patent number: 11862687
    Abstract: A nitride semiconductor device is provided, comprising: a first nitride semiconductor layer of a first conductivity-type; a second nitride semiconductor layer of a second conductivity-type provided above the first nitride semiconductor layer; a junction region of a first conductivity-type which is provided to extend in a direction from a front surface of the second nitride semiconductor layer to the first nitride semiconductor layer and has a doping concentration NJFET equal to or higher than that of the first nitride semiconductor layer; and a source region of a first conductivity-type which is provided more shallowly than the junction region and has a doping concentration equal to or higher than the doping concentration NJFET, wherein a dopant of the source region is an element with an atomic weight larger than that of a dopant in the junction region.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryo Tanaka, Shinya Takashima, Hideaki Matsuyama, Katsunori Ueno, Masaharu Edo
  • Patent number: 11859313
    Abstract: An 8-inch SiC single crystal substrate of an embodiment has a diameter in a range of 195 mm to 205 mm, a thickness in a range of 300 ?m to 650 ?m, a SORI of 50 ?m or less, and an in-plane variation of the thickness of the substrate, which is the difference between the maximum and minimum substrate thickness at the center of the substrate and four points on the circumference of a circle having a radius half the radius of the substrate, is 1.5 ?m or less.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: January 2, 2024
    Assignee: Resonac Corporation
    Inventor: Tomohiro Shonai
  • Patent number: 11862477
    Abstract: A method for manufacturing a semiconductor device having a gallium oxide-based semiconductor layer includes: ion-implanting dopant into a gallium oxide-based semiconductor layer while heating the gallium oxide-based semiconductor layer; and annealing the gallium oxide-based semiconductor layer under an oxygen atmosphere, after the ion-implanting.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: January 2, 2024
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventors: Shuhei Ichikawa, Hiroki Miyake
  • Patent number: 11862672
    Abstract: [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. [Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 2, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Katsuhisa Nagao
  • Patent number: 11864476
    Abstract: An electronic device comprises a semiconductor memory that includes: a first line; a second line disposed over the first line to be spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a selection element layer disposed between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers disposed over or under the selection element layer or disposed over and under the selection element layer, the one or more electrode layers being adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer including a second carbon layer containing nitrogen, the first electrode layer including a first carbon layer containing a lower concentration of nitrogen or containing no nitrogen.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: January 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Byung Jick Cho, Yong Hun Sung, Ji Sun Han
  • Patent number: 11848211
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm?3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: December 19, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Patent number: 11848662
    Abstract: Embodiments of a single-chip ScAIN tunable filter bank include a plurality of switching elements, and a plurality of channel filters integrated on a monolithic platform. The monolithic platform may comprise a single crystal base and each of the switching elements may comprise at least one of a scandium aluminum nitride (ScAIN) or other Group III-Nitride transistor structure fabricated on the single crystal base. In these embodiments, each channel filter comprises a multi-layered ScAIN structure comprising one or more a single-crystal epitaxial ScAIN layers fabricated on the single crystal base. The ScAIN layers for each channel filter may be based on desired frequency characteristics of an associated one of the RF channels.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: December 19, 2023
    Assignee: Raytheon Company
    Inventors: Jason C. Soric, Jeffrey R. Laroche, Eduardo M. Chumbes, Adam E. Peczalski
  • Patent number: 11843061
    Abstract: A power semiconductor device has a semiconductor layer structure that includes a silicon carbide drift region having a first conductivity type, first and second wells in the silicon carbide drift region that are doped with dopants having a second conductivity type, and a JFET region between the first and second wells. The first and second wells each include a main well and a side well that is between the main well and the JFET region, and each side well includes a respective channel region. A doping concentration of the JFET region exceeds a doping concentration of the silicon carbide drift region, and a minimum width of an upper portion of the JFET region is greater than a minimum width of a lower portion of the JFET region.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: December 12, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Kijeong Han, Joohyung Kim, Sei-Hyung Ryu
  • Patent number: 11837629
    Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: December 5, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull