Diamond Or Silicon Carbide Patents (Class 257/77)
  • Patent number: 10418381
    Abstract: A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 17, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kensuke Yoshizumi
  • Patent number: 10415152
    Abstract: A p-type SiC single crystal having lower resistivity than the prior art is provided. This is achieved by a method for producing a SiC single crystal in which a SiC seed crystal substrate is contacted with a Si—C solution having a temperature gradient such that the temperature decreases from the interior toward the surface, to grow a SiC single crystal, the method comprising: using as the Si—C solution a Si—C solution containing Si, Cr and Al, wherein the Al content is 3 at % or greater based on the total of Si, Cr and Al; and contacting a (0001) face of the SiC seed crystal substrate with the Si—C solution to grow a SiC single crystal from the (0001) face.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 17, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takayuki Shirai
  • Patent number: 10410868
    Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 10411105
    Abstract: A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, an Al-based oxide film interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 10, 2019
    Assignees: ROHM CO., LTD., LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Akihiro Hikasa, Kazusuke Kato
  • Patent number: 10403723
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a second conductive type substrate including a first first-conductive-type doping layer and a plurality of devices on the second conductive type substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the first first-conductive-type doping layer, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the first first-conductive-type doping layer and the first nitride semiconductor layer, a first contact electrically connected to the first heterojunction interface, and a contact connector electrically connecting the first contact to the first first-conductive-type doping layer.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: September 3, 2019
    Assignee: LG Innotek Co., Ltd.
    Inventor: John Twynam
  • Patent number: 10396169
    Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10396170
    Abstract: A semiconductor device includes a transistor doping region of a vertical transistor structure arranged in a semiconductor substrate. Additionally, the semiconductor device includes a graphene layer portion located adjacent to at least a portion of the transistor doping region at a surface of the semiconductor substrate. The semiconductor device further includes a transistor wiring structure located adjacent to the graphene layer portion.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Guenther Ruhl, Roland Rupp
  • Patent number: 10388755
    Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating channel layers and sacrificial layers. The sacrificial layers are recessed relative to the channel layers. A metal-doped insulator layer is in contact with sidewalls of the channel layers. The metal-doped insulator layer is annealed to form a metallic layer at an interface between the metal-doped insulator layer and the channel layers. The metal-doped insulator layer is etched back to form inner spacers. Source/drain regions are formed in contact with the metallic layer. The sacrificial layers are etched away and a gate stack is formed on and around the channel layers.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li
  • Patent number: 10389263
    Abstract: Motor drive power conversion systems are provided including a rectifier and a switching inverter, wherein the switching devices of the rectifier, the inverter and/or of a DC/DC converter are silicon carbide switches, such as silicon carbide MOSFETs. Driver circuits are provided for providing bipolar gate drive signals to the silicon carbide MOSFETs, including providing negative gate-source voltage for controlling the off state of enhancement mode low side drivers and positive gate-source voltage for controlling the off state of enhancement mode high side drivers.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: August 20, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Kevin Baumann, Richard Lukaszewski, Rangarajan Tallam, Lixiang Wei, Lee Gettelfinger, Garron Morris, Bruce Weiss, Neil Gollhardt, Navid R. Zargari, William Brumsickle, Robert Wright Reese, Stephen E. Denning
  • Patent number: 10381442
    Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Chun-chen Yeh
  • Patent number: 10381445
    Abstract: A silicon carbide semiconductor device includes: a drift layer in contact with a first main surface and having a first conductivity type; a body region located in the drift layer, in contact with the first main surface, and having a second conductivity type; and a protruding portion having the second conductivity type and connected to a bottom of the body region. A manufacturing method includes forming, in the drift layer of a silicon carbide substrate, by ion implantation, the body region, the protruding portion, a JTE region, and at least one guard ring region, each having the second conductivity type.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: August 13, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takashi Tsuno
  • Patent number: 10381568
    Abstract: A photoelectric conversion device including a photoelectric conversion module, wherein the photoelectric conversion module includes a carbon nanotube structure and a cover structure, the carbon nanotube structure includes a carbon nanotube, the carbon nanotube includes two metallic carbon nanotube segments and one semiconducting carbon nanotube segment between the two metallic carbon nanotube segments, the cover structure covers only a portion of the semiconducting carbon nanotube segment, the part area is a covered area.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: August 13, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jiang-Tao Wang, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10381453
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide layer including an n-type region having an n conductivity type and a p-type region having a p conductivity type, forming a material layer containing titanium, aluminum, and silicon on the n-type region and the p-type region, and forming an electrode layer in contact with the n-type region and the p-type region by heating the material layer. In forming a material layer, composition of the material layer is determined such that a point (x, y, z) (x, y, and z each being a numeric value greater than 0) representing a composition ratio among titanium, aluminum, and silicon is included in a first triangular pyramidal region having four points of the origin (0, 0, 0), a point (1, 2, 2), a point (2, 1, 2) and a point (2, 2, 1) as vertices.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: August 13, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: So Tanaka, Shunsuke Yamada, Takahiro Matsui, Hideto Tamaso
  • Patent number: 10381441
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, and a first insulating film. The first electrode includes a first conductive region. The second electrode includes a second conductive region. The first semiconductor region includes first to fourth partial regions. The second semiconductor region includes a fifth partial region. The third semiconductor region includes a sixth partial region provided between the fourth partial region and the fifth partial region. The fourth semiconductor region includes is electrically connected to the second conductive region, and includes first and second portions. The first insulating film includes first to third insulating regions. The first insulating region is positioned between the first portion and the first conductive region. The second insulating region contacts the fourth and sixth partial regions.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 13, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Kyogoku, Ryosuke Iljima
  • Patent number: 10381519
    Abstract: A light emitting device package, according to an embodiment, includes: a substrate; a light emitting structure that is disposed below the substrate and includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; a first bonding pad connected with the first conductive type semiconductor layer while being embedded in a through-hole exposed the first conductive type semiconductor layer by passing through the active layer and the second conductive type semiconductor layer; a second bonding pad that is disposed below the second conductive type semiconductor layer while being spaced apart from the first bonding pad and is connected with the second conductive type semiconductor layer; a first insulation layer disposed on the lateral portion of the light emitting structure in the through-hole and on the lower inner edge of the light emitting structure; and a second insulation layer disposed between the first insulation layer and the first bonding pad in the
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: August 13, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jae Won Seo, Hoe Jun Kim, Bum Jin Yim, Jun Hee Hong
  • Patent number: 10373952
    Abstract: A semiconductor device includes first and second transistors connected to the same power supply. Each of the first and second transistors includes, under a channel region of a low concentration provided between a source region and a drain region of a first conductivity type, an impurity region of a second conductivity type having a higher concentration. The thickness of the gate insulating film in one of the first and second transistors is made larger than the thickness of the gate insulating film in the other one.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 6, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazushi Fujita
  • Patent number: 10374050
    Abstract: A titanium layer and a nickel layer are sequentially formed on a back surface of a SiC wafer. Next, by high-temperature heat treatment, the SiC wafer is heated and the titanium layer and the nickel layer are sintered forming a nickel silicide layer that includes titanium carbide. By this high-temperature heat treatment, an ohmic contact of the SiC wafer and the nickel silicide layer is formed. Thereafter, on the nickel silicide layer, a back surface electrode multilayered structure is formed by sequentially stacking a titanium layer, a nickel layer, and a gold layer. Here, in forming the nickel layer that configures a back surface electrode multilayered structure, the nickel layer is formed under a condition that satisfies 0.0<y<?0.0013x+2.0, where the thickness of the nickel layer is x [nm] and the deposition rate of the nickel layer is y [nm/second]. Thus, peeling of the back surface electrode can be suppressed.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: August 6, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Fumikazu Imai, Tsunehiro Nakajima
  • Patent number: 10373880
    Abstract: A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 6, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 10367086
    Abstract: Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: July 30, 2019
    Assignee: HRL Laboratories, LLC
    Inventor: Biqin Huang
  • Patent number: 10367501
    Abstract: A semiconductor device according to an embodiment includes: a normally-off transistor having a first source, a first drain, and a first gate; a normally-on transistor having a second source electrically connected to the first drain, a second drain, and a second gate; a first capacitor having a first end and a second end, wherein the second end is electrically connected to the second gate; a first diode having a first anode electrically connected between the second end and the second gate, and a first cathode; a gate drive circuit electrically connected to the first gate and the first end; and a switch having a third end and a fourth end, wherein the third end is electrically connected to the first end.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 30, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kentaro Ikeda
  • Patent number: 10367092
    Abstract: In a vertical MOSFET of a trench gate structure, a high-concentration implantation region is provided in a p-type base region formed from a p-type silicon carbide layer formed by epitaxial growth, so as to include a portion in which a channel is formed. The high-concentration implantation region is formed by ion implantation of a p-type impurity into the p-type silicon carbide layer. The high-concentration implantation region is formed by p-type ion implantation and has an impurity concentration profile in which concentration differences in a depth direction form a bell-shaped curve at a peak of impurity concentration that is higher than that of the p-type silicon carbide layer. In the p-type base region, disorder occurs partially in the crystal structure consequent to the ion implantation for forming the high-concentration implantation region.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Setsuko Wakimoto, Masanobu Iwaya
  • Patent number: 10361192
    Abstract: A semiconductor device with a trench gate structure in a semiconductor body with a hexagonal crystal lattice is disclosed. In an embodiment a semiconductor device includes a semiconductor body with a hexagonal crystal lattice, wherein a mean surface plane of a first surface of the semiconductor body is tilted with respect to a <1-100> crystal direction of the hexagonal crystal lattice by an off-axis angle, a trench gate structure extending into the semiconductor body and at least two transistor mesas formed from portions of the semiconductor body and adjoining the trench gate structure, wherein sidewalls of the at least two transistor mesas are aligned with a (11-20) crystal plane and deviate from a normal to the mean surface plane by at most 5 degrees, and wherein each transistor mesa comprises a MOS gate channel.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 23, 2019
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Romain Esteve, Dethard Peters
  • Patent number: 10361296
    Abstract: Metal-Oxide-Semiconductor (MOS) controlled semiconductor devices and methods of making the devices are provided. The devices include a gate which controls current flow through channel regions positioned between source/emitter and drain regions of the device. The devices include a gate oxide layer having a variable thickness. The thickness of the gate oxide layer under the edge of the gate and over the source/emitter regions is different than the thickness over the channel regions of the device. The oxide layer thickness near the edge of the gate can be greater than the oxide layer thickness over the channel regions. The source/emitter regions can be implanted to provide enhanced oxide growth during gate oxide formation. The source/emitter region can include regions that are implanted to provide enhanced oxide growth during gate oxide formation and regions which do not provide enhanced oxide growth during gate oxide formation. The devices can be SiC devices such as SiC MOSFETs and SiC IGBTs.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 23, 2019
    Assignee: Monolith Semiconductor Inc.
    Inventors: Kevin Matocha, Sauvik Chowdhury, Kiran Chatty, John Nowak
  • Patent number: 10355619
    Abstract: A semiconductor module according to an embodiment includes an insulating substrate having a power conversion circuit mounted thereon, a first transistor constituting an upper arm, a second transistor constituting a lower arm, a first input interconnection pattern coupled to a positive-side input terminal, a second input interconnection pattern coupled to a negative-side input terminal, an output interconnection pattern coupled to an output terminal, and an absorbing device configured to absorb surge voltage, wherein the first input interconnection pattern includes a first-transistor mounting area on which the first transistor is mounted, wherein the output interconnection pattern includes a second-transistor mounting area on which the second transistor is mounted, wherein the second input interconnection pattern includes an absorbing-device connecting area disposed between the first and second transistor mounting areas, and wherein the absorbing-device connecting area is electrically coupled to the first-tran
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 16, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hirotaka Oomori
  • Patent number: 10347694
    Abstract: Disclosed is a pixel arrangement with a shared blue light emitting layer (7), comprising m rows and n columns of first pixel units, the first pixel units are blue light sub-pixels (B), m is a non-zero natural number, n is a natural number larger than or equal to 2, wherein, two columns of second pixel units are arranged between neighboring first pixel units, each of the second pixel units comprises a red light sub-pixel (R), a green light sub-pixel (G) and a yellow light sub-pixel (Y) that are arranged in a juxtaposed manner. By properly modifying the pixel arrangement of the device configuration, light emitting in four colors can be achieved by using only two or less sets of low precision masks in the preparation process, so that the resolution is increased with reduced cost, and as compared to conventional pixel arrangement, the PPI can be doubled, reaching 600 PPI.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 9, 2019
    Assignees: KunShan New Hat Panel Display Technology Center Co., Ltd., Beijing Visionox Technology Co., Ltd.
    Inventors: Weiwei Li, Song Liu, Xiuqi Huang, Zhizhong Luo
  • Patent number: 10347732
    Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Xiaoju Wu
  • Patent number: 10347724
    Abstract: A gate insulating film covers a trench penetrating through a source region and a body region and reaching a drift layer in each of a first cell region and a second cell region. The gate electrode is provided in the trench. A high-concentration layer of the first conductivity type is provided between the drift layer and the body region in the first cell region and has a second impurity concentration higher than the first impurity concentration. A current restriction layer is provided between the drift layer and the body region in the second cell region and has the first conductivity type and a third impurity concentration higher than the first impurity concentration and lower than the second impurity concentration.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 9, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Katsutoshi Sugawara, Yasuhiro Kagawa, Naruhisa Miura
  • Patent number: 10347620
    Abstract: Provided is a semiconductor device having an ESD protection diode and a vertical MOSFET in which desired ESD tolerance is obtained without reducing the active region size or increasing the chip size. The semiconductor device includes: a substrate; a drain region and a source region in the substrate; a base region between the drain region and the source region; a gate electrode comprising a first polysilicon layer, and being in contact with the base region across a gate insulating film so that a channel is formed in the base region; and a bidirectional diode in which the gate electrode, a second polysilicon layer, and a third polysilicon layer are arranged in the stated order in a direction perpendicular to a front surface of the substrate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 9, 2019
    Assignee: ABLIC INC.
    Inventors: Yuki Osuga, Hirofumi Harada, Mio Mukasa
  • Patent number: 10340344
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 2, 2019
    Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi
  • Patent number: 10332817
    Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 25, 2019
    Assignee: Cree, Inc.
    Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
  • Patent number: 10325791
    Abstract: A light emitting diode (LED) includes an elastomeric material that facilitates adhesive attachment with a pick-up head for pick and place manufacturing operations. The LED includes an epitaxial layer defining a mesa structure and a light emitting surface. The mesa structure includes an active layer to emit light, and the emitted light is reflected at the mesa structure toward a light emitting region of the light emitting surface and transmitted at the light emitting region. An elastomeric material is on a portion of the light emitting surface, such as the light emitting region or a passive region. At the light emitting region, the elastomeric material may be shaped as a lens that collimates light transmitted from the light emitting region, and also facilitates adhesion to the pick-up head. At the passive region, the elastomeric material facilitates adhesion to the pick-up head without interfering with light emitted from the light emitting region.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 18, 2019
    Assignee: Facebook Technologies, LLC
    Inventors: Pooya Saketi, Patrick Joseph Hughes, William Padraic Henry, Joseph O'Keeffe
  • Patent number: 10326012
    Abstract: A semiconductor device includes a semiconductor substrate, a source electrode, a drain electrode, and a gate electrode disposed on the semiconductor substrate via a gate insulator film. The semiconductor substrate includes a first portion constituted of GaN and a second portion constituted of AlxGa(1-x)N (0<x?1). The first portion includes an n-type source region being in contact with the source electrode, an n-type drain region being in contact with the drain electrode, a p-type body region intervening between the source region and the drain region and being in contact with the source electrode, and an n-type drift region intervening between the body region and the drain region and having a carrier density that is lower than a carrier density of the drain region. The second portion includes a barrier region being in contact with each of the source electrode, the body region and the drift region.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 18, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi Watanabe, Hiroyuki Ueda, Tomohiko Mori
  • Patent number: 10325990
    Abstract: A HEMT device is provided. The HEMT device includes a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, an insulating layer, a gate, a source, a drain, a trench, and a metal layer. The buffer layer is formed on the substrate. The first epitaxial layer is formed on the buffer layer. The second epitaxial layer is formed on the first epitaxial layer. The insulating layer is formed on the second epitaxial layer. The gate is disposed in the insulating layer. The source and the drain are disposed in the insulating layer. The trench passes through the insulating layer and the second epitaxial layer, and extends into the first epitaxial layer. The metal layer is formed on the insulating layer to connect to the source, and is filled into the trench to electrically connect to the first epitaxial layer and the source.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 18, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
  • Patent number: 10326014
    Abstract: In at least some embodiments, a semiconductor device comprises a source region is formed within a well. The source region comprises a first dopant type, and the well comprises a second dopant type opposite the first dopant type. A termination region is formed within the well, the termination region being aligned with the source region and having an end adjacent to and spaced apart from an end of the source region. The termination region comprises a semiconducting material having the second dopant type. A preselected concentration value of the dopant in the termination region is greater than a concentration value of the second dopant type in the well.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: June 18, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Xiaoju Wu
  • Patent number: 10323335
    Abstract: A SiC epitaxial wafer includes: a substrate having an off angle of less than 4 degrees; and a SiC epitaxial growth layer disposed on the substrate having the off angle of less than 4 degrees, wherein an Si compound is used for a supply source of Si, and a C compound is used as a supply source of C, for the SiC epitaxial growth layer, wherein the uniformity of carrier density is less than 10%, and the defect density is less than 1 count/cm2; and a C/Si ratio of the Si compound and the C (carbon) compound is within a range of 0.7 to 0.95. There is provide a high-quality SiC epitaxial wafer excellent in film thickness uniformity and uniformity of carrier density, having the small number of surface defects, and capable of reducing costs, also in low-off angle SiC substrates on SiC epitaxial growth.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 18, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Hirokuni Asamizu
  • Patent number: 10319851
    Abstract: A semiconductor device includes an n+ type silicon carbide substrate, an n? type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 11, 2019
    Assignee: Hyundai Motor Company
    Inventors: Dae Hwan Chun, Youngkyun Jung, NackYong Joo, Junghee Park, JongSeok Lee
  • Patent number: 10320309
    Abstract: A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: June 11, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Hiroyuki Sakairi
  • Patent number: 10319819
    Abstract: A semiconductor device according to an embodiment includes a SiC semiconductor layer, a gate electrode, a gate insulating film provided between the SiC semiconductor layer and the gate electrode, and a region that is provided between the SiC semiconductor layer and the gate insulating film and includes at least one element selected from the group consisting of antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), and lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu). The concentration of the at least one element is equal to or greater than 1×1019 cm?3 and equal to or less than 2.4×1022 cm?3.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 11, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Takashi Shinohe
  • Patent number: 10297685
    Abstract: According to an embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of third electrodes, and a plurality of gate electrodes. The gate electrodes and the third electrodes are arranged parallel in a second direction and periodically with a third arrangement cycle such that the ratio of the number of the gate electrodes and the third electrodes in the first region is m3 to m4 (m3, m4 being positive integers and m3 being more than or equal to m4).
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 21, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Makoto Mizukami
  • Patent number: 10297526
    Abstract: A semiconductor device structure includes a layer of single crystal compound semiconductor material; and a layer of polycrystalline CVD diamond material. The layer of polycrystalline CVD diamond material is bonded to the layer of single crystal compound semiconductor material via a bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm. The effective thermal boundary resistance as measured by transient thermoreflectance at an interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m2K/GW with a variation of no more than 12 m2K/GW as measured across the semiconductor device structure. The layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm2V?1s?1; and a sheet resistance of no more than 700 ?/square.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 21, 2019
    Assignee: RFHIC CORPORATION
    Inventors: Frank Yantis Lowe, Daniel Francis, Firooz Nasser-Faili, Daneil James Twitchen
  • Patent number: 10297450
    Abstract: Provided is a manufacturing method for manufacturing a SiC substrate having a flattened surface, including etching the surface of the SiC substrate by irradiating the surface of the SiC substrate with atomic hydrogen while the SiC substrate having an off angle is heated. In the etching, the SiC substrate may be heated within a range of 800° C. or higher and 1200° C. or lower.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Fujii, Mariko Sato, Takuro Inamoto
  • Patent number: 10297666
    Abstract: Supposing x is defined as a position of an end of a depletion layer extending when a rated voltage V [V] is applied to a rear surface electrode, W1 is defined as a distance between the position x and an outer peripheral edge of a surface electrode in an outer peripheral direction, W2 is defined as a distance between the position x and an outer peripheral edge of a field insulating film in the outer peripheral direction, t [?m] is defined as a film thickness t [?m] of the field insulating film, a layout of a terminal part is defined so that an electrical field in the field insulating film at the position x expressed as W2V/t(W1+W2) is 3 MV/cm or smaller.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 21, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Ebihara, Hiroshi Watanabe
  • Patent number: 10290727
    Abstract: A performance of a semiconductor device including an RC-IGBT is improved. An AlNiSi layer (a layer containing aluminum (Al), nickel (Ni), and silicon (Si)) is formed between a back surface of a semiconductor substrate and a back surface electrode. Thus, a favorable ohmic junction can be obtained between the back surface electrode and an N+-type layer constituting a cathode region in an embedded diode, and a favorable ohmic junction can be obtained between the back surface electrode and a P-type layer constituting a collector region in an IGBT. The AlNiSi layer contains 10 at % or more of each of the aluminum (Al), the nickel (Ni), and the silicon (Si).
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 14, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Nakanishi, Yuji Fujii
  • Patent number: 10283591
    Abstract: A vertical MOSFET of a trench gate structure includes an n?-type drift layer and a p+-type base layer formed by epitaxial growth. The vertical MOSFET includes a trench that penetrates the n?-type drift layer and the p+-type base layer. A low-concentration thin film is provided in the trench. The low-concentration thin film is in contact with the p+-type base layer and is of the same conductivity type as the p+-type base layer. Further, the low-concentration thin film has an impurity concentration that is lower than that of the p+-type base layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 7, 2019
    Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Naoyuki Ohse, Yusuke Kobayashi, Takahito Kojima, Shinsuke Harada
  • Patent number: 10283725
    Abstract: An organic diode has a substrate, a first conductor layer on the substrate, an organic semiconductor layer on the first conductor layer, and a second conductor layer on the organic substrate layer, wherein one of the conductor layers has an injection enhancement.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 7, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Bing R. Hsieh, Tse Nga Ng, Gregory Whiting
  • Patent number: 10283594
    Abstract: A silicon carbide (SiC) structure and a method of forming the SiC structure are disclosed. The SiC structure includes an SiC substrate and a film provided on the SiC substrate. The SiC substrate contains both of a hexagonal close packed (hcp) structure and a face centered cubic (fcc) structure, and has only one of the hcp surface and the fcc surface, where the hcp surface includes atoms in the topmost layer whose rows overlap with rows of atoms in the third layer, while, the fcc surface includes atoms in the topmost layer whose rows are different from rows of atoms in the third layer.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 7, 2019
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., TOHOKU UNIVERSITY
    Inventors: Hiroyuki Nagasawa, Maki Suemitsu, Hirokazu Fukidome, Yasunori Tateno, Fuminori Mitsuhashi, Masaya Okada, Masaki Ueno
  • Patent number: 10283351
    Abstract: A single-crystal silicon carbide substrate has a main surface having a surface roughness fulfilling Ra?1 nm, and has a ratio of hidden scratches of less than 50%, where, in the case where the main surface is arbitrary observed at 50 or more observation points with a field of view having a diameter of 100 ?m, the ratio of hidden scratches is defined by a value obtained by dividing the number of the observation points at which a striped hidden scratch having a length of at least 50 ?m by the total number of the observation points.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: May 7, 2019
    Assignee: HITACHI METALS, LTD.
    Inventors: Taisuke Hirooka, Hiroyuki Okuda
  • Patent number: 10276380
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a dielectric layer over a substrate, forming a hard mask (HM) layer over the dielectric layer, forming a fin trench through the HM layer and the dielectric layer and extending down to the substrate, forming a semiconductor feature in the fin trench and removing the HM layer to expose an upper portion of the semiconductor feature to form fin features.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Yao Wen, Angus Hsiao
  • Patent number: 10269964
    Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu
  • Patent number: 10269554
    Abstract: In order to reduce edge defects efficiently and sufficiently, a method for manufacturing a SiC epitaxial wafer according to the present invention is a method for manufacturing a SiC epitaxial wafer that forms a SiC epitaxial layer on top of a SiC single crystal substrate having an off angle, and includes a rough polishing step for subjecting an outer circumferential edge on a starting side of step-flow growth in the SiC single crystal substrate to rough polishing before forming the SiC epitaxial layer; and a final polishing step for further polishing for finish.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 23, 2019
    Assignee: SHOWA DENKO K.K.
    Inventors: Yuzo Sasaki, Susumu Sugano