Diamond Or Silicon Carbide Patents (Class 257/77)
  • Patent number: 10784245
    Abstract: An integrated circuit is provided including a first substrate with a first thermal conductivity. An active layer is deposited on the first substrate. At least one native device is fabricated on the active layer. A window is formed in the active layer, which exposes a portion of the first substrate. A non-native device is fabricated on a second substrate with a second thermal conductivity lower than the first thermal conductivity. The non-native device is flip-chip mounted in the widow on the first substrate and electrically connected to the at least one native device. The non-native device is also thermally connected to the first substrate such that heat generated by the non-native device is removed through the first substrate.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 22, 2020
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventor: Gregg H Jessen
  • Patent number: 10774441
    Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single-crystal substrate of one conductivity type, a first silicon carbide layer of the above-mentioned one conductivity type, a second silicon carbide layer of the above-mentioned one conductivity type, and a third silicon carbide layer of the above-mentioned one conductivity type. The silicon carbide single-crystal substrate has first impurity concentration. The first silicon carbide layer is provided on the silicon carbide single-crystal substrate, and has second impurity concentration that is lower than the first impurity concentration. The second silicon carbide layer is provided on the first silicon carbide layer, and has third impurity concentration that is higher than the first impurity concentration. The third silicon carbide layer is provided on the second silicon carbide layer, and has fourth impurity concentration that is lower than the second impurity concentration.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 15, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yu Nakamura, Kazuya Konishi
  • Patent number: 10777654
    Abstract: The present invention relates to a method for manufacturing a nitrogen-face polarity gallium nitride epitaxial structure, which includes: providing a gallium nitride template which includes a substrate and a first nitrogen-face polarity gallium nitride layer positioned on the substrate; re-growing the gallium nitride on a surface of the first nitrogen-face polarity gallium nitride layer to form a second nitrogen-face polarity gallium nitride layer; and sequentially growing a barrier layer and a channel layer on the second nitrogen-face polarity gallium nitride layer. The method for manufacturing the nitrogen-face polarity gallium nitride epitaxial structure provided by the present application enables a simple growth of the nitrogen-face polarity gallium nitride, can effectively eliminate the radio frequency dispersion phenomenon, and is beneficial to large-scale production and utilization of the nitrogen-face polarity gallium nitride epitaxial structure.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 15, 2020
    Assignee: SUZHOU HAN HUA SEMICONDUCTOR CO., LTD.
    Inventors: Xianfeng Ni, Qian Fan, Wei He
  • Patent number: 10770615
    Abstract: An AlGaN template including a substrate and an Al1-xGaxN crystallization thin film deposited on the substrate, where 0<x<1. A method for preparing the AlGaN template includes providing a substrate; and depositing an Al1-xGaxN crystallization thin film on the substrate.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 8, 2020
    Assignee: HC SEMITEK (SUZHOU) CO., LTD.
    Inventors: Binzhong Dong, Wubin Zhang, Haiping Ai, Peng Li, Jiangbo Wang
  • Patent number: 10770552
    Abstract: An epitaxial substrate for semiconductor elements suppresses leakage current and has a high breakdown voltage. The epitaxial substrate for semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer formed of a group 13 nitride adjacent to the free-standing substrate; a channel layer formed of a group 13 nitride adjacent to the buffer layer; and a barrier layer formed of a group 13 nitride on an opposite side of the buffer layer with the channel layer therebetween, wherein part of a first region consisting of the free-standing substrate and the buffer layer is a second region containing Si at a concentration of 1×1017cm?3 or more, and a minimum value of a concentration of Zn in the second region is 1×1017cm?3.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: September 8, 2020
    Assignee: NGK INSULATORS, LTD.
    Inventors: Mikiya Ichimura, Sota Maehara, Yoshitaka Kuraoka
  • Patent number: 10770548
    Abstract: A silicon nitride film having a thickness in a range from 1 [nm] to 3 [nm] is deposited on a front surface of a silicon carbide semiconductor base, by an ALD method. Next, on the silicon nitride film, for example, a silicon oxide film having a thickness in a range from 20 [nm] to 100 [nm] is deposited. After deposition of the silicon oxide film, for example, heat treatment is performed at a temperature in a range from 1100 degrees C. to 1350 degrees C., in a gas atmosphere that includes oxygen. By this heat treatment, nitrogen surface density of an interface of the silicon carbide semiconductor base and the silicon oxide film (gate insulating film) is increased, reducing interface state density of the interface of the silicon carbide semiconductor base and the silicon nitride film.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsuyoshi Araoka, Mitsuo Okamoto, Yohei Iwahashi
  • Patent number: 10770691
    Abstract: A method for producing an organic EL device having an anode, a cathode, at least one organic functional layer disposed between the anode and the cathode, and a sealing layer, comprising a step of forming the anode, a step of forming the cathode, a step of forming the at least one organic functional layer and a step of forming the sealing layer, wherein the average concentration: A (ppm) of ammonia to which the organic EL device during production is exposed from initiation time of the step of forming the at least one organic functional layer until termination time of the step of forming the sealing layer and the exposure time thereof: B (sec) satisfy the formula (1-1): 0?A×B?105??(1-1).
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: September 8, 2020
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masataka Iwasaki, Takaaki Okamoto
  • Patent number: 10761043
    Abstract: Provided are graphene-based nanopore and nanostructure devices, which devices may include an insulating layer disposed atop the graphene, which can be in a planar shape or nanostructured into a ribbon or other shapes, containing a single graphene layer or several layers. Graphene layers and nanostructures can be placed nearby horizontally or stacked vertically. Also provided are related methods of fabricating and processing such devices and also methods of using such devices in macromolecular analysis.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: September 1, 2020
    Assignee: The Trustees of the University of Pennsylvania
    Inventors: Marija Drndic, Ken Healy, Meni Wanunu, Christopher Ali Merchant, Matthew Puster, Kimberly Elizabeth Venta
  • Patent number: 10763354
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer having a first and a second plane, a trench, a gate electrode in the trench, an n-type first silicon carbide region, a p-type second silicon carbide region and a p-type third silicon carbide region provided between the first silicon carbide region and the first plane and interposing the trench therebetween, a p-type sixth silicon carbide region between the first silicon carbide region and the second silicon carbide region, a p-type seventh silicon carbide region between the first silicon carbide region and the third silicon carbide region, an eighth silicon carbide region between the first silicon carbide region and the sixth silicon carbide region, and a ninth silicon carbide region between the first silicon carbide region and the seventh silicon carbide region. The eighth silicon carbide region has a plurality of first regions extending toward the ninth silicon carbide region.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 1, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Kyogoku, Katsuhisa Tanaka, Ryosuke Iijima
  • Patent number: 10763330
    Abstract: A silicon carbide semiconductor element includes a silicon carbide semiconductor layer of a first conductivity type, a body region of a second conductivity type, a channel layer made of a silicon carbide semiconductor disposed on the silicon carbide semiconductor layer so as to be in contact with at least a part of the body region, and a gate electrode disposed on the channel layer via a gate insulating film. The channel layer has a multilayer structure of a high-concentration impurity layer containing impurities of the first conductivity type, a first medium-concentration impurity layer containing impurities of the first conductivity type, and a first low-concentration impurity layer containing impurities of the first conductivity type. The first low-concentration impurity layer is disposed closer to the body region than the high-concentration impurity layer and the first medium-concentration impurity layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 1, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tsutomu Kiyosawa
  • Patent number: 10756188
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, a fifth impurity region, and a sixth impurity region. A first main surface of the silicon carbide substrate is provided with a trench defined by a side surface and a bottom portion. The sixth impurity region includes a first region which faces the bottom portion and a second region which faces a second main surface of the silicon carbide substrate. The first region is higher in impurity concentration than the second region. In a direction perpendicular to the second main surface, a fifth main surface of the fourth impurity region is located between a sixth main surface of the second impurity region and the second main surface.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 25, 2020
    Assignees: Sumitomo Electric Industries, Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Ryouji Kosugi
  • Patent number: 10756169
    Abstract: A second source portion having an impurity concentration lower than that of a first source portion, both forming a source region, includes a first sub-portion having a depth from a bottom surface of the first source portion down to a second height higher than a first height, and a second sub-portion having an upper surface in contact with a part of a bottom surface of the first sub-portion, one side surface in a second direction perpendicular to a first direction in contact with an outer side surface of the trench, another side surface in the second direction, both side surfaces in the first direction, and a bottom surface in contact with the base layer, and having a depth from a bottom surface of the first sub-portion up to at least the first height.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: August 25, 2020
    Assignee: ABLIC INC.
    Inventors: Yuki Osuga, Hirofumi Harada
  • Patent number: 10756189
    Abstract: A substrate is made of gallium-nitride-based material. The n-type layer is disposed on a first surface of the substrate. A p-type layer is disposed on the n-type layer, and constitutes, along with the n-type layer, a semiconductor layer on the first surface of the substrate, the semiconductor layer being provided with a mesa shape having a bottom surface, a side surface, and a top surface. An anode electrode is disposed on the p-type layer. A cathode electrode is disposed on a second surface of the substrate. An insulating film continuously extends over the bottom surface and the top surface to cover the side surface. The top surface is provided with at least one trench. The at least one trench includes a trench filled with the insulating film.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 25, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsuro Hayashida, Takuma Nanjo, Tatsuro Watahiki, Akihiko Furukawa
  • Patent number: 10756200
    Abstract: A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 ?m and smaller than 1.0 ?m.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yasuhiko Oonishi, Kenji Fukuda, Shinsuke Harada, Masanobu Iwaya
  • Patent number: 10748763
    Abstract: An n?-type epitaxial layer is grown on a front surface of the silicon carbide substrate by a CVD method in a mixed gas atmosphere containing a source gas, a carrier gas, a doping gas, an additive gas, and a gas containing vanadium. The doping gas is nitrogen gas; and the gas containing vanadium is vanadium tetrachloride gas. In the mixed gas atmosphere, the vanadium bonds with the nitrogen, producing vanadium nitride, whereby the nitrogen concentration in the mixed gas atmosphere substantially decreases. As a result, the nitrogen taken in by the n?-type epitaxial layer decreases and the n?-type epitaxial layer including nitrogen and vanadium as dopants is grown having a low impurity concentration.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Tetsuya Miyazawa
  • Patent number: 10748999
    Abstract: A switchable array micro-lattice comprises a plurality of interconnected units wherein the units are formed of graphene tubes. JFET gates are provided in selected members of the micro-lattice. Gate connectors are routed from an external surface of an integrated circuit (IC) through openings in the micro-lattice to permit control of the JFET gates.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Luigi Colombo, Nazila Dadvand, Archana Venugopal
  • Patent number: 10749017
    Abstract: Power amplifiers in radio frequency circuits are typically implemented as heterojunction bipolar transistors. In applications such as in 5G systems, the circuits are expected to operate at very high speeds, e.g., up to 100 GHz. Also, a certain amount of output power should be maintained for stable operation. To achieve both high power and high speed, it is proposed to incorporate field plates in the heterojunction bipolar transistors to reduce electric field in the collector. This allows the breakdown voltage of the transistor to be high, which aids in power output. At the same time, the collector can be relatively thin, which aids in operation speed.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 18, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Bin Yang, Xia Li
  • Patent number: 10748957
    Abstract: A method of manufacturing a curved semiconductor die includes: designing a semiconductor die design by conducting finite element analysis of an initial semiconductor die design having a partial spherical curvature, the initial semiconductor die design including a shape of a semiconductor die and a location and shape of a slit in the semiconductor die; when a size of a gap at the slit in the curved semiconductor die is outside a tolerance, modifying the initial semiconductor die design to provide a revised semiconductor die design and conducting another finite element analysis thereof; when the size of the gap at the slit in the curved semiconductor die is within the tolerance, manufacturing a microfabrication mask utilizing the initial semiconductor die design or the revised semiconductor die design having the size of the gap within the tolerance; forming a semiconductor die by utilizing the microfabrication mask; and curving the semiconductor die.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: August 18, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Geoffrey P. McKnight, Andrew C. Keefe, Alexander R. Gurga, Ryan Freeman
  • Patent number: 10738393
    Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single-crystal substrate of one conductivity type, a first silicon carbide layer of the above-mentioned one conductivity type, a second silicon carbide layer of the above-mentioned one conductivity type, and a third silicon carbide layer of the above-mentioned one conductivity type. The silicon carbide single-crystal substrate has first impurity concentration. The first silicon carbide layer is provided on the silicon carbide single-crystal substrate, and has second impurity concentration that is lower than the first impurity concentration. The second silicon carbide layer is provided on the first silicon carbide layer, and has third impurity concentration that is higher than the first impurity concentration. The third silicon carbide layer is provided on the second silicon carbide layer, and has fourth impurity concentration that is lower than the second impurity concentration.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: August 11, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yu Nakamura, Kazuya Konishi
  • Patent number: 10734486
    Abstract: A method of forming a semiconductor device includes providing an engineered substrate, forming a gallium nitride layer coupled to the engineered substrate, forming a channel region coupled to the gallium nitride layer by forming an aluminum gallium nitride barrier layer on the front surface of the gallium nitride layer, forming a gate dielectric layer coupled to the aluminum gallium nitride barrier layer in the central portion of the channel region, forming a gate contact coupled to the gate dielectric layer, forming a source contact at the first end of the channel region, forming a via at the second end of the channel region, filling the via with a conductive material, forming a drain contact coupled to the via, removing the engineered substrate to expose the back surface of the epitaxial gallium nitride layer, and forming a drain pad on the back surface of the epitaxial gallium nitride layer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: August 4, 2020
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Ozgur Aktas
  • Patent number: 10734483
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; a first silicon carbide region; second and third silicon carbide regions between the first silicon carbide region and the first plane; a fourth silicon carbide region between the second silicon carbide region and the first plane; a first and second gate electrodes; a suicide layer on the fourth silicon carbide region; a first electrode on the first plane having a first portion and a second portion, the first portion being in contact with the first silicon carbide region, the second portion being in contact with the suicide layer; a second electrode on the second plane; and an insulating layer between the first portion and the second portion having a first side surface and a second side surface, an angle of the first side surface being smaller than that of the second side surface.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 4, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Makoto Mizukami, Masaru Furukawa, Teruyuki Ohashi
  • Patent number: 10734524
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10734222
    Abstract: A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is formed. Density of a second recessed portion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm?2 in the epi principal surface.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 4, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Taro Nishiguchi, Yu Saitoh, Hirofumi Yamamoto
  • Patent number: 10727188
    Abstract: A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with a first portion of the conductive layer over a remaining portion of the surface of the semiconductor substrate between the openings and a second portion of the conductive layer in the openings. The remaining portion of the surface of the semiconductor substrate is removed to lift-off the first portion of the conductive layer while leaving the second portion of the conductive layer in the openings. The semiconductor substrate is singulated to separate the semiconductor die leaving the second portion of the conductive layer over a surface of the semiconductor die. Alternatively, a plurality of openings is formed over each semiconductor die. A conductive layer is formed over a remaining portion of the surface of the semiconductor substrate between the openings and into the openings.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: July 28, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 10727152
    Abstract: A semiconductor apparatus includes: a radiator plate; a resin insulating layer provided on the radiator plate; a resin block made of resin and armularly disposed to cover an end part of the radiator plate and an end part of the resin insulating layer; a case disposed to cover the resin block; and a sealing material filled in an inside of the case.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroki Tanaka
  • Patent number: 10714611
    Abstract: A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: July 14, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Atsuya Akiba, Sachiko Aoi, Katsumi Suzuki
  • Patent number: 10707075
    Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: July 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Hamano, Akihito Ohno, Takuma Mizobe, Masashi Sakai, Yasuhiro Kimura, Yoichiro Mitani, Takashi Kanazawa
  • Patent number: 10680058
    Abstract: A semiconductor device of the embodiment includes: a first region provided in a silicon carbide layer; and a second region provided around the first region in the silicon carbide layer, the second region having a higher concentration of at least one kind of a lifetime killer impurity selected from the group consisting of B (boron), Ti (titanium), V (vanadium), He (helium) and H+ (proton) than a concentration of a lifetime killer impurity in the first region.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 9, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Mitsuhiro Kushibe, Tatsuo Shimizu
  • Patent number: 10675841
    Abstract: A thin diamond film bonded to a diamond substrate made by the process of heating a diamond substrate inside a vacuum chamber to about 500° C., cooling the diamond substrate, coating a first surface of the diamond substrate with chromium, depositing an initial layer of palladium, heating the diamond substrate, allowing the chromium and the diamond substrate to form a chemical bond, inter-diffusing the adhesion layer of chromium and the initial layer of palladium, cooling, depositing palladium, placing a shadow mask, degassing the vacuum, depositing a tin layer, assembling the tin layer, heating the tin layer, melting the tin layer, and bonding the thin diamond film to the diamond substrate. A thin diamond film bonded to a diamond substrate comprising a thin diamond film, a layer of chromium, palladium, tin, and a diamond substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: June 9, 2020
    Assignee: The Government of the United States of America, as represented by the Secretary by the Navy
    Inventors: Jonathan L. Shaw, Jeremy Hanna
  • Patent number: 10673405
    Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices that include a bottom electrode formed of a two-dimensional electron gas (2DEG). The disclosed FBAR devices may be implemented with various group III-nitride (III-N) materials, and in some cases, the 2DEG may be formed at a heterojunction of two epitaxial layers each formed of III-N materials, such as a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer. The 2DEG bottom electrode may be able to achieve similar or increased carrier transport as compared to an FBAR device having a bottom electrode formed of metal. Additionally, in some embodiments where AlN is used as the piezoelectric material for the FBAR device, the AlN may be epitaxially grown which may provide increased performance as compared to piezoelectric material that is deposited by traditional sputtering techniques.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 2, 2020
    Assignee: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Bruce A. Block, Paul B. Fischer
  • Patent number: 10672878
    Abstract: The silicon carbide semiconductor device includes a plurality of unit cells each having an MISFET structure and provided on a silicon carbide semiconductor substrate. A gate upper electrode disposed adjacent to the plurality of unit cells includes a gate pad and gate global wires. When viewed in plan, gate electrodes do not overlap with the gate pad.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: June 2, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Ohoka, Nobuyuki Horikawa, Masao Uchida
  • Patent number: 10672883
    Abstract: A method for manufacturing a SiC mixed trench Schottky diode may include steps of providing a substrate and an epitaxial layer on top of the substrate; forming a plurality of trenches on a surface of the epitaxial layer; conducting ion implantation at a bottom portion of each trench; conducting ion implantation at sidewalls of each trench; forming an ohmic contact metal at a bottom portion of the Schottky diode; forming a Schottky contact metal on top of the epitaxial layer and in the trenches. In one embodiment, the substrate is an N+ type SiC and the epitaxial layer is an N? type SiC. In another embodiment, the step of forming a plurality of trenches on a surface of the epitaxial layer may include the step of etching the surface of the epitaxial layer by either dry etching or wet etching.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: June 2, 2020
    Assignee: AZ Power, Inc
    Inventors: Na Ren, Zheng Zuo, Ruigang Li
  • Patent number: 10665668
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 26, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Naoyuki Ohse, Shinsuke Harada, Takahito Kojima
  • Patent number: 10658466
    Abstract: A semiconductor element includes: a semiconductor substrate of a first conduction type; a silicon carbide semiconductor layer of the first conduction type disposed above a principal surface of the semiconductor substrate; a terminal edge region of a second conduction type disposed in the silicon carbide semiconductor layer; an insulating film; a first electrode disposed on the silicon carbide semiconductor layer; and a seal ring surrounding the first electrode. The terminal edge region is disposed to surround part of a surface of the silicon carbide semiconductor layer when viewed in a normal direction of the principal surface of the semiconductor substrate. The terminal edge region includes a guard ring region of the second conduction type, and a terminal edge injection region of the second conduction type. The seal ring is formed on the terminal edge injection region through an opening disposed on the insulating film.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 19, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Masao Uchida
  • Patent number: 10651096
    Abstract: A method for manufacturing a semiconductor device according to the present invention includes a manufacturing step of forming a plurality of unit regions each having a plurality of first regions serving as effective cells in which main current flows, and a second region that has an appearance different from that of the first regions and serves as an ineffective cell in which no main current flows, and an appearance inspection step including a step of imaging the unit region to obtain a captured image, a step of cutting out an inspection image from the captured image based on a position of an alignment pattern containing the second region, and a step of comparing the inspection image with a reference image.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: May 12, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noriaki Tsuchiya, Yosuke Setoguchi
  • Patent number: 10651318
    Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a silicon carbide layer disposed between the first electrode and the second electrode; a first n-type silicon carbide region disposed in the silicon carbide layer; and a first nitrogen region disposed in the silicon carbide layer, the first nitrogen region disposed between the first n-type silicon carbide region and the first electrode, and the first nitrogen region having a first nitrogen concentration higher than a first n-type impurity concentration of the first n-type silicon carbide region.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 12, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10643894
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 5, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
  • Patent number: 10644145
    Abstract: A semiconductor device, including a semiconductor substrate, a semiconductor layer disposed on a surface of the semiconductor substrate, a first semiconductor region disposed in the semiconductor layer at a surface thereof, a source region and a second semiconductor region disposed in the first semiconductor region at a surface thereof, a source electrode contacting the source region and the second semiconductor region, a gate insulating film disposed on the surface of the semiconductor layer and covering a portion of the first semiconductor region between the source region and the semiconductor layer, a gate electrode disposed on a surface of the gate insulating film, a drain electrode disposed on another surface of the semiconductor substrate, and a third semiconductor region, which has an impurity concentration higher than that of the first semiconductor region, formed in the semiconductor layer at the surface thereof and being electrically connected to the source electrode.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: May 5, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Hoshi, Yuichi Harada, Akimasa Kinoshita, Yasuhiko Oonishi
  • Patent number: 10626520
    Abstract: A method for producing an epitaxial silicon carbide single crystal wafer comprised of a silicon carbide single crystal substrate having a small off angle on which a high quality silicon carbide single crystal film with little basal plane dislocations is provided, that is, a method for producing an epitaxial silicon carbide single crystal wafer epitaxially growing silicon carbide on a silicon carbide single crystal substrate using a thermal CVD method, comprising supplying an etching gas inside the epitaxial growth reactor to etch the surface of the silicon carbide single crystal substrate so that the arithmetic average roughness Ra value becomes 0.5 nm to 3.0 nm, then starting epitaxial growth to convert 95% or more of the basal plane dislocations at the surface of the silicon carbide single crystal substrate to threading edge dislocations.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 21, 2020
    Assignee: SHOWA DENKO K.K.
    Inventors: Takashi Aigo, Wataru Ito, Tatsuo Fujimoto
  • Patent number: 10615028
    Abstract: By depositing a layer of metal on the semiconductor surface where the metal is deposited in a non-oxidized state first and then depositing a layer of the high-k oxide material over the layer of metal by an atomic layer deposition, a high-k metal oxide is formed at the interface between the semiconductor substrate and the high-k oxide and prevents formation of the undesirable low-k semiconductor oxide layer at the semiconductor/high-k oxide interface.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: April 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Georgios Vellianitis
  • Patent number: 10615031
    Abstract: A silicon carbide semiconductor substrate includes an epitaxial layer. A difference of a donor concentration and an acceptor concentration of the epitaxial layer is within a range from 1×1014/cm3 to 1×1015/cm3. Further, the donor concentration and the acceptor concentration of the epitaxial layer are a concentration unaffected by an impurity inside epitaxial growth equipment.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Fumikazu Imai
  • Patent number: 10615292
    Abstract: A silicon carbide chip array containing a silicon carbide substrate; a silicon carbide layer on top of the silicon carbide substrate; a first metal contact connected to the silicon carbide substrate; and two second metal contacts connected to the first portion and the second portion respectively. The silicon carbide layer is thinner and having lower doping than the silicon carbide layer. The silicon carbide layer includes a first portion and a second portion which are separate from each other. Each one of the second metal contacts forms a semiconductor device with the first metal contact. At least one of the first and second portions contains a side face which is inclined with respect to the silicon carbide substrate. Such a configuration enhances the breakdown voltage and reduces leakage current of the resultant silicon carbide diode array.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventors: Siu Wai Wong, Shu Kin Yau
  • Patent number: 10604844
    Abstract: A method of growing graphene at low temperature on a substrate. The method includes placing a substrate with a layer of cobalt deposited thereon in a plasma enhanced chemical vapor deposition (PECVD) chamber, providing a carbon precursor gas to the PECVD chamber, generating plasma at between about 350° C. and about 800° C. to decompose the carbon precursor gas to thereby deposit carbon atoms on the cobalt layer and enabling a plurality of the carbon atoms to diffuse through the cobalt layer thereby growing graphene on top of the cobalt layer and in between the substrate and the cobalt layer, removing carbon atoms from top of the cobalt layer, and removing the cobalt layer.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: March 31, 2020
    Assignee: Purdue Research Foundation
    Inventors: Zhihong Chen, Shengjiao Zhang
  • Patent number: 10608105
    Abstract: A substrate for a metal oxide semiconductor field effect transistor, and a metal oxide semiconductor field effect transistor, are made available. The substrate encompasses: an n-doped epitaxial drift zone, a p?-doped epitaxial first layer disposed on the drift zone, a heavily n-doped second layer disposed on the first layer, and a terminal formed by p+ implantation, the first layer being in electrical contact with the terminal and being disposed laterally between the terminal and a trench, the trench being formed in the drift zone, in the first layer, and in the second layer. The substrate is characterized in that an implantation depth (P) of the p+ implantation is at least as great as a depth of the trench. The deep p+ implantation can separate adjacent trenches in such a way that a field can no longer attack a gate oxide because it is directed around the gate oxide.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: March 31, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Michael Grieb, Achim Trautmann, Ning Qu
  • Patent number: 10608107
    Abstract: A silicon carbide substrate includes a first impurity region, a second impurity region in contact with the first impurity region and having p type, a third impurity region on the first impurity region and the second impurity region and having n type, a body region, and a source region. A gate insulating film is in contact with the source region, the body region and the third impurity region at a side surface, and in contact with the third impurity region at a bottom surface. When viewed in a direction perpendicular to a main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface. An impurity concentration of the second impurity region exceeds 1×1019 cm?3, and is not more than 1×1021 cm?3.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 31, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsuhiko Sakai, Toru Hiyoshi, So Tanaka
  • Patent number: 10600873
    Abstract: A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: March 24, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Yasuhiro Kawakami
  • Patent number: 10593840
    Abstract: A light emitting element has first and second electrodes. In plan view, the first electrode has a first connecting portion configured to be bonded with a conductive wire, a first extending portion, and two second extending portions. The second electrode has a second connecting portion configured to be bonded with a conductive wire, and two third extending portions. The first extending portion extends linearly toward the second connecting portion, and the two second extending portions are arranged on two sides of the first extending portion. The second extending portions each has two bent portions and a linear portion extending parallel to the first extending portion and disposed between the two bent portions. The third extending portions extend parallel to the first extending portion between the first extending portion and the second extending portions. Each of the second extending portions extends beyond a position of the second connecting portion.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: March 17, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Kosuke Sato, Keiji Emura
  • Patent number: 10593750
    Abstract: A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate including a foundation layer having a first conductivity type; forming a deep trench in the foundation layer; and forming a deep layer having a second conductivity type by introducing material gas of the compound semiconductor while introducing dopant gas into an epitaxial growth equipment to cause epitaxial growth of the deep layer in the deep trench. A period in which a temperature in the epitaxial growth equipment is increased to a temperature of the epitaxial growth of the deep layer is defined as a temperature increasing period. In the forming the deep layer, the deep layer is further formed in a bottom corner portion of the deep trench by starting the introducing of the dopant gas during the temperature increasing period and starting the introducing of the material gas after the temperature increasing period.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 17, 2020
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Atsuya Akiba, Katsumi Suzuki, Yusuke Yamashita
  • Patent number: 10586876
    Abstract: A Schottky device includes a silicon carbide (SiC) substrate of a first conductivity type, a drift layer of the first conductivity type, a trench, a barrier layer of a second conductivity type, an electrically conductive material that at least partially fills the trench and contacts the barrier layer, a first electrode, and a second electrode. The drift layer is formed of SiC and is situated onto the SiC substrate. The trench extends from the top surface of the drift layer towards the SiC substrate. The barrier layer contacts the drifting layer and covers a sidewall and a bottom wall of the trench. The first electrode forms a Schottky junction with the drift layer and forms a low resistivity contact with the barrier layer and the electrically conductive material. The second electrode forms an ohmic contact with the SiC substrate.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: March 10, 2020
    Assignee: Alpha Power Solutions Limited
    Inventors: Wing Chong Tony Chau, Wing Kit Cheung, Wai Tien Chan
  • Patent number: RE48072
    Abstract: The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 30, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano