Diamond Or Silicon Carbide Patents (Class 257/77)
  • Patent number: 11139376
    Abstract: A trench gate MOSFET has at an n-type current spreading region between an n?-type drift region and a p-type base region, a first p+-type region facing a bottom of a trench, and a second p+-type region disposed between adjacent trenches. The first and the second p+-type regions extend parallel to a first direction in which the trench extends and are partially connected by a p+-type connecting portion and thus, disposed in a ladder shape when viewed from the front surface of a semiconductor substrate. The second p+-type region has at a portion of a surface on a drain side, a recessed portion that is recessed toward a source side. One or more recessed portions is provided between connection sites in the second p+-type region for connection with the p+-type connecting portions that are adjacent to each other in the first direction X.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: October 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Keiji Okumura
  • Patent number: 11127612
    Abstract: Several embodiments of the present technology are directed to semiconductor devices, and systems and associated methods for treating semiconductor devices based on warpage data. In some embodiments, a method can include heating a plurality of semiconductor devices from a first temperature to a second temperature, and determining warpage data at a plurality of points on the surfaces of the semiconductor devices as they are being heated. The method can further comprise applying a multivariate analysis to the surface warpage data to generate a multivariate statistic for each of the semiconductor devices at various sample temperatures. The multivariate statistics can be used to determine whether the semiconductor devices exceed or fall below a threshold limit.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James D. Huffaker, Kim M. Hartnett, Ajay Raghunathan, Libo Wang, Linmiao Zhang, Di Wu
  • Patent number: 11127740
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Meng-Hsuan Hsiao, Tsung-Lin Lee, Chih Chieh Yeh, Yee-Chia Yeo
  • Patent number: 11127857
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a treatment process is utilized in order to introduce silicon into a p-metal work function layer. By introducing silicon into the p-metal work function layer, subsequently deposited layers which may comprise diffusable materials such as aluminum can be prevented from diffusing through the p-metal work function layer and affect the operation of the device.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11114295
    Abstract: An epitaxial silicon carbide single crystal wafer having a small depth of shallow pits and having a high quality silicon carbide single crystal thin film and a method for producing the same are provided. The epitaxial silicon carbide single crystal wafer according to the present invention is produced by forming a buffer layer made of a silicon carbide epitaxial film having a thickness of 1 ?m or more and 10 ?m or less by adjusting the ratio of the number of carbon to that of silicon (C/Si ratio) contained in a silicon-based and carbon-based material gas to 0.5 or more and 1.0 or less, and then by forming a drift layer made of a silicon carbide epitaxial film at a growth rate of 15 ?m or more and 100 ?m or less per hour. According to the present invention, the depth of the shallow pits observed on the surface of the drift layer can be set at 30 nm or less.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: September 7, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Takashi Aigo, Wataru Ito, Tatsuo Fujimoto
  • Patent number: 11114560
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer and a first semiconductor region each of a first conductivity type, and a first base region, a second semiconductor layer and a second semiconductor region each of a second conductivity type. The first base region opposes the second semiconductor region in a depth direction. A distribution of point defects in a depth direction from a first surface of the second semiconductor region, opposite a second surface of the second semiconductor region facing toward a front surface of the silicon carbide semiconductor substrate has two peaks at positions deeper than an interface between the first semiconductor layer and the first base region, where a first peak at a deeper position of the two peaks has a greater quantity of the point defects than does a second peak at a shallower position of the two peaks.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 7, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 11107893
    Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 500/cm2. An acceptor layer is attached at the graphene layer to form a wafer-stack. The acceptor layer includes silicon carbide having a second defect density higher than first defect density. The wafer-stack is split along a split plane in the silicon carbide substrate to form a device wafer including the graphene layer and a silicon carbide split layer at the graphene layer. An epitaxial silicon carbide layer extending to an upper side of the device wafer is formed on the silicon carbide split layer. The device wafer is further processed at the upper side.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 31, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp
  • Patent number: 11109370
    Abstract: The present application discloses a method for a terminal to transmit an uplink data signal configured with a plurality of code blocks in a wireless communication system. Particularly, the method comprises: a step of mapping, within one slot, a plurality of code blocks to resource elements by using a time-first method, for each time block; and a step of transmitting, to a base station, an uplink demodulation reference signal and an uplink data signal which is configured with a plurality of code blocks, wherein the size of the time block to which the time-first method is applied is determined based on a mapping pattern of the uplink demodulation reference signal.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 31, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Hyungtae Kim, Jiwon Kang, Kijun Kim, Sukhyon Yoon, Sangrim Lee
  • Patent number: 11107677
    Abstract: A SiC varied-growth-rate layer (2) is formed on a SiC bulk substrate (1) while increasing a growth speed from an initial growth speed of 2.0 ?m/h or less. A speed change rate of the SiC varied-growth-rate layer (2) is 720 ?m/h2 or less. A molar flow ratio of nitrogen to carbon when growth of the SiC varied-growth-rate layer (2) starts is 2.4 or less.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 31, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Susumu Hatakenaka
  • Patent number: 11094615
    Abstract: A semiconductor device, a drain electrode terminal supporting the semiconductor device and connected directly to a drain electrode pad, a source electrode terminal connected to a source electrode pad, and a gate electrode terminal are provided, wherein the source electrode terminal includes a wire post, a first lead extending from one end of the wire post, and a second lead extending from another end of the wire post, wherein the source electrode pad and the wire post of the source electrode terminal are connected to each other through a plurality of bonding wires, and wherein the semiconductor device, a surface, supporting the semiconductor device thereon, of the drain electrode terminal, the wire post of the source electrode terminal, the bonding wires, and part of the gate electrode terminal are covered with a mold resin.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: August 17, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hisato Michikoshi
  • Patent number: 11094790
    Abstract: A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 17, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasunori Oritsuki, Yoichiro Tarui
  • Patent number: 11094835
    Abstract: It is an object of the present invention to provide a silicon carbide substrate having a low defect density that does not contaminate a process device and a silicon carbide semiconductor device including the silicon carbide substrate. A silicon carbide substrate according to the present invention is a silicon carbide substrate including: a substrate inner portion; and a substrate outer portion surrounding the substrate inner portion, wherein non-dopant metal impurity concentration of the substrate inner portion is 1×1016 cm?3 or more, and a region of the substrate outer portion at least on a surface side thereof is a substrate surface region in which the non-dopant metal impurity concentration is less than 1×1016 cm?3.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 17, 2021
    Assignees: MITSUBISHI ELECTRIC CORPORATION, NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY
    Inventors: Tomoaki Furusho, Takanori Tanaka, Takeharu Kuroiwa, Toru Ujihara, Shunta Harada, Kenta Murayama
  • Patent number: 11087986
    Abstract: To enhance efficiency of a process of implanting impurities into a silicon carbide semiconductor layer. To provide a method of manufacturing a semiconductor device including a silicon carbide semiconductor layer, the method of manufacturing including: implanting impurities multiple times to an impurity implantation region in the silicon carbide semiconductor layer to different depths, with temperature of the silicon carbide semiconductor layer being set to be equal to or lower than 150° C. In the implanting, impurities may be implanted multiple times to the impurity implantation region to different depths, with temperature of the silicon carbide semiconductor layer being set to be equal to or higher than room temperature.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 10, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsushi Nishiyama, Masayuki Miyazaki, Shoji Kitamura
  • Patent number: 11088276
    Abstract: A plurality of trench gate electrodes are formed from an upper surface to reach an intermediate depth of an n-type SiC epitaxial substrate including an n-type drain region on a lower surface and an n-type source region on an upper surface in contact with the source region to be arranged in a direction along the upper surface. Here, at least three side surfaces among four side surfaces of each of the trench gate electrodes having a rectangular planar shape are in contact with a p-type body layer below the source region. In addition, a JFET region in the SiC epitaxial substrate and a source electrode connected to the source region immediately above the JFET region extend along a direction in which the plurality of trench gate electrodes are arranged.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: August 10, 2021
    Assignee: HITACHI, LTD.
    Inventors: Takeru Suto, Naoki Tega, Naoki Watanabe
  • Patent number: 11088073
    Abstract: In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 10, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Toshikazu Tanioka, Yasunori Oritsuki, Kenichi Hamano, Naochika Hanano
  • Patent number: 11081457
    Abstract: In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Danny Clavette, Paul Ganitzer, Martin Poelzl, Carsten von Koblinski
  • Patent number: 11081564
    Abstract: A semiconductor device includes a first electrode, a silicon carbide substrate having a first surface electrically connected with the first electrode and a second surface opposite to the first surface, an ohmic junction layer disposed on the second surface, and a second electrode disposed on the ohmic junction layer. The ohmic junction layer has a first layer that is directly disposed on the second surface and includes a first silicide of titanium and a first silicide of a metal element other than titanium, and a second layer that is directly disposed on the first layer, includes a second silicide of titanium and a second silicide of the metal element, and has a lower titanium concentration than the first layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 3, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoyuki Ohse
  • Patent number: 11081549
    Abstract: A method for fabricating a semiconductor device includes providing a semiconductor structure including a semiconductor substrate, a plurality of semiconductor fin structures, and a trench insulation layer formed on the semiconductor substrate and surrounding each semiconductor fin structure. The semiconductor fin structures include a plurality of first semiconductor fin structures and a plurality of second semiconductor fin structures. The top surface of the trench insulation layer is leveled with the top surface of the semiconductor fin structures.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 3, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11075277
    Abstract: An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N? drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: July 27, 2021
    Assignee: GeneSIC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11069803
    Abstract: A semiconductor device according to an embodiment includes: a SiC layer having a first plane, a second plane, a first trench located on a first plane side, an n-type first SiC region, a p-type second SiC region between the first SiC region and the first plane, an n-type third SiC region between the second SiC region and the first plane, and a p-type fourth SiC region between the first SiC region and the first plane, at least a portion of the fourth SiC region located in the second SiC region, the fourth SiC region having a higher p-type impurity concentration than the second SiC region; a gate electrode in the first trench; a first electrode located on the first plane side; and a second electrode located on a second plane side. A depth of the fourth SiC region increases with distance from the first trench.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: July 20, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuhisa Tanaka, Shinya Kyogoku, Ryosuke Iijima, Shinichi Kimoto
  • Patent number: 11069778
    Abstract: A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Ronny Kern
  • Patent number: 11069602
    Abstract: The present invention is a semiconductor module including: first and second drive circuits that perform drive control of at least one pair of first and second switching devices, in which the at least one pair of first and second switching devices and the first and second drive circuits are sealed in a package having a rectangular shape in plan view, and there are provided: a control terminal provided to protrude from a side surface of a first long side out of first and second long sides of the package, and to which a control signal of the first and second drive circuits is inputted; an output terminal provided to protrude from a side surface of the second long side; a first main terminal provided to protrude from a side surface of a first short side out of first and second short sides of the package; and a second main terminal provided to protrude from a side surface of the second short side.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: July 20, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shuhei Yokoyama, Shogo Shibata, Maki Hasegawa, Koichiro Noguchi, Shigeru Mori, Toru Iwagami
  • Patent number: 11069779
    Abstract: A silicon carbide semiconductor device includes a first semiconductor layer of silicon carbide, a device structure provided on top of the first semiconductor layer, a second semiconductor layer of silicon carbide having a higher impurity concentration than the first semiconductor layer, provided under the first semiconductor layer, the second semiconductor layer implementing an ohmic-contact, and a metallic electrode film provided under the second semiconductor layer. A thickness of a carbon-containing region in which carbon-atoms are precipitated between the second semiconductor layer and the metallic electrode film is 10 nm or less.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: July 20, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa, Yusuke Wada
  • Patent number: 11063161
    Abstract: A method of forming a photovoltaic device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 11063122
    Abstract: In a termination region of a SiC-MOSFET, suppressing operation of a p-n diode between a well and a drift layer sometimes decreases reliability during high-speed switching. In a termination region of a SiC-MOSFET with a built-in SBD are provided second well region having an impurity concentration lower than the impurity concentration in a well region in an active region, and a high-concentration region that is formed on a surface layer of the second well region, has an impurity concentration higher than the impurity concentration in the well region in the active region, and is ohmic-connected to a source electrode.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yusuke Yamashiro, Kazuyuki Sugahara, Hiroshi Watanabe, Kohei Ebihara
  • Patent number: 11063149
    Abstract: A semiconductor device includes a first layer of a first semiconductor material disposed on a semiconductor substrate and a second layer of a second semiconductor material disposed on the first layer. The second semiconductor material is formed of an alloy that includes a first element and a second element. The first semiconductor material and the second semiconductor material are different. A gate structure is disposed on a first portion of the second layer. A surface region of a second portion of the second layer not covered by the gate structure has a higher concentration of the second element than an internal region of the second portion of the second layer, and the surface region surrounds the internal region.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: July 13, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang Lu, I-Hsieh Wong, Shih-Ya Lin, Cheewee Liu, Samuel C. Pan
  • Patent number: 11053607
    Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×1014 cm?3 and less than or equal to 5×1016 cm?3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: July 6, 2021
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Tsutomu Hori, Taro Nishiguchi
  • Patent number: 11056562
    Abstract: A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 6, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasunori Oritsuki, Yoichiro Tarui
  • Patent number: 11056557
    Abstract: A semiconductor device includes a semiconductor layer on a first electrode. The semiconductor layer includes a first region of a first type, a second region of a second type, a third region of the second type, and a fourth region of the first type. The second region is above the first region. The third region surrounds the second region. The fourth region surrounds the third region. The second electrode includes a first portion above the second region and a second portion surrounding the first portion. The third electrode surrounds the second electrode and is electrically connected to the fourth region. The semi-insulating layer is electrically connected to the second electrode and the third electrode. A first end portion of the first insulating layer is above the third region.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: July 6, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kazuki Minamikawa, Yukie Nishikawa, Kotaro Zaima
  • Patent number: 11049942
    Abstract: A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 29, 2021
    Inventors: Te-Chang Tseng, Riichiro Shirota
  • Patent number: 11049931
    Abstract: A gate connection layer (14) includes a portion placed on an outer trench (TO) with a gate insulating film (7) being interposed. A first main electrode (10) includes a main contact (CS) electrically connected to a well region (4) and a first impurity region (5) within an active region (30), and an outer contact (CO) being spaced away from the active region (30) and in contact with a bottom face of the outer trench (TO). A trench-bottom field relaxing region (13) is provided in a drift layer (3). A trench-bottom high-concentration region (18) has an impurity concentration higher than that of the trench-bottom field relaxing region (13), is provided on the trench-bottom field relaxing region (13), and extends from a position where it faces the gate connection layer (14) with the gate insulating film (7) being interposed, to a position where it is in contact with the outer contact (CO) of the first main electrode (10).
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 29, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yutaka Fukui, Katsutoshi Sugawara, Shiro Hino, Kazuya Konishi, Kohei Adachi
  • Patent number: 11049962
    Abstract: An embodiment relates to a device comprising a unit cell on a SiC substrate, the unit cell comprising a gate insulator film, a trench in the well region, and a first sinker region of a second conduction type, wherein the first sinker region has a depth that is equal to or greater than a depth of a well region; wherein the device has an on-resistance of less than 3 milliohm-cm2, a gate threshold voltage of greater than 2.8V, a breakdown voltage of greater than 1450V, and an electric field of less than 3.5 megavolt/cm in the gate insulator film at a drain voltage of less than or equal to 1200 V.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: June 29, 2021
    Assignee: GeneSiC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Patent number: 11037826
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature directly over the first fin, and a second lower semiconductor feature directly over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate. The semiconductor also further includes an upper semiconductor feature directly over and in physical contact with the first and second lower semiconductor features. The semiconductor device further includes a dielectric layer on sidewalls of the first and second lower semiconductor features.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • Patent number: 11037832
    Abstract: Semiconductor devices and methods of forming the same include partially etching sacrificial layers in a first stack of alternating sacrificial layers and channel layers to form first recesses. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers are etched away. The first inner spacer sub-layer is etched away. A gate stack is formed on and around the channel layers and in contact with the second inner spacer sub-layer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Patent number: 11031503
    Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 11024731
    Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: June 1, 2021
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
  • Patent number: 11018248
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: May 25, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Patent number: 11018228
    Abstract: A silicon carbide semiconductor device includes a first doped region including a plurality of first leg portions, a plurality of body portions, and a plurality of first arm portions. The first leg portions are extending along a second direction, the body portions connect at least two of the first leg portions, and the first arm portions are extending along a first direction and connecting at least two of the first leg portions. A second doped region includes a plurality of second leg portions, a plurality of source portions, and a plurality of second arm portions. The second leg portions are extending along the second direction, the source portions are arranged in the body portions and connecting at least two of the second leg portions, and the second arm portions are extending along the first direction and connecting at least two of the second leg portions.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: May 25, 2021
    Assignee: FAST SIC SEMICONDUCTOR INCORPORATED
    Inventor: Cheng-Tyng Yen
  • Patent number: 11011640
    Abstract: A fin field effect transistor is provided. The FinFET device includes a base substrate; an isolation layer on the base substrate; first fins in the isolation layer and on the base substrate. The first fins is made of a material having a thermal conductivity greater than a material of the base substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11011370
    Abstract: A method for manufacturing a semiconductor device includes: forming an ohmic electrode including Al on a semiconductor substrate; forming a SiN film covering the ohmic electrode; forming a first photoresist on the SiN film, the first photoresist having an opening pattern overlapping the ohmic electrode; performing ultraviolet curing of the first photoresist; forming an opening in the SiN film exposed through the opening pattern and causing a surface of the ohmic electrode to be exposed inside the opening; forming a barrier metal layer on the first photoresist and on the ohmic electrode exposed through the opening; forming a second photoresist in the opening pattern; performing a heat treatment on the second photoresist and covering the barrier metal layer overlapping the opening with the second photoresist; and etching the barrier metal layer using the second photoresist.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: May 18, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kenichi Watanabe
  • Patent number: 11011440
    Abstract: A semiconductor element bonding body including: a substrate, in which a concave portion is formed; and a semiconductor element placed in the concave portion to be mounted to the substrate. A portion of the substrate in which the concave portion is formed is made of Cu. The concave portion has a perimeter portion in which a level difference is formed, and the level difference has a height d of 20 ?m or more and less than 50 ?m. The concave portion has a bottom surface having a flatness degree of ?/8.7 ?m or more and ?/1.2 ?m or less when a wavelength ? of a laser is 632.8 nm. A metal film is formed on the semiconductor element, and the bottom surface of the concave portion and the metal film are bonded directly to each other.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: May 18, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji Yamazaki, Tomoaki Kato
  • Patent number: 11004788
    Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan Jun, Seul-Ki Hong, Hyun-Soo Kim, Sang-Hyun Lee
  • Patent number: 11004941
    Abstract: A silicon carbide epitaxial substrate has a silicon carbide single-crystal substrate and a silicon carbide layer. An average value of carrier concentration in the silicon carbide layer is not less than 1×1015 cm?3 and not more than 5×1016 cm?3. In-plane uniformity of the carrier concentration is not more than 2%. The second main surface has: a groove 80 extending in one direction along the second main surface, a width of the groove in the one direction being twice or more as large as a width thereof in a direction perpendicular to the one direction, and a maximum depth of the groove from the second main surface being not more than 10 nm; and a carrot defect. A value obtained by dividing a number of the carrot defects by a number of the grooves is not more than 1/500.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: May 11, 2021
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Hironori Itoh, Taro Nishiguchi
  • Patent number: 11004939
    Abstract: A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 11, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Yasuhiro Kawakami
  • Patent number: 11001753
    Abstract: A phosphor comprises a crystal phase that has a chemical composition of (Y1-x-y,Cex,Lay)?Si?-zAlzN?O, where the ? satisfies 5.5???6.5, the ? satisfies 9.5???12.5, the ? satisfies 17.5???22.5, the x satisfies 0<x?0.1, the y satisfies 0?y?0.4, and the z satisfies 0?z?0.5. A light emission spectrum of the phosphor includes a peak within a wavelength range of not less than 600 nm and not more than 660 nm.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 11, 2021
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Mitsuru Nitta, Nobuaki Nagao
  • Patent number: 10998406
    Abstract: A silicon carbide single crystal substrate includes a first main surface and an orientation flat. The orientation flat extends in a <11-20> direction. The first main surface includes an end region extending by at most 5 mm from an outer periphery of the first main surface. In a direction perpendicular to the first main surface, an amount of warpage of the end region continuous to the orientation flat is not greater than 3 ?m.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 4, 2021
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Tsutomu Hori
  • Patent number: 10991822
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 27, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuichi Nagahisa, Shiro Hino, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
  • Patent number: 10985240
    Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Patent number: 10978359
    Abstract: Provided is an SiC substrate evaluation that includes irradiating a first surface of an SiC substrate which is cut out from an SiC ingot with excitation light before an epitaxial film is laminated on the first surface to perform photoluminescence measurement.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 13, 2021
    Assignee: SHOWA DENKO K.K.
    Inventor: Shunsuke Noguchi
  • Patent number: 10978575
    Abstract: A semiconductor structure is provided and includes a substrate; a gate dielectric layer on the substrate; a dielectric barrier layer structure on the gate dielectric layer; a work function layer on the dielectric barrier layer structure; a gate barrier layer structure on the work function layer; and a gate electrode layer on the gate barrier layer structure. The dielectric barrier layer structure is doped with silicon and the gate barrier layer structure is doped with silicon.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: April 13, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hao Deng