Abstract: A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

Abstract: A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.

Abstract: Semiconductor devices, and more particularly semiconductor devices with improved edge termination structures are disclosed. A semiconductor device includes a drift region that forms part of an active region. An edge termination region is arranged along a perimeter of the active region and also includes a portion of the drift region. The edge termination region includes one or more sub-regions of an opposite doping type than the drift region and one or more electrodes may be capacitively coupled to the drift region by way of the one or more sub-regions. During a forward blocking mode for the semiconductor device, the one or more electrodes may provide a path that draws ions away from passivation layers that are on the edge termination region and away from the active region. In this manner, the semiconductor device may exhibit reduced leakage, particularly at higher operating voltages and higher associated operating temperatures.

Abstract: There is provided a group III nitride laminate, including: a substrate comprised of silicon carbide; a first layer comprised of aluminum nitride and formed on the substrate; a second layer comprised of gallium nitride and formed on the first layer; and a third layer formed on the second layer and comprised of group III nitride having an electron affinity lower than that of the gallium nitride which is comprised in the second layer, the second layer having a thickness of less than 500 nm, the second layer containing iron at a concentration of less than 1×1017/cm3, and the second layer containing carbon at a concentration of less than 1×1017/cm3.

Abstract: A method and apparatus include an n-doped layer having a first applied charge, and a p?-doped layer having a second applied charge. The p?-doped layer may be positioned below the n-doped layer. A p+-doped buffer layer may have a third applied charge and be positioned below the p?-doped layer. The respective charges at each layer may be determined based on a dopant level and a physical dimension of the layer. In one example, the n-doped layer, the p?-doped layer, and the p+-doped buffer layer comprise a lateral semiconductor manufactured from silicon carbide (SiC).

Abstract: A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.

Abstract: A ceramic circuit substrate having high bonding performance and excellent thermal cycling resistance properties, wherein a ceramic substrate and a copper plate are bonded by a braze material containing Ag and Cu, at least one active metal component selected from Ti and Zr, and at least one element selected from among In, Zn, Cd, and Sn, wherein a braze material layer, after bonding, has a continuity ratio of 80% or higher and a Vickers hardness of 60 to 85 Hv.

Abstract: An object of the present invention is to provide a Schottky barrier diode less liable to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode according to this disclosure includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, and a cathode electrode brought into ohmic contact with the semiconductor substrate. The drift layer has an outer peripheral trench surrounding the anode electrode in a plan view. The surface of the drift layer positioned between the anode electrode and the outer peripheral trench is covered with a semiconductor layer having a conductivity type opposite to that of the drift layer.

Abstract: A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the lead frame, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.

Abstract: Embodiments disclosed herein include electronic packages with improved thermal performance. In an embodiment, the electronic package comprises a first package substrate, a first die stack over the first package substrate, and a heat spreader over the first die stack. In an embodiment, the heat spreader comprises arms that extend out past sidewalls of the first package substrate. In an embodiment, the electronic package further comprises an interposer over and around the heat spreader, where the interposer is electrically coupled to the first package substrate by a plurality of interconnects. In an embodiment, the electronic package further comprises a second package substrate over the interposer, and a second die over the second package substrate.

Abstract: A photovoltaic unit that includes a biological interface for sensing an electrical signal from the biological tissue, the biological interface including a multilayered piezoelectric amplifier including a composite impulse generating layer including a matrix of a piezo polymeric material and dispersed phases including piezo nanocrystals and carbon nanotubes. The photovoltaic unit also includes a transducer structure comprising a fiber substrate having quantum dots present on a receiving end of the fiber. The receiving end of the fiber receiving the electrical signal. The quantum dots converts the electrical signal to a light signal.

Abstract: A semiconductor apparatus includes: a semiconductor substrate; a diffusion layer; a first depletion prevention region; a channel stopper electrode, a monitor electrode and an insulating film. The inner edge portion of the monitor electrode is positioned between the diffusion layer and the first depletion prevention region. A distance between the outer edge portion of the channel stopper electrode and the inner edge portion of the monitor electrode is a first distance. A distance between the diffusion layer and the first depletion prevention region is a second distance. The first and second distances are set so that a discharge voltage between the channel stopper electrode and the monitor electrode becomes greater than an avalanche breakdown voltage at a PN junction portion of the diffusion layer and the semiconductor substrate.

Abstract: A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.

Abstract: An electronic circuit, including a first switching device that contains a first semiconductor material with a first band gap, and a second switching device that is coupled in parallel to the first switching device, and contains a second semiconductor material with a second band gap smaller than the first band gap. Each of the first and second switching devices has a control electrode, and the control electrode of the first switching device is coupled to the control electrode of the second switching device.

Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film.

Abstract: A semiconductor substrate has a first surface and a second surface that includes an inner region and an outer region. The semiconductor substrate includes a drift layer of a first conductivity type and a terminal well region of a second conductivity type. The terminal well region includes a portion that extends from between the inner region and the outer region toward the outer region. A first electrode is on the first surface. A second electrode is on at least part of the inner region and electrically connected to the terminal well region, and has its edge located on a boundary between the inner region and the outer region. A peripheral structure is provided on part of the outer region, away from the second electrode. A surface protective film covers the edge of the second electrode and at least part of the outer region and has the peripheral structure engaged therein.

Abstract: A manufacturing method of a silicon carbide semiconductor device may include: forming a gate insulating film on a silicon carbide substrate; and forming a gate electrode on the gate insulating film. The forming of the gate insulating film may include forming an oxide film on the silicon carbide substrate by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere.

Abstract: A semiconductor device according to an embodiment includes first and second electrode, and semiconductor layer between the first and the second electrode. The semiconductor layer has first and second plane. The semiconductor layer includes first region of first conductivity type, second region of second conductivity type between the first plane and the first region, third region of second conductivity type between the first plane and the first region and, fourth region of second conductivity type between the second and the third region, and fifth region of first conductivity type having first portion provided between the first and the fourth region. Width of the fourth region is larger than that of the second region. Distance between the second region and the first portion is smaller than distance between the second and the fourth region. And width of the first portion is smaller than that of the fourth region.

Abstract: Described is a power semiconductor module that includes: a frame made of an electrically insulative material; a first substrate seated in the frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a busbar extending from the first substrate through a side face of the frame; a current sensor module seated in a receptacle of the frame in sensing proximity of the busbar, the current sensor module including a current sensor attached to a circuit board; and a potting material fixing the current sensor module to the frame such that no air gap is present between the current sensor and the busbar. The potting material contacts the frame and the current sensor. Methods of producing the power semiconductor module are also described.

Abstract: A semiconductor device of an embodiment includes: a first trench in a silicon carbide layer and extending in a first direction; a second trench and a third trench located in a second direction orthogonal to the first direction with respect to the first trench and adjacent to each other in the first direction, n type first silicon carbide region, p type second silicon carbide region on the first silicon carbide region, n type third silicon carbide region on the second silicon carbide region, p type fourth silicon carbide region between the first silicon carbide region and the second trench, and p type fifth silicon carbide region located between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode; and a second electrode. A part of the first silicon carbide region is located between the second trench and the third trench.

Abstract: To improve an on-resistance of a semiconductor device. A plurality of collector regions are formed at a predetermined interval on a bottom surface of a drift layer made of SiC. Next, on the bottom surface of the drift layer, both of the drift layer and a collector region via a silicide layer are connected to a collector electrode.

Abstract: A semiconductor device includes an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side, a semiconductor element which is formed in the first main surface, a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed in a first direction which is one of the plane directions of the second main surface, and an electrode which is formed on the second main surface and connected to the raised portion group.

Abstract: A plurality of waveguide display substrates, each waveguide display substrate having a cylindrical portion having a diameter and a planar surface, a curved portion opposite the planar surface defining a nonlinear change in thickness across the substrate and having a maximum height D with respect to the cylindrical portion, and a wedge portion between the cylindrical portion and the curved portion defining a linear change in thickness across the substrate and having a maximum height W with respect to the cylindrical portion. A target maximum height Dt of the curved portion is 10?7 to 10?6 times the diameter, D is between about 70% and about 130% of Dt, and W is less than about 30% of Dt.

Abstract: A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

Abstract: A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (?m). A width of the unit cell is one of less than and equal to 5.0 micrometers (?m). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.

Abstract: A semiconductor device includes a diamond substrate made of diamond, and a nitride semiconductor layer formed in a recess formed at an upper surface of the diamond substrate. The semiconductor device further includes at least one of: (A) the nitride semiconductor layer formed to be surrounded entirely by the upper surface of the diamond substrate in a plan view; (B) the diamond substrate in which the upper surface of the diamond substrate and an upper surface of the nitride semiconductor layer are located on the same plane; and (C) the diamond substrate having electrical insulating properties.

Abstract: A power SiC MOSFET with a built-in Schottky rectifier provides advantages of including a Schottky rectifier, such as avoiding bipolar degradation, while reducing a parasitic capacitive charge and related power losses, as well as system cost. A lateral built-in channel layer may enable lateral spacing of the MOSFET gate oxide from a high electric field at the Schottky contact, while also providing current limiting during short-circuit events.

Abstract: A method of producing a wafer from a hexagonal single-crystal ingot includes the steps of planarizing an end face of the hexagonal single-crystal ingot, forming a peel-off layer in the hexagonal single-crystal ingot by applying a pulsed laser beam whose wavelength is transmittable through the hexagonal single-crystal ingot while positioning a focal point of the pulsed laser beam in the hexagonal single-crystal ingot at a depth corresponding to a thickness of a wafer to be produced from the planarized end face of the hexagonal single-crystal ingot, recording a fabrication history on the planarized end face of the hexagonal single-crystal ingot by applying a pulsed laser beam to the hexagonal single-crystal ingot while positioning a focal point of the last-mentioned pulsed laser beam in a device-free area of the wafer to be produced.

Abstract: A semiconductor device includes a semiconductor device provided on a semiconductor substrate and an ohmic electrode provided on a back surface of the semiconductor device and containing a nickel silicide and a molybdenum carbide, or the nickel silicide and a titanium carbide. The ohmic electrode is configured by first regions where a silicide is thick and second regions where the silicide is thin; a ratio of an arithmetic area of the second regions to an arithmetic area of the ohmic electrode is in a range from 10% to 30% in a plan view.

Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer stacked on the first semiconductor layer, includes a Ga2O3-based single crystal, and includes a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench electrode that is buried in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes an insulating dry-etching-damaged layer with a thickness of not more than 0.8 ?m in a region including the inner surface of the trench.

Abstract: The present invention provides a trench gate structure and a method of forming the same. The method comprises steps of forming a first trench on the surface of a substrate, a surface of a bottom of the first trench comprising a crystal face belonging to the first family of crystal faces, and a surface of a sidewall of the first trench comprising another crystal face belonging to a second family of crystal faces. With a face-selective wet etching, a specific crystal face is presented on the surface of the bottom of the trench and a thicker gate oxide layer is formed thereon after performing thermal oxidation to avoid from failure due to thinner gate oxide layer on the surface of the bottom, increase breakdown voltage, and improve reliability of the device.

Abstract: A nitride semiconductor multilayer structure includes a first nitride semiconductor layer; a second nitride semiconductor layer; and a third nitride semiconductor layer formed between the first nitride semiconductor layer and the second nitride semiconductor layer. The third nitride semiconductor layer includes a first region and a second region that surrounds the first region in a same plane, and an indium content of the second region is lower than an indium content of the first region.

Abstract: There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions (7) comprising an access region (7a) and a JFET region (7b) defining the length of the MOS channel (17), and wherein the access region (7a) and the JFET region (7b) are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel (17) is defined by simultaneous creating n-type regions on both sides of the channel (17) using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.

Abstract: The disclosure relates to a semiconductor component having an SiC semiconductor body and a first load terminal on a first surface of the SiC semiconductor body. A second load terminal is formed on a second surface of the SiC semiconductor body opposite the first surface. The semiconductor component has a drift zone of a first conductivity type in the SiC semiconductor body and a first semiconductor area of a second conductivity type which is electrically connected to the first load terminal. A pn junction between the drift zone and the first semiconductor area defines a voltage blocking strength of the semiconductor component.

Abstract: A semiconductor device according to the present disclosure includes a substrate including a plurality of atomic steps that propagate along a first direction, and a transistor disposed on the substrate. The transistor includes a channel member extending a second direction perpendicular to the first direction, and a gate structure wrapping around the channel member.

Abstract: The present application discloses a semiconductor device with graphene layers and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first passivation layer positioned above the substrate, a redistribution layer positioned on the first passivation layer, a first adjustment layer positioned on the redistribution layer, a pad layer positioned on the first adjustment layer, and a second adjustment layer positioned between the pad layer and the first adjustment layer. The first adjustment layer and the second adjustment layer are formed of graphene.

Abstract: Before formation of gate insulating films, an oblique ion implantation of oxygen into opposing sidewalls of trenches, from a top of an oxide film mask is performed, forming oxygen ion-implanted layers in surface regions of the sidewalls. A peak position of oxygen concentration distribution of the oxygen ion-implanted layers is inside the oxide film mask. After removal of the oxide film mask, HTO films constituting the gate insulating films are formed. During deposition of the HTO films, excess carbon occurring at the start of the deposition of the HTO films and in the gate insulating films reacts with oxygen in the oxygen ion-implanted layers, thereby becoming an oxocarbon and being desorbed. The oxygen ion-implanted layers have a thickness in a direction orthogonal to the sidewalls at most half of the thickness of the gate insulating films, and an oxygen concentration higher than any other portion of the semiconductor substrate.

Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.

Abstract: The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an N+ high-concentration substrate layer, an N? low-concentration Ga2O3 epitaxial layer and an anode metal layer from bottom to top, wherein the N? low-concentration Ga2O3 epitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a semiconductor layer, a first conductive part, a second conductive part, and a second electrode. The semiconductor layer includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The first conductive part includes a buried electrode provided in the first semiconductor region with a first insulator interposed. The second conductive part includes a gate electrode provided on the buried electrode with a second insulator interposed. The first conductive part is electrically connected to the second conductive part. An electrical resistance of the first conductive part is greater than an electrical resistance of the second conductive part.

Abstract: An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.

Abstract: A semiconductor device includes an active region, a gate ring region surrounding a periphery of the active region, and a source ring region surrounding a periphery of the gate ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and a second electrode. The semiconductor device has, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film and a first first-electrode, and has, in the source ring region, a third semiconductor region and a second first-electrode. In the source ring region, a second semiconductor region of the first or second conductivity type is provided at a bottom of the third semiconductor region, directly below the second first-electrode in a depth direction of the semiconductor device.

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

Abstract: A semiconductor module may include: a first semiconductor chip including a first semiconductor substrate including a field effect transistor and constituted of SiC, a drain electrode and a source electrode provided on the first semiconductor substrate; a second semiconductor chip including a second semiconductor substrate including a diode, a cathode electrode and an anode electrode provided on the second semiconductor substrate; a first lead frame including a first main terminal and connected to the drain electrode and the cathode electrode; and a second lead frame including a second main terminal and connected to the source electrode and the anode electrode. A first current path extending from the second to first main terminal via the first semiconductor chip may be longer than a second current path extending from the second to first main terminal via the second semiconductor chip.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

Abstract: A semiconductor device has: a semiconductor substrate; a drift layer of a first conductivity type; a well region of a second conductivity type; a high-concentration region of the second conductivity type, a source region of the first conductivity type; an insulating film provided on the drift layer; a first contact metal film in contact with the source region and the high-concentration region through a first opening provided in the insulating film; and a second contact metal film formed on a surface of the first contact metal film and contacting the high-concentration region through a second opening provided in the first contact metal film; a source electrode film formed on a surface of a contact metal layer including the first contact metal film and the second contact metal film. The first contact metal film includes titanium nitride, and the second contact metal film includes titanium.

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.

Abstract: A semiconductor structure includes a substrate; at least one mask layer spaced apart from the substrate in a first direction; a first semiconductor region of a first conductivity type between the substrate and the at least one mask layer; a second semiconductor region of a second conductivity type on the at least one mask layer; and a third semiconductor region of the first conductivity type on the first semiconductor region. The third semiconductor region may contact the second semiconductor region to form a PN-junction structure in a second direction different from the first direction. The semiconductor structure may be applied to vertical power devices and may be capable of increasing withstand voltage performance and lowering an on-resistance.

Abstract: A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.