Abstract: A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111> oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region including first and second compounds including silicon and carbon. The first semiconductor region includes first to third regions contacting the second semiconductor region. The third region is positioned between the first and second regions. The first and second regions include a first element. The first element includes at least one selected from the group consisting of second and third elements. The second element includes at least one selected from the group consisting of Ar, Kr, Xe, and Rn. The third element includes at least one selected from the group consisting of Cl, Br, I, and At. The third region does not include the first element, or a concentration of the first element in the third region is lower than concentrations of the first element in the first and second regions.

Abstract: Contemplated is a semiconductor device comprising: a substrate; a group (III)-nitride layer; a metal-group (III)-nitride layer deposited between the substrate and group (III)-nitride layer; and a metal-nitride layer deposited between the substrate and the metal-group (III)-nitride layer. Also a method for making a semiconductor device with the above mentioned structure is contemplated. Furthermore, the substrate can be a silicon on insulator (SOI) substrate; the metal-nitride layer can be an aluminium nitride layer; the metal-group (III)-nitride layer can be an aluminium gallium nitride layer; and the group (III)-nitride layer can be a gallium nitride layer.

Abstract: The purpose of the present invention is to provide a method for manufacturing a light-amplified optoelectronic device, on which pristine or doped graphene is transferred. Specifically, the method includes the steps of: depositing a first electrode, as a thin film, on the light emitting device; transferring pristine or doped graphene on the electrode thin film; etching the light emitting device in contact with the electrode thin film on which the transferred graphene has been transferred, thereby removing a part of the electrode thereon; spin-coating photoresist on the etched light emitting device; removing the photoresist from the spin-coated light emitting device, thereby forming an electrode thin film in a spin form and the pristine transferred to or graphene doped to the electrode thin film; and depositing metal on a second electrode.

Abstract: Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

Abstract: A semiconductor base substance includes: a substrate; a buffer layer which is made of a nitride semiconductor and provided on the substrate; and a channel layer which is made of a nitride semiconductor and provided on the buffer layer, wherein the buffer layer includes: a first region which is provided on the substrate side and has boron concentration higher than acceptor element concentration; and a second region which is provided on the first region, and has boron concentration lower than that in the first region and acceptor element concentration higher than that in the first region. As a result, the semiconductor base substance which can obtain a high pit suppression effect while maintaining a high longitudinal breakdown voltage is provided.

Abstract: A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.

Abstract: In one aspect, a method for manufacturing a Schottky diode with double P-type epitaxial layers may include steps of: providing a substrate; forming a first epitaxial layer on top of the substrate; forming a second epitaxial layer on top of the first epitaxial layer; depositing a third epitaxial layer on top of the second epitaxial layer; patterning the second and third epitaxial layers to form a plurality of trenches in the second and third epitaxial layers; depositing a first ohmic contact metal on a backside of the substrate; forming a second ohmic contact metal on top of the patterned third epitaxial layer; forming a Schottky contact metal at a bottom portion of each trench; and forming a pad electrode on top of the Schottky contact metal. In one embodiment, the second and third epitaxial layers can be made by P? type SiC and P+ type SiC, respectively.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region including a first compound including silicon and carbon, and a second semiconductor region including a second compound including silicon and carbon. The first semiconductor region includes first to third regions contacting the second semiconductor region. The third region is positioned between the first region and the second region. The first region and the second region include germanium. The third region does not include germanium, or a concentration of germanium in the third region is lower than a concentration of germanium in the first region and lower than a concentration of germanium in the second region.

Abstract: A semiconductor device includes: a substrate; a drift layer which is disposed on the substrate and has a groove; an underlayer which is disposed above the drift layer; a first opening which penetrates the underlayer to reach the drift layer; an electron transit layer and an electron supply layer which are disposed to cover the first opening; a second opening which penetrates the electron supply layer and the electron transit layer to reach the underlayer; a gate electrode which is disposed above the electron supply layer at a position corresponding to a position of the first opening; a source electrode which is disposed to cover the second opening and in contact with the underlayer; and a drain electrode which is disposed on a backside surface of the substrate. A bottom surface of the groove is closer to the substrate than a bottom surface of the first opening.

Abstract: The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.

Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Abstract: A method of manufacture and structure for an acoustic resonator device having a hybrid piezoelectric stack with a strained single crystal layer and a thermally-treated polycrystalline layer. The method can include forming a strained single crystal piezoelectric layer overlying the nucleation layer and having a strain condition and piezoelectric layer parameters, wherein the strain condition is modulated by nucleation growth parameters and piezoelectric layer parameters to improve one or more piezoelectric properties of the strained single crystal piezoelectric layer. Further, the method can include forming a polycrystalline piezoelectric layer overlying the strained single crystal piezoelectric layer, and performing a thermal treatment on the polycrystalline piezoelectric layer to form a recrystallized polycrystalline piezoelectric layer. The resulting device with this hybrid piezoelectric stack exhibits improved electromechanical coupling and wide bandwidth performance.

Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a type III-V semiconductor back-barrier region, a type III-V semiconductor channel layer formed on the back-barrier region, and a type III-V semiconductor barrier layer formed on the back-barrier region. A first two-dimensional charge carrier gas is at an interface between the channel and barrier layers. A second two-dimensional charge carrier gas is disposed below the first two-dimensional charge carrier gas. A deep contact structure in the heterojunction semiconductor body that extends through the channel layer and forms an interface with the second two-dimensional charge carrier gas is formed. The first semiconductor region includes a first contact material that provides a conductive path for majority carriers of the second two-dimensional charge carrier gas at the interface with the second two-dimensional charge carrier gas.

Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.

Abstract: A semiconductor device includes a mechanical release layer, such as a van der Waals buffer layer, with a predetermined material roughness and thickness adjacent to a first substrate; a nucleation layer adjacent to the mechanical release layer; and a first semiconductor layer attached to the nucleation layer. The first semiconductor layer, the nucleation layer, and a portion of the mechanical release layer are releasably connected to the first substrate. The predetermined material roughness and thickness of the mechanical release layer determines a bonding strength of the first semiconductor layer to the first substrate. The semiconductor device may include an aluminum nitride insert layer adjacent to the first semiconductor layer; an aluminum gallium nitride barrier layer adjacent to the aluminum nitride insert layer; and a second semiconductor layer adjacent to the aluminum gallium nitride barrier layer.

Abstract: A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon. A related substrate is also disclosed.

Abstract: A drift layer is made of a wide bandgap semiconductor. First well regions are formed on the drift layer. A source region is formed on each of the first well regions. A gate insulating film is formed on the first well regions. A first electrode is in contact with the source regions, and has diode characteristics allowing unipolar conduction to the drift layer between the first well regions. A second well region is formed on the drift layer. A second electrode is in contact with the second well region, and separated from a gate electrode and the first electrode.

Abstract: Methods of forming a thin-film piezoelectric acoustic filter, a GaN-channel/buffer Bragg reflector, and a monolithically integrated GaN HEMT PA and CMOS over a [111] crystal orientation Si handle of a SOI wafer and resulting devices are provided. Embodiments include providing a SOI wafer including a [111] crystal orientation Si handle, a BOX layer, and a top Si layer; forming a CMOS device over the top Si layer; and forming a Bragg reflector over the [111] crystal orientation Si handle wafer, the Bragg reflector including a GaN stack with alternating layers of high/low acoustic impedance.

Abstract: A semiconductor device includes a semiconductor stack comprising a surface, and an electrode structure comprises an electrode pad formed on the surface, and the electrode structure further comprises a first extending electrode, a second extending electrode and a third extending electrode connecting to the electrode pad. The first extending electrode is closer to a periphery of the surface than the third extending electrode is, and the second extending electrode is between the first extending electrode and the third extending electrode. From a top view of the semiconductor device, the first extending electrode, the second extending electrode and the third extending electrode respectively include a first curve having a first angle ?1, a second curve having a second angle ?2 and a third curve having a third angle ?3, wherein ?3>?2>?1 .

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

Abstract: A display device includes a substrate, a first electrode, a second electrode, and a protective layer. The first electrode is disposed on the substrate. The second electrode has a first segment and a second segment. The first segment is located at a first side of the first electrode. The second segment is located at a second side of the first electrode. The second side is opposite to the first side. The protective layer overlaps the first segment and the second segment. The first segment has a length which is shorter than that of the second segment. The display device further includes a light-emitting element disposed on the substrate.

Abstract: A semiconductor device including a substrate, a semiconductor layer, and a buffer structure is provided. The semiconductor layer is located on the substrate. The buffer structure is located between the substrate and the semiconductor layer. The buffer structure includes a plurality of first layers and a plurality of second layers. The first layers and the second layers are alternately stacked with a same pitch or different pitches.

Abstract: An OLED display device and a method for manufacturing the OLED display device are provided. The OLED display device comprises a substrate, a first electrode disposed on the substrate, a hole injection layer disposed on the first electrode, an organic light emitting layer disposed on the hole injection layer, an electron injection layer disposed on the organic light emitting layer, and a second electrode disposed on the electron injection layer. A material of the electron injection layer comprises an inorganic electron injecting material and an organic electron transporting material which can be dissolved in a polar solvent. The OLED display device and the method for manufacturing the OLED display device can effectively improve the electron injection efficiency for providing an excellent electron injection effect through the electron injection layer is prepared by a solution in which the inorganic salt material and the organic material were mixed.

Abstract: A nitride semiconductor template includes a substrate, and a chlorine-containing nitride semiconductor layer. The chlorine-containing nitride semiconductor layer contains an iron concentration of not higher than 1×1017 cm?3.

Abstract: A structure with micro device including a substrate, at least one micro device, at least one holding structure, and at least one buffering structure is provided. The micro device is disposed on the substrate and has a top surface away from the substrate, a bottom surface opposite to the top surface, and a circumferential surface connecting the top surface and the bottom surface. The holding structure is disposed on the substrate. From the cross-sectional view, a thickness of the holding structure in a normal direction of the substrate gradually increases from the boundary of the top surface and the circumferential surface to the substrate. The buffering structure is disposed between the holding structure and the substrate. The holding structure is connected to the substrate through the buffering structure.

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part.

Abstract: A heterojunction semiconductor device is disclosed. The heterojunction semiconductor device includes a substrate and a multilayer structure disposed on the substrate. The multilayer structure includes a first layer comprising a first semiconductor disposed on top of the substrate, and a second layer comprising a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas forms adjacent to the interface. The device also includes a first terminal electrically coupled to a first area of the interface between the first layer and second layer and a second terminal electrically coupled to a second area of the interface between the first layer and second layer. The device also includes an electrically conducting channel comprising an implanted region at bottom and sidewalls.

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.

Abstract: The present disclosure relates to devices and techniques for an interconnect bridge to communicatively couple two or more dies. In an example, the interconnect bridge can include a base element having a first material. A first layer, including a second material, can be attached to the base element. A second layer, including a third material, can be disposed on the first layer. A two-dimensional electron gas (2DEG) can be located between the first layer and the second layer. A first contact, adapted to electrically couple to the first die, can be disposed in a first side of the 2DEG. A second contact, adapted to electrically couple to the second die, can be disposed in a second side of the 2DEG. Accordingly, the first die can be electrically coupled to the second die through the 2DEG.

Abstract: A light generating device, comprising: at least one light emitting diode having a semiconductor layer that emits a first primary light, and having a phosphor layer arranged on the semiconductor layer, and at least one laser for generating at least one laser beam composed of a second primary light, by means of which the phosphor layer is irradiatable, wherein the phosphor layer is configured for at least partly converting the first primary light into at least one first secondary light and for at least partly converting the second primary light into at least one second secondary light. The light generating device is configured to dynamically illuminate the phosphor layer by means of the second primary light.

Abstract: A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess.

Abstract: A semiconductor device according to the present invention includes a semiconductor chip having a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface, a conductive substrate onto which the semiconductor chip is die-bonded, a conductive spacer that has a planar area smaller than that of the first electrode and supports the semiconductor chip on the conductive substrate, and a resin package that seals at least the semiconductor chip and the conductive spacer.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

Abstract: A nitride semiconductor epitaxial stack structure including: a Silicon substrate; an aluminum-including nucleation layer disposed on the silicon substrate; a buffer structure disposed on the aluminum-including nucleation layer and sequentially including: a first superlattice epitaxial structure, a first GaN based thick layer disposed on the first superlattice epitaxial structure, a second superlattice epitaxial structure disposed on the first GaN based thick layer, and a second GaN based thick layer disposed on the second superlattice epitaxial structure; a channel layer disposed on the buffer structure; a barrier layer disposed on the channel layer; and a two dimensional electron gas layer disposed near an interface between the channel layer and the barrier layer, wherein the total thickness of the first GaN based thick layer and the second GaN based thick layer is more than 2 micrometers.

Abstract: A method, device, and system for calibrating and adapting transmission rate in wireless communication is disclosed. The method includes sending, based on a static Module and Coding Schemes (MCS) probe table, a plurality of probe packets at each of a set of probe MCSs associated with a current MCS. The static MCS probe table includes a plurality of MCSs and a set of probe MCSs associated with each of the plurality of MCSs. The method further includes determining percentage of probe packets successfully received by a receiver for each of the set of probe MCSs associated with the current MCS, based on a link adaptation statistic packet received from the receiver. The method includes identifying an MCS from the set of probe MCSs for subsequent transmissions based on the determined percentage.

Abstract: Methods for fabricating semiconductor devices incorporating an activated p-(Al,In)GaN layer include exposing a p-(Al,In)GaN layer to a gaseous composition of H2 and/or NH3 under conditions that would otherwise passivate the p-(Al,In)GaN layer. The methods do not include subjecting the p-(Al,In)GaN layer to a separate activation step in a low hydrogen or hydrogen-free environment. The methods can be used to fabricate buried activated n/p-(Al,In)GaN tunnel junctions, which can be incorporated into electronic devices.

Abstract: A nitride semiconductor device includes: an electron transit layer including GaxIn1-xN (0<x?1); an electron supply layer formed on the electron transit layer and including AlyIn1-yN (0<y?1); a gate insulating film formed to pass through the electron supply layer to contact the electron transit layer; and a gate electrode facing the electron transit layer with the gate insulating film interposed therebetween, wherein, in the electron transit layer, a portion contacting the gate insulating film and a portion contacting the electron transit layer are flush with each other.

Abstract: An UV light-emitting diode includes a patterned substrate, a template layer, a growth layer, a first n-type semiconductor layer, an intrinsic semiconductor layer, a second n-type semiconductor layer, a plurality of layers of multiple quantum wells, a barrier layer, a first electron blocking layer, a second electron blocking layer, a first p-type semiconductor layer and a second p-type semiconductor layer in sequence from a bottom layer to a top layer. Whereas the aforementioned layers all include Group III nitride materials and the number of layers for the plurality of layers of multiple quantum wells is at least five layers. Because the first n-type semiconductor layer, the first p-type semiconductor layer, and the plurality of layers of multiple quantum wells all contain aluminum, short-wavelength UV light is emitted when a current is applied.

Abstract: A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a sidewall of the structure defined by the silicon material; adjusting a growth condition to facilitate a first growth rate of the III-V material in directions along a surface of the sidewall and a second growth rate of the III-V material in a direction laterally from the surface of the sidewall, wherein the second growth rate is less than the first growth rate; and processing the silicon material and the III-V material to form a fin.

Abstract: An efficient and economical process for H2 evolution by water splitting, catalyzed by layered oxides that function in UV and visible light.

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.

Abstract: An RAMO4 substrate that includes an RAMO4 monocrystalline substrate formed of a single crystal represented by general formula RAMO4, wherein R represents one or more trivalent elements selected from the group consisting of Sc, In, Y, and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga, and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn, and Cd. The RAMO4 monocrystalline substrate has a principal surface with a plurality of grooves. The principal surface has an off-angle ? with respect to a cleaving surface of the single crystal. The RAMO4 monocrystalline substrate satisfies tan ??Wy/Wx, where Wx is the width at the top surface of a raised portion between the grooves, and Wy is the height of the raised portion.

Abstract: Provided is a III nitride semiconductor light emitting device with improved reliability capable of maintaining light output power reliably as compared with conventional devices, and a method of producing the same. The III-nitride semiconductor light-emitting device comprising: a light emitting layer, a p-type electron blocking layer, a p-type contact layer, and a p-side electrode in this order. The p-type contact layer has a first p-type contact layer co-doped with Mg and Si in contact with the p-type electron blocking layer and a second p-type contact layer doped with Mg in contact with the p-side electrode.

Abstract: Problems associated with the mismatch between a silicon substrate and a group-IIIA nitride layer are addressed by employing a silicon substrate processed to have a surface comprising closely spaced tips extending from the surface, depositing a group-IIIB silicide layer on the tips, then depositing a group-IIIB nitride layer, and then depositing a group-IIIA nitride.

Abstract: A MOS gate having a trench gate structure is formed on the front surface side of a silicon carbide substrate. A gate trench of the trench gate structure goes through an n+ source region and a p-type base region and reaches an n? drift region. Between adjacent gate trenches, a first p+ region that goes through the p-type base region in the depth direction and reaches the n? drift region is formed at a position separated from the gate trenches. The first p+ region is formed directly beneath a p++ contact region. The width of the first p+ region is less than the width w1 of the gate trench. A second p+ region is formed at the bottom of the gate trench. The first and second p+ regions are silicon carbide epitaxial layers.

Abstract: A high electron mobility transistor includes a semiconductor structure having a channel layer and a cap layer forming a two dimensional electron gas (2-DEG) channel, and a source, a drain, and a gate electrodes. The gate is arranged on the cap layer between the source and the drains, such that the conductivity of the 2-DEG channel is modulated in response to applying voltage to the gate. The cap layer includes III-N material. The gate has a layered structure including a bottom metal layer arranged on cap layer, a ferroelectric oxide (FEO) layer arranged on bottom metal layer, and a top metal layer arranged on the FEO layer. Thickness of FEO layer is less than tcap/(2??cap), wherein ? is a parameter of material of FEO layer, tcap is thickness of cap layer, and ?cap is electric permittivity of cap layer.