Abstract: A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor.

Abstract: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.

Abstract: A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

Abstract: A package substrate includes a workpiece having at least a top dielectric layer and a metal layer thereon which provides a plurality of metal traces on a surface of the top dielectric layer. A first solder resist layer provides covered trace portions of the plurality of metal traces. A second solder resist layer on the first solder resist layer defines an inner die attach region. The die attach region includes exposed trace portions of the metal traces. The exposed trace portions each include (i) a bonding area having a base metal and a metal or metal alloy surface finish thereon for bonding to bonding features of an integrated circuit (IC) die, and (ii) an interconnect trace portion on both sides of the bonding area including the base metal having a second surface finish thereon different from the metal or metal alloy surface finish.

Abstract: An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.

Abstract: A semiconductor device includes a workpiece and a first material layer disposed over the workpiece. The first material layer has a first number of atoms at a surface. A seed layer is disposed over the first material layer. The seed layer includes a chemisorbed monolayer of a second number of atoms at the surface having a surface coverage of at least 0.5 such that the ratio of the number of first atoms at the surface to the number of second atoms at the surface is no more than 2:1. The second atoms of the seed layer include oxygen or nitrogen.

Abstract: A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

Abstract: A chip bonding structure at least includes a first substrate, a second substrate opposite to the first substrate, and a copper bonding structure sandwiched in between the first and the second substrates. A Cu—Cu bonding interface is within the copper bonding structure and is characterized with combinations of protrusions and recesses, and the copper crystallization orientation at one side of the Cu—Cu bonding interface is different from that at another side.

Abstract: A template having tapered openings can be employed to enable injection of underfill material through gaps having a width less than a lateral dimension of an injector needle for the underfill material. Each tapered opening has a first lateral dimension on an upper side and a second lateral dimension on a lower side. Compliant material portions can be employed to accommodate variations in distance between the template and stacked semiconductor chips and/or an injector head. Optionally, another head can be employed to apply compressed gas to push out the underfill material after the underfill material is applied to the gaps. Multiple injector heads can be employed to simultaneously inject the underfill material at different sites. An adhesive layer can be substituted for the at least one lower compliant material portion.

Abstract: A template having tapered openings can be employed to enable injection of underfill material through gaps having a width less than a lateral dimension of an injector needle for the underfill material. Each tapered opening has a first lateral dimension on an upper side and a second lateral dimension on a lower side. Compliant material portions can be employed to accommodate variations in distance between the template and stacked semiconductor chips and/or an injector head. Optionally, another head can be employed to apply compressed gas to push out the underfill material after the underfill material is applied to the gaps. Multiple injector heads can be employed to simultaneously inject the underfill material at different sites. An adhesive layer can be substituted for the at least one lower compliant material portion.

Abstract: A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.

Abstract: A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene forms an electrical connection between two or more VIAs or components, or a combination of VIAs and components. A VIA includes a fill metal, with at least a portion of the fill metal being surrounded by a barrier metal. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300° C.-400° C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper.

Abstract: Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.

Abstract: Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.

Abstract: Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of wiring lines which are provided on one side of the semiconductor substrate and which have connection pad portions, and a plurality of columnar electrodes respectively provided on the connection pad portions of the wiring lines, each of the columnar electrodes including an outer peripheral surface and a top surface. An electromigration prevention film is provided on at least the surfaces of the wiring lines. A sealing film is provided around the outer periphery surfaces of the columnar electrodes.

Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.

Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool.

Abstract: A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space, wherein an edge of the first metal line is exposed to the first air gap. A second air gap is on a sidewall of the second metal line and in the space, wherein an edge of the second metal line is exposed to the second air gap. A dielectric material is disposed in the space and between the first and the second air gaps.

Abstract: A power semiconductor device may comprise: a lower structure; a solder layer on the lower structure; a semiconductor structure on the solder layer; a contact layer on the semiconductor structure; a pad layer on the contact layer; and/or a wire between the pad layer and the lower structure. The solder layer may be electrically connected to a first electrode of the semiconductor structure.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

Abstract: A diode arrangement includes a diode and two electrodes. Each electrode is connected to the diode in an electrically conductive manner via a soldered connection on one of two oppositely arranged contact surfaces of the diode. The contact surfaces of the diode are formed substantially by the surfaces of a lower side and an upper side of the diode and are contacted with the contact extensions of the electrodes via the soldered connection. The contact extensions forming counter contact surfaces are substantially congruent with the contact surfaces of the diode.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.

Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract: In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.

Abstract: A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 ?m and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer adjoining a different layer of the multilayer metallization. The interlayer includes at least one of W, WTi, Ta, TaN, TiW, and TiN or other suitable compound metal or a metal silicide such as WSi, MoSi, TiSi, and TaSi.

Abstract: An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.

Abstract: A semiconductor device includes a circuit substrate which is configured with an insulative substrate formed of a ceramic material and provided on its one surface with an electrode formed of a copper material, and a power semiconductor element bonded with the electrode using a sinterable silver-particle bonding material, wherein the electrode has a Vickers hardness of 70 HV or more in its portion from the bonding face with the power semiconductor element toward the insulative substrate to a depth of 50 ?m, and has a Vickers hardness of 50 HV or less in its portion at the side toward the insulative substrate.

Abstract: The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.

Abstract: In one embodiment, an assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor.

Abstract: The present invention provides a semiconductor device, a semiconductor package and a semiconductor process. The semiconductor process includes the following steps: (a) providing a semiconductor wafer having a first surface, a second surface and a passivation layer; (b) applying a first laser on the passivation layer to remove a part of the passivation layer and expose a part of the semiconductor wafer; (c) applying a second laser, wherein the second laser passes through the exposed semiconductor wafer and focuses at an interior of the semiconductor wafer; and (d) applying a lateral force to the semiconductor wafer. Whereby, the cutting quality is ensured.

Abstract: A power semiconductor module has an insulating layer; a copper base substrate having first and second copper blocks, either the first or the second copper block being fixed on one side and the other being fixed on the other side of the insulating layer; a plurality of power semiconductor elements using silicon carbide, and having one side fixed onto the first copper block with a conductive bond layer; a plurality of implant pins fixed to the other side of each of the plurality of power semiconductor elements with a conductive bond layer; a printed circuit board fixed to the implant pins and disposed to face the power semiconductor elements; a first sealing material containing no flame retardant, and disposed at least between the power semiconductor elements and the printed circuit board; and a second sealing material containing a flame retardant, and disposed to cover the first sealing material.

Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have line widths of less than forty nanometers. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, performing a first sputter etch of the layer of conductive metal using a methanol plasma, and performing a second sputter etch of the layer of conductive metal using a second plasma, wherein a portion of the layer of conductive metal that remains after the second sputter etch forms the one or more conductive lines.

Abstract: An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics.

Abstract: A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad.

Abstract: A packaging substrate includes a base layer, a first wiring layer, a second wiring layer, a first solder mask layer, a second solder mask layer and copper portions. The first second wiring layers are arranged on opposite sides of the base layer. The first solder mask layer covers the first wiring layer, and defines plenty of first openings. The first wiring layer exposed through the first openings serves as first contact pads. The second solder mask layer covers the second wiring layer. The second solder mask layer defines plenty of second openings. The second wiring layer exposed through the second openings serves as second contact pads. The copper portions are formed on the second contact pads. The copper portions protrude beyond the second solder mask layer. This disclosure further relates to a method of manufacturing the packaging substrate and a chip packaging body.

Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.

Abstract: X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.

Abstract: To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 ?m to 10 ?m from the edge of the concave to the bottom of the concave.

Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

Abstract: A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width WP and a metal line trace, provided on a package substrate, having a top surface with a width WT, where WP is greater than WT. The solder joint is bonded to the bonding surface by wetting across the width WP and bonded predominantly only to the top surface of the metal line trace by wetting predominantly only to the top surface across the width WT.

Abstract: A bonded structure 106 includes a semiconductor element 102 bonded to a Cu electrode 103 with a bonding material 104 predominantly composed of Bi, wherein the semiconductor element 102 and the Cu electrode 103 are bonded to each other via a laminated body 209a that progressively increases a Young's modulus from the bonding material 104 to a bonded material (the semiconductor element 102 and the Cu electrode 103), achieving stress relaxation against a thermal stress generated in a temperature cycle during the use of a power semiconductor module.

Abstract: A semiconductor device includes a copper-containing post overlying and electrically connected to a bond pad region. The semiconductor device further includes a protection layer on a surface of the copper-containing post, where the protection layer includes manganese.

Abstract: A method, and an apparatus formed thereby, to construct shallow recessed wells on top of exposed conductive vias on the surface of a semiconductor. The shallow recessed wells are subsequently filled with a conductive cap layer, such as a tantalum nitride (TaN) layer, to prevent or reduce oxidation which may otherwise occur naturally when exposed to air, or possibly occur during an under-bump metallization process.

Abstract: Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate; (ii) a plurality of first connecting structures and a plurality of second connecting structures that are aligned and configured to electrically connect the chip and the substrate; and (iii) where each of the plurality of first connecting structures comprises a first metal, and each of the plurality of second connecting structures comprises a second metal, and where a hardness of the first metal is less than a hardness of the second metal.

Abstract: A semiconductor device includes: a plurality of semiconductor chips stacked on each other, each of the plurality of semiconductor chips having a semiconductor substrate and a wiring layer; a through electrode penetrating the semiconductor substrate in a thickness direction and electrically connected to each other between the semiconductor chips adjacent to each other; a conductor penetrating the semiconductor substrate in the thickness direction and not electrically connected between the other semiconductor chips; and an insulating separator penetrating the semiconductor substrate in the thickness direction and formed in a shape of a ring surrounding the conductor.