Layered Patents (Class 257/750)
  • Patent number: 10692756
    Abstract: A method for forming a dual damascene interconnect structure. A substrate having a conductor layer, an etch stop layer on the conductor layer, a dielectric stack on the etch stop layer, and a hard mask layer on the dielectric stack is provided. A photoresist layer having a resist opening is formed on the hard mask layer. The hard mask layer is etched through the resist opening to form a hard mask opening. The dielectric stack is etched through the hard mask opening to form a partial via hole. The photoresist layer is trimmed to form a widened resist opening above the partial via hole. The hard mask layer is etched through the widened resist opening to form a widened hard mask opening above the partial via hole. The dielectric stack is etched through the widened hard mask opening and the partial via hole to form a dual damascene via.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: June 23, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jian Xu, Liang Xiao, Jin Wen Dong, Meng Yan, Li Hong Xiao
  • Patent number: 10685878
    Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh, Sarah A. Niroumand
  • Patent number: 10685915
    Abstract: A first dielectric layer on a substrate is provided. The first dielectric layer has a first level metal line embedded in the dielectric. An opposite gouging feature is in a top surface of the first level metal line. The opposite gouging feature has a protuberant shape relative to the first level metal line. A second dielectric layer is over the first dielectric layer. A compound recess is in the second dielectric layer. A first portion of the recess is for a via connector positioned over the opposite gouging feature.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theodorus E Standaert
  • Patent number: 10669647
    Abstract: The present disclosure relates to a method for producing a network of interconnected nanostructures comprising the steps of: providing a substantially plane substrate; growing a plurality of elongated nanostructures from the substrate; kinking the growth direction of at least a part of the nanostructures such that at least part of the kinked nanostructures are growing in a network plane parallel to the substrate, and creating one or more network(s) of interconnected kinked nanostructures in the network plane, wherein a dielectric support layer is provided below the network plane to support said network(s) of interconnected nanostructures.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 2, 2020
    Assignee: University of Copenhagen
    Inventors: Peter Krogstrup, Charles Marcus, Thomas Sand Jespersen, Jesper Nygård
  • Patent number: 10665586
    Abstract: A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Cheng Chi
  • Patent number: 10658280
    Abstract: An electrical device includes a substrate and a via. The substrate has a first surface and defines a recess in the first surface. The via is disposed in the recess. The via includes an insulation layer, a first conductive layer and a second conductive layer. The insulation layer is disposed on the first surface of the substrate and extends at least to a sidewall of the recess. The first conductive layer is disposed adjacent to the insulation layer and extends over at least a portion of the first surface. The second conductive layer is disposed adjacent to the first conductive layer and extends over at least a portion of the first surface. The second conductive layer has a negative coefficient of thermal expansion (CTE).
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 19, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10651043
    Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 12, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Minrui Yu, Mehul B. Naik
  • Patent number: 10644117
    Abstract: A method may include providing a device structure, where the device structure includes a semiconductor region, and a gate structure, disposed over the semiconductor region. The gate structure may further include a gate metal. The method may further include oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: May 5, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Wenhui Wang, Jun Lee, Sony Varghese
  • Patent number: 10629479
    Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 10629686
    Abstract: A semiconductor power device may include a Silicon Carbide (SiC) layer having an active power device formed on a first surface thereof. An Ohmic contact layer may be formed on a second, opposing surface of the SiC layer, the Ohmic contact layer including Nickel Silicide (NiSix) with a first silicide region containing a first precipitate of non-reacted carbon disposed between the SiC layer and a second silicide region. The second silicide region may be disposed between the first silicide region and a third silicide region, and may include a mixture of a first precipitate of refractory metal carbide and a second precipitate of non-reacted carbon. The third silicide region may contain a second precipitate of refractory metal carbide. A solder metal layer may be formed on the Ohmic contact layer, with the third silicide region disposed between the second silicide region and the solder metal layer.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 21, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Thi Thu Phuong Pham, Kyeongseok Park, Andrei Konstantinov, Thomas Neyer
  • Patent number: 10629808
    Abstract: A method for forming a phase change random access memory is provided. The method includes providing a substrate having a surface; and forming a dielectric layer on the surface of the substrate. The method also includes forming a through-hole penetrating through the dielectric layer; and forming an adhesion layer on inner surface of the through-hole. Further, the method includes forming a metal layer doped with inorganic ions on the adhesion layer to reduce over-etching of the metal layer and increase heating efficiency of the metal layer on the surface of the adhesion layer; and forming a phase change layer on the dielectric layer, the adhesion layer and the doped metal layer.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: April 21, 2020
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Zhichao Li, Guangcai Fu
  • Patent number: 10629478
    Abstract: A method of forming a semiconductor device includes forming a dielectric spacer along sidewalls of a plurality of interconnect openings extending through a sacrificial dielectric layer and a first dielectric layer until a top portion of a first conductive material, the dielectric spacer includes a dielectric material having a dielectric constant higher than a dielectric constant of the sacrificial dielectric layer and higher than a dielectric constant of the first dielectric layer, conformally depositing a barrier liner within the plurality of interconnect openings above and in direct contact with the dielectric spacer, filling the interconnect openings with a second conductive material, removing the sacrificial dielectric layer to expose portions of the dielectric spacer above the first dielectric layer, and reducing a thickness of exposed portions of the dielectric spacer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Huai Huang, Christopher J. Penny, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 10612149
    Abstract: This invention relates to a platinum electrodeposition bath which is capable of forming platinum deposits having an attractive shiny granular surface like a velvet, which is particularly useful in jewelry manufacturing. The velvet effect can be illustrated by comparing the surface roughness with a bright smooth platinum deposit.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 7, 2020
    Assignee: CHOW SANG SANG JEWELLERY COMPANY LIMITED
    Inventors: Wai Kei Cheung, Shuk Kwan Mak, Candice Wing Jong Tong
  • Patent number: 10600921
    Abstract: In forming an ohmic electrode on a back surface of an n-type SiC substrate, an n+-type semiconductor region is formed in a surface layer of the back surface of an n-type epitaxial substrate by ion implantation. In this ion implantation, the impurity concentration of the n+-type semiconductor region is a predetermined range and preferably a predetermined value or less, and an n-type impurity is implanted by acceleration energy of a predetermined range such that the n+-type semiconductor region has a predetermined thickness or less. Thereafter, a nickel layer and a titanium layer are sequentially formed on the surface of the n+-type semiconductor region, the nickel layer is heat treated to form a silicide, and the ohmic electrode formed from nickel silicide is formed. In this manner, a back surface electrode that has favorable properties can be formed while peeling of the back surface electrode can be suppressed.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: March 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Fumikazu Imai, Tsunehiro Nakajima, Kenji Fukuda, Shinsuke Harada, Mitsuo Okamoto
  • Patent number: 10522403
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jason E. Stephens, Daniel Chanemougame, Ruilong Xie, Lars W. Liebmann, Gregory A. Northrop
  • Patent number: 10512165
    Abstract: A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: December 17, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Ching-Hao Huang, Ho-Shing Lee, Yu-Cheng Lin
  • Patent number: 10490505
    Abstract: In some examples, a circuit package further includes an insulating layer and a first transistor extending through the insulating layer, where the first transistor includes a first control terminal on a top side of the insulating layer, a first source terminal on the top side of the insulating layer, and a first drain terminal on a bottom side of the insulating layer. The circuit package includes a second transistor extending through the insulating layer, where the second transistor includes a second control terminal on the top side of the insulating layer, a second source terminal on the bottom side of the insulating layer, and a second drain terminal on the top side of the insulating layer.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: November 26, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Patent number: 10446494
    Abstract: A trench is formed in an insulating film, carbon is formed on the insulating film to fill an inside of the trench, a catalytic material is formed on the carbon, heat treatment is performed on the carbon to turn the carbon into graphenes which are stacked in a plurality of layers, and the catalytic material and a part of the graphenes on the insulating film are removed to make the graphenes remain only in the trench.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Motonobu Sato
  • Patent number: 10418553
    Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may comprise depositing metal layers, such layers of a transition metal, over a conductive substrate. Dopant layers may subsequently be deposited on the layers of the transition metal, followed by annealing of the layers of transition metal and dopant layers. Responsive to annealing, dopant from the dopant layers may diffuse into the one or more layers of transition metal, thereby forming a CEM.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 17, 2019
    Assignee: ARM Ltd.
    Inventors: Lucian Shifren, Carlos Alberto Paz de Araujo, Jolanta Bozena Celinska, Christopher Randolph McWilliams
  • Patent number: 10403591
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 3, 2019
    Assignee: XILINX, INC.
    Inventor: Jaspreet Singh Gandhi
  • Patent number: 10340278
    Abstract: A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 2, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wei-Hsin Liu, Cheng-Hsu Huang, Jui-Min Lee, Yi-Wei Chen
  • Patent number: 10340206
    Abstract: A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Jui Kuo, Hui-Jung Tsai
  • Patent number: 10340229
    Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dirk Breuer, Georg Talut
  • Patent number: 10332840
    Abstract: A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 25, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Kai-Chieh Hsu
  • Patent number: 10319628
    Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 11, 2019
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Fabien Deprat, Perrine Batude, Laurent Brunet, Claire Fenouillet-Beranger, Maud Vinet
  • Patent number: 10290584
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10283471
    Abstract: A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hsiung Lu, Chen-Shien Chen, Chen-En Yen, Cheng-Jen Lin, Chin-Wei Kang, Kai-Jun Zhan
  • Patent number: 10276529
    Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Kenneth N. Hagen
  • Patent number: 10262961
    Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mayukhee Das, Jonathan S. Hacker, Christopher J. Gambee, Chandra S. Tiwari
  • Patent number: 10256135
    Abstract: To provide a semiconductor device having a substrate contact in a deep trench thereof and having an improved characteristic. A PVD-metal film (metal film formed by PVD) is used as a first barrier metal film which is a lowermost layer barrier metal film formed in a deep trench penetrating an n type epitaxial layer and a reaching a layer therebelow. Such a configuration makes it possible to stably form a metal silicide layer at a boundary between the PVD-metal film and a silicon layer therebelow (or silicon substrate) and thereby stabilize the contact resistance.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuya Usami
  • Patent number: 10236255
    Abstract: A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed in the dielectric layer. The contact stack includes an electrically conductive contact element, and a contact liner on first and second opposing sidewalls of the contact element. A first air gap is interposed between the dielectric layer and the contact liner on the first side wall, and a second air gap interposed between the dielectric layer and the contact liner on the second side wall.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Junli Wang, Chih-Chao Yang
  • Patent number: 10186462
    Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Yun Chen Hsieh, Hung-Jui Kou
  • Patent number: 10176999
    Abstract: A film stack and manufacturing method thereof are provided. The film stack includes a plurality of first metal-containing films, and a plurality of second metal-containing films. The first metal-containing films and the second metal-containing films are alternately stacked to each other. The first metal-containing films and the second metal-containing films comprise the same metal element and the same nonmetal element, and a concentration of the metal element in the second metal-containing film is greater than a concentration of the nonmetal element in the second metal-containing film.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Wen Chang, Jian-Shiou Huang, Cheng-Yuan Tsai
  • Patent number: 10170426
    Abstract: A trench is formed in an insulating film, carbon is formed on the insulating film to fill an inside of the trench, a catalytic material is formed on the carbon, heat treatment is performed on the carbon to turn the carbon into graphenes which are stacked in a plurality of layers, and the catalytic material and a part of the graphenes on the insulating film are removed to make the graphenes remain only in the trench.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: January 1, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Motonobu Sato
  • Patent number: 10164045
    Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Tian Hou, Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung
  • Patent number: 10153232
    Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 11, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert J. Fox, III, Kevin M. Boyd, Nicholas A. Polomoff, Roderick A. Augur, Jeannine M. Trewhella
  • Patent number: 10147612
    Abstract: A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 4, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Nakanishi, Yusuke Tanaka, Atsushi Hieno, Yasuhito Yoshimizu, Akihiko Happoya
  • Patent number: 10147642
    Abstract: A method involving a barrier for preventing eutectic break-through in through-substrate vias is disclosed. The method generally includes steps (A) to (D). Step (A) may form one or more vias through a substrate. The substrate generally comprises a semiconductor. Step (B) may form a first metal layer. Step (C) may form a barrier layer. The barrier layer generally resides between the vias and the first metal layer. Step (D) may form a second metal layer. The second metal layer may be in electrical contact with the first metal layer through the vias and the barrier layer.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 4, 2018
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Allen W. Hanson, Rajesh Baskaran, Timothy E. Boles
  • Patent number: 10103057
    Abstract: Provided herein are methods for selectively forming layers of metal films on one portion of a substrate while leaving adjacent portions of the substrate uncoated. The methods provide for selectively depositing metal films on a conductive surface, such as ruthenium oxide, disposed on or near an insulating portion of the substrate, such as a silicon dioxide (SiO2) surface. The invention provides methods to simultaneously contact the substrate surface with both the precursor gas and the inhibitor agent leading to the selective formation of metal nuclei on the conductive portion of the substrate. In the methods described, nuclei are selectively formed by a disproportionation reaction occurring on the conductive portion of the substrate but not on the insulating portion of the substrate.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 16, 2018
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John Abelson, Shaista Babar, Elham Mohimi, Gregory Girolami
  • Patent number: 10090265
    Abstract: A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure and contains a first metal. An auxiliary layer stack is sandwiched between the conductive structure and the metal structure and includes an adhesion layer that contains a second metal. The auxiliary layer stack further includes a metal diffusion barrier layer between the adhesion layer and the conductive structure. The adhesion layer contains the first metal and a second metal.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: October 2, 2018
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Franziska Haering, Hans-Joachim Schulze, Bernhard Weidgans
  • Patent number: 10090260
    Abstract: A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 2, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Lun-Chun Chen, Meng-Yi Wu, Chih-Hao Huang, Tung-Cheng Kuo
  • Patent number: 10083904
    Abstract: Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric layer; forming a graded interlayer dielectric over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon film over the metal layer.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil Kumar Singh, Shesh Mani Pandey
  • Patent number: 10002840
    Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad, and a conductive interconnect can extend from the conductive structure.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 19, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Mayukhee Das, Jonathan S. Hacker, Christopher J. Gambee, Chandra S. Tiwari
  • Patent number: 10002834
    Abstract: A method and apparatus for forming an interconnect on a substrate is provided. A protective layer is formed on the substrate and in a via formed on the substrate wherein the protective layer is resistant to a halogen containing material. A barrier layer is formed on top of the protective layer. The barrier layer comprises a halogen containing material. A metal layer is deposited over the barrier layer. In another embodiment, the protective layer is selectively deposited in the via.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: June 19, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Mehul B. Naik, Paul F. Ma, Tae Hong Ha, Srinivas Guggilla
  • Patent number: 9978637
    Abstract: Various embodiments of mechanisms for forming through a three-dimensional integrated circuit (3DIC) structure are provided. The 3DIC structure includes an interposer bonded to a die and a substrate. The interposer has a conductive structure with through silicon vias (TSVs) connected to a patterned metal pad and a conductive structure on opposite ends of the TSVs. The pattern metal pad is embedded with dielectric structures to reduce dishing effect and has regions over TSVs that are free of the dielectric structures. The conductive structure has 2 or more TSVs. By using a patterned metal pad and 2 or more TSVs, the reliability and yield of the conductive structure and the 3DIC structure are improved.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Shih-Wen Huang, Chung-Yu Lu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 9960119
    Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 1, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Yan Xun Xue
  • Patent number: 9929081
    Abstract: An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an interconnect in the dielectric layer is provided, wherein the dielectric layer includes a stop layer contacting the oxide layer and the interconnect includes a metal structure having a barrier layer protruding from the stop layer. The substrate and the oxide layer are removed until exposing the stop layer and the barrier layer by a removing selectivity between the oxide layer and the stop layer. A wafer packaging structure formed by said interposer is also provided.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • Patent number: 9911689
    Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 6, 2018
    Assignee: INTEL CORPORATION
    Inventors: Kevin J. Lee, Ruchir Saraswat, Uwe Zillmann, Nicholas P. Cowley, Andre Schaefer, Rinkle Jain, Guido Droege
  • Patent number: 9905311
    Abstract: A shift register circuit has a plurality of unit circuits that are cascade-connected to one another and that output received pulse signals as output signals in accordance with a clock signal, the shift register circuit sequentially outputting the output signals from the plurality of respective unit circuits. The output circuits each include a double-gate transistor having first gate electrode that controls conductivity between the drain electrode and the source electrode, and a second gate electrode formed through an insulating layer and disposed to face the first gate electrode across a semiconductor layer between the drain electrode and the source electrode. The shift register circuit applies a prescribed voltage to the second gate electrode in accordance with a voltage applied to the first gate electrode.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: February 27, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuyuki Ogawa, Kaoru Yamamoto, Akihiro Oda, Masahiro Tomida
  • Patent number: 9892963
    Abstract: A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a trench in the dielectric layer. The method further includes depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum. The method further includes depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and depositing a metal layer over the Ta layer.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Lien Lee, Hung-Wen Su, Kuei-Pin Lee, Yu-Hung Lin, Yu-Min Chang