Solder Composition Patents (Class 257/772)
  • Patent number: 11903292
    Abstract: Provided is an organic light emitting display device. The organic light emitting display device includes a lower substrate including sub-pixels, a display area, a non-display area, and an exposed area; a lower touch pad unit in the non-display area and adjacent to the exposed area on the lower substrate; an upper substrate disposed opposite to the remaining area excluding the exposed area of the lower substrate; an upper touch pad unit on the upper substrate so as to correspond to the lower touch pad unit; a first connection electrode in direct contact with the lower touch pad unit; a second connection electrode opposite to the first connection electrode and in direct contact with the upper touch pad unit; and a self-assembly contact member disposed between the first connection electrode and the second connection electrode so as to electrically connect the first connection electrode and the second connection electrode.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 13, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: JoongHa Lee, DongKyu Lee, BooYoung Kim, YoungJun Hong, Onesouk Cho, SeongHoon Kim, SeYoung Kim, Jaehwan Yun, WonGyu Jeong, WooJin Sim
  • Patent number: 11901323
    Abstract: A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
  • Patent number: 11890702
    Abstract: The present invention provides a highly reliable solder joint, the solder joint including a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface in contact with the solder joint layer, wherein the Ni—P—Cu plating layer contains Ni as a main component and contains 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, the Ni—P—Cu plating layer has a microcrystalline layer at an interface with the solder joint layer, and the microcrystalline layer includes a phase containing microcrystals of a NiCuP ternary alloy, a phase containing microcrystals of (Ni,Cu)3P, and a phase containing microcrystals of Ni3P.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 6, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko Watanabe, Shunsuke Saito, Takeshi Yokoyama
  • Patent number: 11848161
    Abstract: Provided are a multilayer ceramic capacitor and a board having the same, the multilayer ceramic capacitor including: a capacitor body including an active region, which includes a plurality of dielectric layers and a plurality of internal electrodes alternately disposed with respective dielectric layers interposed therebetween, and covers formed on and under the active region, respectively. The multilayer ceramic capacitor further includes external electrodes disposed on the capacitor body so as to be connected to the internal electrodes. Among the internal electrodes, an internal electrode disposed adjacently to one of the covers has at least one cutaway portion within a portion of the internal electrode connected to the external electrode, and the cutaway portion is (at least partially) filled with a dielectric material.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Joon Woon Lee, Je Ik Moon
  • Patent number: 11842997
    Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: December 12, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Terry Alcorn, Daniel Namishia, Fabian Radulescu
  • Patent number: 11824007
    Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong
  • Patent number: 11819915
    Abstract: A bonding member that includes a resin body defining an airtight interior, and a bonding material enclosed in the interior of the resin body. The bonding material is a mixed powder that includes a plurality of particles of a first metal powder and a plurality of particles of a second metal powder. The second metal powder reacts with the first metal powder when melted to thereby produce an intermetallic compound. The resin body has a melting point higher than a softening point of the mixed powder.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Seitaro Washizuka
  • Patent number: 11824130
    Abstract: Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: November 21, 2023
    Assignee: Maxeon Solar Pte. Ltd.
    Inventors: Seung Bum Rim, Hung-Ming Wang, David Okawa, Lewis Abra
  • Patent number: 11817411
    Abstract: A semiconductor package including a first die, through electrodes penetrating the first die, a first pad on a top surface of the first die and coupled to a through electrode, a second die on the first die, a second pad on a bottom surface of the second die, a first connection terminal connecting the first pad to the second pad, and an insulating layer that fills a region between the first die and the second die and encloses the first connection terminal. The first connection terminal includes an intermetallic compound made of solder material and metallic material of the first and second pads. A concentration of the metallic material in the first connection terminal is substantially constant regardless of a distance from the first pad or the second pad.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: November 14, 2023
    Inventor: Young Lyong Kim
  • Patent number: 11792936
    Abstract: A printed circuit board includes a first chip component, a second chip component, and a printed wiring board. The first chip component and the second chip component each has a length L2 in the longitudinal direction. A relationship of 0.894?L2/L1?1.120 is satisfied, where L1 represents a length of the first opening in the longitudinal direction. A relationship of 0.894?L2/L4?1.120 is satisfied, where length L4 represents a length of the second opening in the longitudinal direction. A relationship of 0.183?LOA/LiA?50.309 is satisfied, where LiA represents a length of the first land in the longitudinal direction, and LOA represents a thickness of solder on an end surface of the first electrode. A relationship of 0.183?LOB/LiB?0.309 is satisfied, where LiB represents a length of the second land in the longitudinal direction, and LOB represents a thickness of solder on an end surface of the second electrode.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: October 17, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Noritake Tsuboi, Tomohisa Ishigami
  • Patent number: 11769768
    Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: September 26, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Terry Alcorn, Daniel Namishia, Fabian Radulescu
  • Patent number: 11756923
    Abstract: A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: September 12, 2023
    Assignee: Infineon Technologies AG
    Inventors: Marian Sebastian Broll, Barbara Eichinger, Alexander Herbrandt, Alparslan Takkac
  • Patent number: 11742461
    Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a second layer in contact with the second electrodes of the semiconductor element and a first layer located on a side opposite to the second electrodes, an average crystal grain size of crystals included in the second layer is larger than an average crystal grain size of crystals included in the first layer, and the first layer is spaced apart from the second electrodes of the semiconductor element.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: August 29, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Masanori Hiroki, Shigeo Hayashi, Kenji Nakashima, Toshiya Fukuhisa, Keimei Masamoto, Atsushi Yamada
  • Patent number: 11735512
    Abstract: A leadframe including a metal oxide layer on at least a portion of the leadframe are disclosed. More specifically, leadframes with a metal layer and a metal oxide layer formed on one or more leads before a tin finish plating layer is formed are described. The layers of metal and metal oxide between the one or more leads and the tin finish plating layer reduce the formation of tin whiskers, thus reducing the likelihood of shorting and improving the overall reliability of the package structure and device produced.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 22, 2023
    Assignee: STMicroelectronics International N.V.
    Inventor: Luca Maria Carlo Di Dio
  • Patent number: 11728259
    Abstract: A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having an aspect ratio of 2 to 25 in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: August 15, 2023
    Assignee: ABSOLICS INC.
    Inventors: Youngho Rho, Sungjin Kim, Jincheol Kim
  • Patent number: 11721685
    Abstract: A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: August 8, 2023
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Thomas Edward Dungan
  • Patent number: 11657978
    Abstract: A capacitor component includes a body including a dielectric layer, a first electrode and a second internal electrode, laminated in a first direction, opposing each other, and a first cover portion and a second cover portion, disposed on outermost surfaces of the first and second internal electrodes, each having a thickness of 25 ?m or less, a first electrode layer and a second electrode layer, respectively disposed on both external surfaces of the body in a second direction perpendicular to the first direction and respectively, and plating layers, respectively disposed on the first and second electrode layers. A metal oxide is disposed on a boundary between the first electrode layer and the plating layer and a boundary between the second electrode layer and the plating layer.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jang Yeol Lee, Ji Hong Jo, Yoo Jeong Lee, Myung Jun Park, Jong Ho Lee, Hye Young Choi, Jae Hyun Lee, Hyun Hee Gu
  • Patent number: 11652182
    Abstract: A five junction solar cell and its method of manufacture including an upper first solar subcell composed of a semiconductor material having a first band gap; a second solar subcell adjacent to said first solar subcell and composed of a semiconductor material having a second band gap smaller than the first band gap and being lattice matched with the upper first solar subcell; a third solar subcell adjacent to said second solar subcell and composed of a semiconductor material having a third band gap smaller than the second band gap and being lattice matched with the second solar subcell; a fourth solar subcell adjacent to said second solar subcell and composed of a semiconductor material having a fourth band gap smaller than the third band gap and being lattice matched with respect to the third solar subcell; a graded interlayer adjacent to the fourth solar subcell and having a fifth band gap greater than the fourth band gap; and a bottom solar subcell adjacent to the graded interlayer and being lattice mismatc
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 16, 2023
    Assignee: SolAero Technologies Corp.
    Inventor: Daniel Derkacs
  • Patent number: 11646161
    Abstract: A capacitor component includes a body including dielectric layers, first and second internal electrodes, laminated in a first direction, facing each other, and first and second cover portions, disposed on outermost portions of the first and second internal electrodes, and first and second external electrodes, respectively disposed on both external surfaces of the body in a second direction, perpendicular to the first direction, and respectively connected to the first and second internal electrodes. An indentation is disposed at at least one of boundaries between the first internal electrodes and the first external electrode or one of boundaries between the second internal electrodes and the second external electrode.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jang Yeol Lee, Ji Hong Jo, Yoo Jeong Lee, Myung Jun Park, Jong Ho Lee, Hye Young Choi, Jae Hyun Lee, Hyun Hee Gu
  • Patent number: 11637052
    Abstract: A semiconductor device, including a metal base plate having a front surface on which a disposition area is set apart from a central portion of the metal base plate, and a board placed over the disposition area with a solder therebetween. The solder has two edge portions of which one is closer than the other to the central portion of the metal base plate, said one being thicker than said the other.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: April 25, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoki Takizawa
  • Patent number: 11637050
    Abstract: The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 ?m and 130 ?m, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 25, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Anthony Chiu, Robert Charles Dry, Mihir Roy
  • Patent number: 11569156
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.
    Type: Grant
    Filed: February 23, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
  • Patent number: 11540397
    Abstract: A printed substrate forming method includes: a resin layer forming step of forming a resin layer with curable resin in a specific region that is a region other than a predetermined region of a base which is composed of an insulating layer and a conductor layer, the predetermined region of which being a region on which a solder resist is formed; and a wiring forming step of forming a wiring by discharging metal-containing liquid which contains metal fine particles onto a top surface of the resin layer, and firing the metal-containing liquid.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 27, 2022
    Assignee: FUJI CORPORATION
    Inventor: Ryojiro Tominaga
  • Patent number: 11532588
    Abstract: A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 ?m and less than or equal to 0.8 ?m, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 ?m and less than or equal to 50 ?m, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300° C., and a content of the solvent having a boiling point of higher than or equal to 300° C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: December 20, 2022
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Hideo Nakako, Kazuhiko Kurafuchi, Yoshinori Ejiri, Dai Ishikawa, Chie Sugama, Yuki Kawana
  • Patent number: 11515280
    Abstract: A mounting structure is used, which includes: a semiconductor element including an element electrode; a metal member; and a sintered body configured to bond the semiconductor element and the metal member is used, in which the sintered body contains a first metal and a second metal solid-dissolved in the first metal, the second metal is a metal having a diffusion coefficient in the first metal larger than a self-diffusion coefficient of the first metal, and a content ratio of the second metal relative to a total mass of the first metal and the second metal in the sintered body is equal to or lower than a solid solution limit of the second metal to the first metal.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 29, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kiyohiro Hine, Hidetoshi Kitaura, Akio Furusawa
  • Patent number: 11516907
    Abstract: A glass wiring board that can be kept from cracking by better preventing concentration of stresses in a glass plate on which a conductor layer including an electrolytic copper plating layer is provided, the wiring board includes: a glass plate; a first metal layer covering at least a part of the glass plate; and a second metal layer covering at least a part of the first metal layer, and the area of the first metal layer in contact with the second metal layer is smaller than the area of the second metal layer facing the first metal layer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: November 29, 2022
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Tetsuyuki Tsuchida
  • Patent number: 11502039
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Patent number: 11501980
    Abstract: A method for manufacturing a fin-integrated semiconductor module includes: clamping a fin-integrated heat-dissipation base using a level different jig while making the heat-dissipation base vary in height; and soldering a semiconductor assembly onto the heat-dissipation base. A semiconductor module includes a fin-integrated heat-dissipation base and a semiconductor assembly provided on the heat-dissipation base. A bending width of the heat-dissipation base is 200 ?m or less.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 15, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kazunaga Onishi, Takashi Masuzawa, Hiromichi Gohara
  • Patent number: 11488924
    Abstract: A semiconductor element bonding substrate according to the present invention includes an insulating plate, and a metal pattern bonded to a main surface of the insulating plate. A main surface of the metal pattern on an opposite side of the insulating plate includes a bonding region to which a semiconductor element is bonded by a solder. The metal pattern includes at least one concave part located in the main surface. The at least one concave part is located closer to an edge of the bonding region in relation to a center part of the bonding region in the bonding region.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: November 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Satoru Ishikawa
  • Patent number: 11469208
    Abstract: A semiconductor package structure includes a redistribution (RDL) layer, a first chip, at least one second chip, an encapsulant and a third chip. The redistribution layer has a first surface and a second surface opposite to each other. The first chip is over the first surface of the redistribution layer and electrically connected to the redistribution layer. The second chip is over the first surface of the redistribution layer. The second chip includes a plurality of through via structures. The encapsulant is over the first surface of the distribution layer, wherein the encapsulant surrounds the first chip and the second chip. The third chip is over the encapsulant and electrically connected to the first chip through the through via structures of the second chip and the redistribution layer.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Puu Jeng, Feng-Cheng Hsu, Shuo-Mao Chen
  • Patent number: 11462360
    Abstract: A multilayer electronic component includes a dielectric layer, and a first internal electrode and a second internal electrode alternately disposed with the dielectric layer interposed therebetween. The first internal electrode includes a first main portion and a first lead portion connecting the first main portion, and the second internal electrode includes a second main portion and a second lead portion connecting the second main portion, and the lead portion of the first internal electrode and a main portion of the second internal electrode are partially overlapped.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eun Gyu Lee, Jong Hoon Kim, Jong Ho Lee
  • Patent number: 11462456
    Abstract: A power-module substrate and a heat sink made of an aluminum-impregnated silicon carbide formed by impregnating aluminum in a porous body made of silicon carbide; where yield strength of a circuit layer is ?1 (MPa), a thickness of the circuit layer is t1 (mm), a bonding area of the circuit layer and a ceramic board is A1 (mm2), yield strength of a metal layer is ?2 (MPa), a thickness of the metal layer is t2 (mm), a bonding area of the metal layer and the ceramic board is A2 (mm2); the thickness t1 is formed to be between 0.1 mm and 3.0 mm (inclusive); the thickness t2 is formed to be between 0.15 mm and 5.0 mm (inclusive); the thickness t2 is formed larger than the thickness t1; and a ratio {(?2×t2×A2)/(?1×t1×A1)} is in a range between 1.5 and 15 (inclusive).
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 4, 2022
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Ryohei Yumoto, Sotaro Oi
  • Patent number: 11417634
    Abstract: A semiconductor module having a first metal wiring board, a second metal wiring board, a third metal wiring board, and a first semiconductor element and a second semiconductor element that each include an emitter electrode and a collector electrode. The second metal wiring board is disposed over a principal surface of the first metal wiring board with an insulation material therebetween. The third metal wiring board has a principal surface thereof facing the first metal wiring board. The first and second semiconductor elements are disposed to face directions opposite to each other. The collector electrodes of the first and second semiconductor elements respectively face the principal surfaces of the first and third metal wiring boards. The emitter electrodes of the first and second semiconductor elements are respectively connected to the principal surfaces of the third and second metal wiring boards.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 16, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshinari Ikeda
  • Patent number: 11417583
    Abstract: An LED module is disclosed. In an embodiment an LED module includes a thermally conductive substrate made of a multilayer ceramic, at least one LED on the substrate, passive SMD components arranged on the substrate, a passive component integrated in the substrate and a heat spreader configured to dissipate waste heat in horizontal and vertical directions.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 16, 2022
    Assignee: TDK ELECTRONICS AG
    Inventors: Thomas Feichtinger, Franz Rinner, Werner Rollett
  • Patent number: 11412616
    Abstract: A printed circuit board includes a first chip component, a second chip component, and a printed wiring board. The first chip component and the second chip component each has a length L2 in the longitudinal direction. A relationship of 0.894?L2/L1?1.120 is satisfied, where L1 represents a length of the first opening in the longitudinal direction. A relationship of 0.894?L2/L4?1.120 is satisfied, where length L4 represents a length of the second opening in the longitudinal direction. A relationship of 0.183?LOA/LiA?0.309 is satisfied, where LiA represents a length of the first land in the longitudinal direction, and LOA represents a thickness of solder on an end surface of the first electrode. A relationship of 0.183?LOB/LiB?0.309 is satisfied, where LiB represents a length of the second land in the longitudinal direction, and LOB represents a thickness of solder on an end surface of the second electrode.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 9, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Noritake Tsuboi, Tomohisa Ishigami
  • Patent number: 11404214
    Abstract: When internal electrode layers are viewed in a stacking direction, the internal electrode layers include an internal electrode main body portion defining an effective region, and an internal electrode lead-out portion that leads to a first or second end surface of a stacked body, and a length of the internal electrode lead-out portion in a width direction of the stacked body is less than or equal to about ½ of a length of the internal electrode main body portion. The internal electrode layer includes a first region having relatively high continuity of a conductive component defining the internal electrode layer, and a second region having relatively continuity of the conductive component. A central portion of the internal electrode main body portion is defined by the first region, and a portion of the internal electrode lead-out portion is defined by the second region.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 2, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hikaru Okuda
  • Patent number: 11398444
    Abstract: Electrical devices, semiconductor packages and methods of forming the same are provided. One of the electrical devices includes a substrate, a conductive pad, a conductive pillar and a solder region. The substrate has a surface. The conductive pad is disposed on the surface of the substrate. The conductive pillar is disposed on and electrically connected to the conductive pad, wherein a top surface of the conductive pillar is inclined with respect to the surface of the substrate. The solder region is disposed on the top surface of the conductive pillar.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
  • Patent number: 11387162
    Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 12, 2022
    Assignee: Littelfuse, Inc.
    Inventors: Gi-Young Jeun, Kang Rim Choi
  • Patent number: 11309235
    Abstract: A semiconductor module includes a printed wiring board and a semiconductor device. The printed wiring board includes a plurality of lands bonded to the semiconductor device via solder, and a solder resist. The plurality of lands includes a first land positioned in a vicinity of an outer edge of the insulating substrate and including a first edge portion, a second edge portion, a third edge portion, and a fourth edge portion. The first edge portion and the second edge portion are configured not to overlap with the solder resist and the third edge portion and the fourth edge portion are configured to overlap with the solder resist.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 19, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hideto Takahashi
  • Patent number: 11233024
    Abstract: An apparatus comprising a substrate having conductive traces and associated integral terminal pads on a surface thereof, the terminal pads having an irregular surface topography formed in a thickness of a single material of the conductive traces and integral terminal pads. Solder balls may be bonded to the terminal pads, and one or more microelectronic components operably coupled to conductive traces of the substrate on a side thereof opposite the terminal pads. Methods of fabricating terminal pads on a substrate, and electronic systems including substrates having such terminal pads are also disclosed.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: January 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Travis M. Jensen
  • Patent number: 11177406
    Abstract: A solar cell and a solar cell module are disclosed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate and first and second electrodes on the semiconductor substrate, the first and second electrodes being alternately positioned in a first direction and extended in a second direction intersecting the first direction, a first conductive line extended in the first direction to intersect the first and second electrodes, connected to the first electrode by a first conductive layer, and insulated from the second electrode by an insulating layer, and a second conductive line positioned in parallel with the first conductive line, connected to the second electrode by the first conductive layer, and insulated from the first electrode by the insulating layer.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 16, 2021
    Assignee: LG ELECTRONICS INC.
    Inventor: Chunghyun Lim
  • Patent number: 11152318
    Abstract: A semiconductor device of the present invention includes a first main electrode and a second main electrode respectively disposed on a first main surface and a second main surface of a semiconductor substrate, a protective film disposed on an edge part of the first main electrode; and a first metal film disposed in a region enclosed by the protective film on the first main electrode. The first metal film has a film thickness at a central portion larger than that at a part in contact with the protective film, and has irregularities on a surface thereof.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: October 19, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tatsunori Yanagimoto, Kaori Sato, Masao Kikuchi
  • Patent number: 11145615
    Abstract: A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: October 12, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko Watanabe, Shunsuke Saito, Yoshitaka Nishimura, Fumihiko Momose
  • Patent number: 10930612
    Abstract: A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 ?m and less than or equal to 0.8 ?m, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 ?m and less than or equal to 50 ?m, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300° C., and a content of the solvent having a boiling point of higher than or equal to 300° C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 23, 2021
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Hideo Nakako, Kazuhiko Kurafuchi, Yoshinori Ejiri, Dai Ishikawa, Chie Sugama, Yuki Kawana
  • Patent number: 10867948
    Abstract: A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-woo Kim, Woon-bae Kim, Bo-in Noh, Go-woon Seong, Ji-yong Park
  • Patent number: 10854804
    Abstract: A light-emitting component includes a light-emitting chip and a housing including a plastic body and a reflector, the reflector includes an electrically conductive layer, the light-emitting chip includes a top side and an underside, the underside of the light-emitting chip is arranged on the plastic body, an electrical terminal on the top side of the light-emitting chip electrically conductively connects to the reflector by a bond wire, the underside of the light-emitting chip and the reflector are electrically insulated from one another, a conduction region is provided within the plastic body, thermal conductivity of the conduction region is greater than thermal conductivity of the plastic body, the conduction region adjoins the underside of the light-emitting chip, and the conduction region extends from the side of the plastic body facing the light-emitting chip as far as the side of the plastic body facing away from the light-emitting chip.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: December 1, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Martin Haushalter, Frank Singer, Thomas Schwarz, Andreas Ploessl
  • Patent number: 10818565
    Abstract: A circuit board includes: a ceramic substrate that has a first surface and a second surface; a first metal part that has a first metal plate joined to the first surface and a protrusion projecting from a front surface of the first metal plate; and a second metal part that has a second metal plate joined to the second surface. When the ceramic substrate is equally divided into first to third sections along a longer side direction, V1, V2, V3, V4, V5, and V6 are numbers satisfying formula V4/V1+V6/V3?2(V5/V2), 0.5?V4/V1?2, 0.5?V5/V2?2, and 0.5?V6/V3?2.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: October 27, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Hiromasa Kato, Takashi Sano
  • Patent number: 10727145
    Abstract: A semiconductor device including: an insulating substrate having a conductor layer on the upper face and the lower face and a semiconductor element mounted on the upper conductor layer; a base plate bonded to the lower conductor layer; a case member surrounding the insulating substrate and bonded to the surface of the base plate to which the conductor layer bonded to the lower face; a first filler being a silicone composition filled in a region surrounded by the base plate and the case member; and a second filler being injected into a region below the first filler and surrounding a peripheral edge portion of the insulating substrate, whose height from the base plate is higher than the upper face and is lower than a bonding face between the semiconductor element and the upper conductor layer.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Harada, Kozo Harada, Hiroki Shiota, Yoshihiro Yamaguchi, Koji Yamada
  • Patent number: 10699994
    Abstract: In a semiconductor device, protective films are formed on facing side surfaces of a plurality of circuit patterns and a plating process or the like is not performed on parts aside from the side surfaces where the protective films are formed. This means that when semiconductor elements and contact elements are directly bonded via solder onto the plurality of circuit patterns, a drop-in wettability of the plurality of circuit patterns for the solder is avoided.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 30, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenshi Kai, Rikihiro Maruyama
  • Patent number: 10629537
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu