Solder Composition Patents (Class 257/772)
  • Patent number: 11515280
    Abstract: A mounting structure is used, which includes: a semiconductor element including an element electrode; a metal member; and a sintered body configured to bond the semiconductor element and the metal member is used, in which the sintered body contains a first metal and a second metal solid-dissolved in the first metal, the second metal is a metal having a diffusion coefficient in the first metal larger than a self-diffusion coefficient of the first metal, and a content ratio of the second metal relative to a total mass of the first metal and the second metal in the sintered body is equal to or lower than a solid solution limit of the second metal to the first metal.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 29, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kiyohiro Hine, Hidetoshi Kitaura, Akio Furusawa
  • Patent number: 11516907
    Abstract: A glass wiring board that can be kept from cracking by better preventing concentration of stresses in a glass plate on which a conductor layer including an electrolytic copper plating layer is provided, the wiring board includes: a glass plate; a first metal layer covering at least a part of the glass plate; and a second metal layer covering at least a part of the first metal layer, and the area of the first metal layer in contact with the second metal layer is smaller than the area of the second metal layer facing the first metal layer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: November 29, 2022
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Tetsuyuki Tsuchida
  • Patent number: 11501980
    Abstract: A method for manufacturing a fin-integrated semiconductor module includes: clamping a fin-integrated heat-dissipation base using a level different jig while making the heat-dissipation base vary in height; and soldering a semiconductor assembly onto the heat-dissipation base. A semiconductor module includes a fin-integrated heat-dissipation base and a semiconductor assembly provided on the heat-dissipation base. A bending width of the heat-dissipation base is 200 ?m or less.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 15, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kazunaga Onishi, Takashi Masuzawa, Hiromichi Gohara
  • Patent number: 11502039
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Patent number: 11488924
    Abstract: A semiconductor element bonding substrate according to the present invention includes an insulating plate, and a metal pattern bonded to a main surface of the insulating plate. A main surface of the metal pattern on an opposite side of the insulating plate includes a bonding region to which a semiconductor element is bonded by a solder. The metal pattern includes at least one concave part located in the main surface. The at least one concave part is located closer to an edge of the bonding region in relation to a center part of the bonding region in the bonding region.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: November 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Satoru Ishikawa
  • Patent number: 11469208
    Abstract: A semiconductor package structure includes a redistribution (RDL) layer, a first chip, at least one second chip, an encapsulant and a third chip. The redistribution layer has a first surface and a second surface opposite to each other. The first chip is over the first surface of the redistribution layer and electrically connected to the redistribution layer. The second chip is over the first surface of the redistribution layer. The second chip includes a plurality of through via structures. The encapsulant is over the first surface of the distribution layer, wherein the encapsulant surrounds the first chip and the second chip. The third chip is over the encapsulant and electrically connected to the first chip through the through via structures of the second chip and the redistribution layer.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Puu Jeng, Feng-Cheng Hsu, Shuo-Mao Chen
  • Patent number: 11462456
    Abstract: A power-module substrate and a heat sink made of an aluminum-impregnated silicon carbide formed by impregnating aluminum in a porous body made of silicon carbide; where yield strength of a circuit layer is ?1 (MPa), a thickness of the circuit layer is t1 (mm), a bonding area of the circuit layer and a ceramic board is A1 (mm2), yield strength of a metal layer is ?2 (MPa), a thickness of the metal layer is t2 (mm), a bonding area of the metal layer and the ceramic board is A2 (mm2); the thickness t1 is formed to be between 0.1 mm and 3.0 mm (inclusive); the thickness t2 is formed to be between 0.15 mm and 5.0 mm (inclusive); the thickness t2 is formed larger than the thickness t1; and a ratio {(?2×t2×A2)/(?1×t1×A1)} is in a range between 1.5 and 15 (inclusive).
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 4, 2022
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Ryohei Yumoto, Sotaro Oi
  • Patent number: 11462360
    Abstract: A multilayer electronic component includes a dielectric layer, and a first internal electrode and a second internal electrode alternately disposed with the dielectric layer interposed therebetween. The first internal electrode includes a first main portion and a first lead portion connecting the first main portion, and the second internal electrode includes a second main portion and a second lead portion connecting the second main portion, and the lead portion of the first internal electrode and a main portion of the second internal electrode are partially overlapped.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eun Gyu Lee, Jong Hoon Kim, Jong Ho Lee
  • Patent number: 11417634
    Abstract: A semiconductor module having a first metal wiring board, a second metal wiring board, a third metal wiring board, and a first semiconductor element and a second semiconductor element that each include an emitter electrode and a collector electrode. The second metal wiring board is disposed over a principal surface of the first metal wiring board with an insulation material therebetween. The third metal wiring board has a principal surface thereof facing the first metal wiring board. The first and second semiconductor elements are disposed to face directions opposite to each other. The collector electrodes of the first and second semiconductor elements respectively face the principal surfaces of the first and third metal wiring boards. The emitter electrodes of the first and second semiconductor elements are respectively connected to the principal surfaces of the third and second metal wiring boards.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 16, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshinari Ikeda
  • Patent number: 11417583
    Abstract: An LED module is disclosed. In an embodiment an LED module includes a thermally conductive substrate made of a multilayer ceramic, at least one LED on the substrate, passive SMD components arranged on the substrate, a passive component integrated in the substrate and a heat spreader configured to dissipate waste heat in horizontal and vertical directions.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 16, 2022
    Assignee: TDK ELECTRONICS AG
    Inventors: Thomas Feichtinger, Franz Rinner, Werner Rollett
  • Patent number: 11412616
    Abstract: A printed circuit board includes a first chip component, a second chip component, and a printed wiring board. The first chip component and the second chip component each has a length L2 in the longitudinal direction. A relationship of 0.894?L2/L1?1.120 is satisfied, where L1 represents a length of the first opening in the longitudinal direction. A relationship of 0.894?L2/L4?1.120 is satisfied, where length L4 represents a length of the second opening in the longitudinal direction. A relationship of 0.183?LOA/LiA?0.309 is satisfied, where LiA represents a length of the first land in the longitudinal direction, and LOA represents a thickness of solder on an end surface of the first electrode. A relationship of 0.183?LOB/LiB?0.309 is satisfied, where LiB represents a length of the second land in the longitudinal direction, and LOB represents a thickness of solder on an end surface of the second electrode.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 9, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Noritake Tsuboi, Tomohisa Ishigami
  • Patent number: 11404214
    Abstract: When internal electrode layers are viewed in a stacking direction, the internal electrode layers include an internal electrode main body portion defining an effective region, and an internal electrode lead-out portion that leads to a first or second end surface of a stacked body, and a length of the internal electrode lead-out portion in a width direction of the stacked body is less than or equal to about ½ of a length of the internal electrode main body portion. The internal electrode layer includes a first region having relatively high continuity of a conductive component defining the internal electrode layer, and a second region having relatively continuity of the conductive component. A central portion of the internal electrode main body portion is defined by the first region, and a portion of the internal electrode lead-out portion is defined by the second region.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 2, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hikaru Okuda
  • Patent number: 11398444
    Abstract: Electrical devices, semiconductor packages and methods of forming the same are provided. One of the electrical devices includes a substrate, a conductive pad, a conductive pillar and a solder region. The substrate has a surface. The conductive pad is disposed on the surface of the substrate. The conductive pillar is disposed on and electrically connected to the conductive pad, wherein a top surface of the conductive pillar is inclined with respect to the surface of the substrate. The solder region is disposed on the top surface of the conductive pillar.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
  • Patent number: 11387162
    Abstract: A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 12, 2022
    Assignee: Littelfuse, Inc.
    Inventors: Gi-Young Jeun, Kang Rim Choi
  • Patent number: 11309235
    Abstract: A semiconductor module includes a printed wiring board and a semiconductor device. The printed wiring board includes a plurality of lands bonded to the semiconductor device via solder, and a solder resist. The plurality of lands includes a first land positioned in a vicinity of an outer edge of the insulating substrate and including a first edge portion, a second edge portion, a third edge portion, and a fourth edge portion. The first edge portion and the second edge portion are configured not to overlap with the solder resist and the third edge portion and the fourth edge portion are configured to overlap with the solder resist.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 19, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hideto Takahashi
  • Patent number: 11233024
    Abstract: An apparatus comprising a substrate having conductive traces and associated integral terminal pads on a surface thereof, the terminal pads having an irregular surface topography formed in a thickness of a single material of the conductive traces and integral terminal pads. Solder balls may be bonded to the terminal pads, and one or more microelectronic components operably coupled to conductive traces of the substrate on a side thereof opposite the terminal pads. Methods of fabricating terminal pads on a substrate, and electronic systems including substrates having such terminal pads are also disclosed.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: January 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Travis M. Jensen
  • Patent number: 11177406
    Abstract: A solar cell and a solar cell module are disclosed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate and first and second electrodes on the semiconductor substrate, the first and second electrodes being alternately positioned in a first direction and extended in a second direction intersecting the first direction, a first conductive line extended in the first direction to intersect the first and second electrodes, connected to the first electrode by a first conductive layer, and insulated from the second electrode by an insulating layer, and a second conductive line positioned in parallel with the first conductive line, connected to the second electrode by the first conductive layer, and insulated from the first electrode by the insulating layer.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 16, 2021
    Assignee: LG ELECTRONICS INC.
    Inventor: Chunghyun Lim
  • Patent number: 11152318
    Abstract: A semiconductor device of the present invention includes a first main electrode and a second main electrode respectively disposed on a first main surface and a second main surface of a semiconductor substrate, a protective film disposed on an edge part of the first main electrode; and a first metal film disposed in a region enclosed by the protective film on the first main electrode. The first metal film has a film thickness at a central portion larger than that at a part in contact with the protective film, and has irregularities on a surface thereof.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: October 19, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tatsunori Yanagimoto, Kaori Sato, Masao Kikuchi
  • Patent number: 11145615
    Abstract: A lead-free solder has a heat resistance temperature which is high and a thermal conductive property which is not changed in a high temperature range. A semiconductor device includes a solder material containing more than 5.0% by mass and 10.0% by mass or less of Sb and 2.0 to 4.0% by mass of Ag, and the remainder consisting of Sn and inevitable impurities. A bonding layer including the solder material, is formed between a semiconductor element and a substrate electrode or a lead frame.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: October 12, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko Watanabe, Shunsuke Saito, Yoshitaka Nishimura, Fumihiko Momose
  • Patent number: 10930612
    Abstract: A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 ?m and less than or equal to 0.8 ?m, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 ?m and less than or equal to 50 ?m, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300° C., and a content of the solvent having a boiling point of higher than or equal to 300° C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 23, 2021
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Hideo Nakako, Kazuhiko Kurafuchi, Yoshinori Ejiri, Dai Ishikawa, Chie Sugama, Yuki Kawana
  • Patent number: 10867948
    Abstract: A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-woo Kim, Woon-bae Kim, Bo-in Noh, Go-woon Seong, Ji-yong Park
  • Patent number: 10854804
    Abstract: A light-emitting component includes a light-emitting chip and a housing including a plastic body and a reflector, the reflector includes an electrically conductive layer, the light-emitting chip includes a top side and an underside, the underside of the light-emitting chip is arranged on the plastic body, an electrical terminal on the top side of the light-emitting chip electrically conductively connects to the reflector by a bond wire, the underside of the light-emitting chip and the reflector are electrically insulated from one another, a conduction region is provided within the plastic body, thermal conductivity of the conduction region is greater than thermal conductivity of the plastic body, the conduction region adjoins the underside of the light-emitting chip, and the conduction region extends from the side of the plastic body facing the light-emitting chip as far as the side of the plastic body facing away from the light-emitting chip.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: December 1, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Martin Haushalter, Frank Singer, Thomas Schwarz, Andreas Ploessl
  • Patent number: 10818565
    Abstract: A circuit board includes: a ceramic substrate that has a first surface and a second surface; a first metal part that has a first metal plate joined to the first surface and a protrusion projecting from a front surface of the first metal plate; and a second metal part that has a second metal plate joined to the second surface. When the ceramic substrate is equally divided into first to third sections along a longer side direction, V1, V2, V3, V4, V5, and V6 are numbers satisfying formula V4/V1+V6/V3?2(V5/V2), 0.5?V4/V1?2, 0.5?V5/V2?2, and 0.5?V6/V3?2.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: October 27, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Hiromasa Kato, Takashi Sano
  • Patent number: 10727145
    Abstract: A semiconductor device including: an insulating substrate having a conductor layer on the upper face and the lower face and a semiconductor element mounted on the upper conductor layer; a base plate bonded to the lower conductor layer; a case member surrounding the insulating substrate and bonded to the surface of the base plate to which the conductor layer bonded to the lower face; a first filler being a silicone composition filled in a region surrounded by the base plate and the case member; and a second filler being injected into a region below the first filler and surrounding a peripheral edge portion of the insulating substrate, whose height from the base plate is higher than the upper face and is lower than a bonding face between the semiconductor element and the upper conductor layer.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Harada, Kozo Harada, Hiroki Shiota, Yoshihiro Yamaguchi, Koji Yamada
  • Patent number: 10699994
    Abstract: In a semiconductor device, protective films are formed on facing side surfaces of a plurality of circuit patterns and a plating process or the like is not performed on parts aside from the side surfaces where the protective films are formed. This means that when semiconductor elements and contact elements are directly bonded via solder onto the plurality of circuit patterns, a drop-in wettability of the plurality of circuit patterns for the solder is avoided.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 30, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenshi Kai, Rikihiro Maruyama
  • Patent number: 10629537
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10504868
    Abstract: The present invention suppresses fracture at an interface between different materials, and provides a solder joining which includes: a solder joining layer 10 having a melted solder material, containing Sb at more than 5.0% by mass and 10.0% by mass or less, Ag at 2.0 to 4.0% by mass, Ni at more than 0 and 1.0% by mass or less, and a balance made up of Sn and inevitable impurities; and joining members 11 and 123 at least one of which is a Cu or Cu-alloy member 123, in which the solder joining layer includes a first structure 1 containing (Cu, Ni)6(Sn, Sb)5 and a second structure 2 containing (Ni, Cu)3(Sn, Sb)X (in the formula, X is 1, 2, or 4) at an interface with the Cu or Cu-alloy member 123, and an electronic device and a semiconductor device including the solder joining.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: December 10, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko Watanabe, Shunsuke Saito, Yoshihiro Kodaira
  • Patent number: 10483232
    Abstract: A method for fabricating bump structures on chips with a panel type process is provided. First, a panel type substrate is provided. Semiconductor chips are fixed on the panel type substrate. Each semiconductor chip includes metal pads and a passivation layer exposing the metal pads. At least an electroless plating process is performed to form under bump metallurgy structures on the metal pads. The method simplifies the processes of forming electrical connections for semiconductor chips. The panel type process can effectively increase the yield, and reduce the manufacturing cost.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 19, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping Hsu, Che-Wei Hsu, Tung-Yao Kuo
  • Patent number: 10340240
    Abstract: Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 10163835
    Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Yi-Li Hsiao, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 10049897
    Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 10043731
    Abstract: A method for high temperature bonding of substrates may include providing a top substrate and a bottom substrate, and positioning an insert between the substrates to form a assembly. The insert may be shaped to hold at least an amount of Sn having a low melting temperature and a gap shaped to hold at least a plurality of metal particles having a high melting temperature greater than the low melting temperature. The assembly may be heated to below the low melting temperature and held for a first period of time. The assembly may further be heated to approximately the low melting temperature and held for a period of time at a temperature equal to or greater than the low melting temperature such that the amount of Sn and the amount of metal particles form one or more intermetallic bonds. The assembly may be cooled to create a bonded assembly.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: August 7, 2018
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Masao Noguchi
  • Patent number: 10032708
    Abstract: A circuit board and a smart card module and a smart card employing the circuit board are provided. The circuit board includes a substrate and a pad region provided on the substrate. The pad region is configured for mounting an electronic component, and comprises a plurality of pads spaced from each other and traces connected to their respective pads. At least one of the pads has an arc edge. In the present invention, the distance between the pads is easy to be controlled during fabrication, and the stability of the adhesion between the chip and pad region is enhanced.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: July 24, 2018
    Assignee: Johnson Electric S.A.
    Inventors: Dominic John Ward, Rong Zhang, Yi Qi Zhang
  • Patent number: 9893043
    Abstract: Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a chip package includes: stacking a second chip on a first chip, wherein a first interconnect including a support structure and a bonding structure is disposed between the first chip and the second chip; bonding the first chip and the second chip via a thermal process applied to the bonding structure of the first interconnect; stacking a third chip on the second chip, wherein a second interconnect including a support structure and a bonding structure is disposed between the second chip and the third chip; bonding the second chip and the third chip via the thermal process applied to the bonding structure of the second interconnect; and reflowing the bond between the first and second chips and simultaneously reflowing the bond between the second and third chips.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Liang Chen, Yu-Chih Liu, Kuan-Lin Ho, Wei-Ting Lin, Shih-Yen Lin
  • Patent number: 9870955
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a dummy shielding layer over the semiconductor substrate and the gate stack. The method also includes forming source and drain features near the gate stack after the dummy shielding layer is formed. The method further includes removing the dummy shielding layer after the source and drain features are formed such that substantially no dummy shielding layer remains on the source and drain features.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Yi-Jen Chen, Yung-Jung Chang
  • Patent number: 9831151
    Abstract: A thermal interface includes a first thermal interface material (TIM) layer and a lid disposed on the first TIM layer. A second TIM layer is disposed on a surface of the lid opposite the first TIM layer. The second TIM layer is from about 75% to about 25% as wide as a width of the lid in at least one direction. A heat sink disposed on a surface of the second TIM layer opposite the lid.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: November 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Mark D. Schultz
  • Patent number: 9818687
    Abstract: A semiconductor module includes an insulated circuit board that includes an insulating substrate, a first conductive plate arranged on a first principal surface of the insulating substrate and within the outer edges of the insulating substrate, and a second conductive plate arranged within the outer edges of the insulating substrate on a second principal surface of the insulating substrate that faces the first principal surface. Furthermore, boundary edges between the first principal surface of the insulating substrate and the side faces of the first conductive plate are covered by an ion gel that contains an ionic liquid.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoyuki Kanai
  • Patent number: 9607862
    Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 9595507
    Abstract: According to one embodiment, a semiconductor device includes a laminate including a plurality of semiconductor chips and having a first width, at least part of the semiconductor chips including an electrode extending through the semiconductor chip, the semiconductor chips being stacked and connected to each other via the electrode; a silicon substrate provided on a first surface of the laminate and having a second width larger than the first width; a wiring layer provided on a second surface of the laminate; and a resin provided around the laminate.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: March 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoichiro Kurita
  • Patent number: 9519166
    Abstract: This disclosure provides a circuit substrate, a display panel and a display device for solving the problem of a relatively large electrode pitch of the circuit substrate in the prior art while reducing the production cost. Wherein the circuit substrate comprises a substrate, a plurality of first electrodes arranged on the substrate, and insulating convex structures arranged between the substrate and the first electrodes, the convex structure comprising a top face and a bottom face, wherein the top face contacts with the first electrode, and the bottom face contacts with the substrate.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: December 13, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Heecheol Kim, Youngsuk Song, Seongyeol Yoo, Seungjin Choi
  • Patent number: 9490232
    Abstract: An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: November 8, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Shimizu, Seiki Sakuyama
  • Patent number: 9324905
    Abstract: A wafer-level process for manufacturing solid state lighting (“SSL”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. The preformed metal substrate can be bonded to the light emitting structure via a metal-metal bond, such as a copper-copper bond, or with an inter-metallic compound bond.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: April 26, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Vladimir Odnoblyudov
  • Patent number: 9299983
    Abstract: The invention discloses a novel method to prepare the Ni(Sn, Sb)3 skutterudite compound. Skutterudite compounds are thermoelectric materials, which can transform heat into electric energy. Besides, the Ni(Sn, Sb)3 compound is also an anode material of Li ion battery. The solid state diffusion method is used to prepare the Ni(Sn1-x, Sbx)3 compound. Compared to traditional physical or chemical processes, the method disclosed in the invention is simpler and operates at a lower temperature. By the method according to the invention, the composition of the Ni(Sn, Sb)3 compound can be adjusted to fulfill variety requirements for different applications. It is noteworthy that the invention can prepare ternary compounds. In comparison with the frequently used binary compounds such as Ni3Sn4 or Cu6Sn5, the invention can produce materials with better performance.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 29, 2016
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Chih-chi Chen, Yue-ting Chen
  • Patent number: 9293416
    Abstract: A functional material includes at least two kinds of particles selected from the group consisting of first metal composite particles, second metal composite particles and third metal composite particles. The first metal composite particles, the second metal composite particles and the third metal composite particles each contain two or more kinds of metal components. The melting point T1(° C.) of the first metal composite particles, the melting point T2(° C.) of the second metal composite particles and the melting point T3(° C.) of the third metal composite particles satisfy a relationship of T1>T2>T3.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 22, 2016
    Assignee: NAPRA CO., LTD.
    Inventors: Shigenobu Sekine, Yurina Sekine
  • Patent number: 9293433
    Abstract: A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: March 22, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yoshihiro Machida
  • Patent number: 9281127
    Abstract: In a method for manufacturing an electronic component, when conductive paste used to form outer electrodes is applied to a component body, a side surface of the component body is subjected to an affinity-reducing process to reduce an affinity for solvent, and then an end surface of the component body is dipped into the conductive paste. Accordingly, spreading of the conductive paste stops at ridge portions of the component body, and the conductive paste is applied to a large thickness. After that, the end surface of the component body is dipped deeper into the conductive paste. Also in this step, the affinity-reducing process prevents upward spreading of the conductive paste along the side surface.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 8, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Toshiki Miyazaki
  • Patent number: 9245687
    Abstract: There is provided a multilayer ceramic capacitor, including a ceramic body, a plurality of first and second internal electrodes, and first and second external electrodes, wherein the first and second external electrodes include first and second internal layers including first and second internal head portions and first and second internal bands formed on both main surfaces of the ceramic body, and first and second external layers including first and second external head portions and first and second external bands formed on the first and second internal bands and having a distance shorter than a distance of the first and second internal bands, the first and second external layers having viscosity higher than that of the first and second internal layers.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: January 26, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyun Tae Kim, Kyu Ree Kim, Mi Jeong Chang
  • Patent number: 9227259
    Abstract: Thickening a contact grid of a solar cell for increased efficiency. A mold containing soldering material is heated. The mold is aligned with the contact grid such that the soldering material is in physical contact with the contact grid. The mold is re-heated, transferring the solder material from the mold to the contact grid to create a thickened contact grid.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: January 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Haag, Ruediger Kellmann, Markus Schmidt
  • Patent number: 9196577
    Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: November 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Höglauer, Jürgen Schredl, Xaver Schlögel, Klaus Schiess
  • Patent number: 9035459
    Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Raschid J. Bezama, Harry D. Cox, Timothy H. Daubenspeck, Krystyna W. Semkow, Timothy D. Sullivan