Abstract: The present invention suppresses fracture at an interface between different materials, and provides a solder joining which includes: a solder joining layer 10 having a melted solder material, containing Sb at more than 5.0% by mass and 10.0% by mass or less, Ag at 2.0 to 4.0% by mass, Ni at more than 0 and 1.0% by mass or less, and a balance made up of Sn and inevitable impurities; and joining members 11 and 123 at least one of which is a Cu or Cu-alloy member 123, in which the solder joining layer includes a first structure 1 containing (Cu, Ni)6(Sn, Sb)5 and a second structure 2 containing (Ni, Cu)3(Sn, Sb)X (in the formula, X is 1, 2, or 4) at an interface with the Cu or Cu-alloy member 123, and an electronic device and a semiconductor device including the solder joining.

Abstract: A method for fabricating bump structures on chips with a panel type process is provided. First, a panel type substrate is provided. Semiconductor chips are fixed on the panel type substrate. Each semiconductor chip includes metal pads and a passivation layer exposing the metal pads. At least an electroless plating process is performed to form under bump metallurgy structures on the metal pads. The method simplifies the processes of forming electrical connections for semiconductor chips. The panel type process can effectively increase the yield, and reduce the manufacturing cost.

Abstract: Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

Abstract: A method for high temperature bonding of substrates may include providing a top substrate and a bottom substrate, and positioning an insert between the substrates to form a assembly. The insert may be shaped to hold at least an amount of Sn having a low melting temperature and a gap shaped to hold at least a plurality of metal particles having a high melting temperature greater than the low melting temperature. The assembly may be heated to below the low melting temperature and held for a first period of time. The assembly may further be heated to approximately the low melting temperature and held for a period of time at a temperature equal to or greater than the low melting temperature such that the amount of Sn and the amount of metal particles form one or more intermetallic bonds. The assembly may be cooled to create a bonded assembly.

Abstract: A circuit board and a smart card module and a smart card employing the circuit board are provided. The circuit board includes a substrate and a pad region provided on the substrate. The pad region is configured for mounting an electronic component, and comprises a plurality of pads spaced from each other and traces connected to their respective pads. At least one of the pads has an arc edge. In the present invention, the distance between the pads is easy to be controlled during fabrication, and the stability of the adhesion between the chip and pad region is enhanced.

Abstract: Chip packages and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a chip package includes: stacking a second chip on a first chip, wherein a first interconnect including a support structure and a bonding structure is disposed between the first chip and the second chip; bonding the first chip and the second chip via a thermal process applied to the bonding structure of the first interconnect; stacking a third chip on the second chip, wherein a second interconnect including a support structure and a bonding structure is disposed between the second chip and the third chip; bonding the second chip and the third chip via the thermal process applied to the bonding structure of the second interconnect; and reflowing the bond between the first and second chips and simultaneously reflowing the bond between the second and third chips.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a dummy shielding layer over the semiconductor substrate and the gate stack. The method also includes forming source and drain features near the gate stack after the dummy shielding layer is formed. The method further includes removing the dummy shielding layer after the source and drain features are formed such that substantially no dummy shielding layer remains on the source and drain features.

Abstract: A thermal interface includes a first thermal interface material (TIM) layer and a lid disposed on the first TIM layer. A second TIM layer is disposed on a surface of the lid opposite the first TIM layer. The second TIM layer is from about 75% to about 25% as wide as a width of the lid in at least one direction. A heat sink disposed on a surface of the second TIM layer opposite the lid.

Abstract: A semiconductor module includes an insulated circuit board that includes an insulating substrate, a first conductive plate arranged on a first principal surface of the insulating substrate and within the outer edges of the insulating substrate, and a second conductive plate arranged within the outer edges of the insulating substrate on a second principal surface of the insulating substrate that faces the first principal surface. Furthermore, boundary edges between the first principal surface of the insulating substrate and the side faces of the first conductive plate are covered by an ion gel that contains an ionic liquid.

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

Abstract: According to one embodiment, a semiconductor device includes a laminate including a plurality of semiconductor chips and having a first width, at least part of the semiconductor chips including an electrode extending through the semiconductor chip, the semiconductor chips being stacked and connected to each other via the electrode; a silicon substrate provided on a first surface of the laminate and having a second width larger than the first width; a wiring layer provided on a second surface of the laminate; and a resin provided around the laminate.

Abstract: This disclosure provides a circuit substrate, a display panel and a display device for solving the problem of a relatively large electrode pitch of the circuit substrate in the prior art while reducing the production cost. Wherein the circuit substrate comprises a substrate, a plurality of first electrodes arranged on the substrate, and insulating convex structures arranged between the substrate and the first electrodes, the convex structure comprising a top face and a bottom face, wherein the top face contacts with the first electrode, and the bottom face contacts with the substrate.

Abstract: An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Abstract: A wafer-level process for manufacturing solid state lighting (“SSL”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. The preformed metal substrate can be bonded to the light emitting structure via a metal-metal bond, such as a copper-copper bond, or with an inter-metallic compound bond.

Abstract: The invention discloses a novel method to prepare the Ni(Sn, Sb)3 skutterudite compound. Skutterudite compounds are thermoelectric materials, which can transform heat into electric energy. Besides, the Ni(Sn, Sb)3 compound is also an anode material of Li ion battery. The solid state diffusion method is used to prepare the Ni(Sn1-x, Sbx)3 compound. Compared to traditional physical or chemical processes, the method disclosed in the invention is simpler and operates at a lower temperature. By the method according to the invention, the composition of the Ni(Sn, Sb)3 compound can be adjusted to fulfill variety requirements for different applications. It is noteworthy that the invention can prepare ternary compounds. In comparison with the frequently used binary compounds such as Ni3Sn4 or Cu6Sn5, the invention can produce materials with better performance.

Abstract: A functional material includes at least two kinds of particles selected from the group consisting of first metal composite particles, second metal composite particles and third metal composite particles. The first metal composite particles, the second metal composite particles and the third metal composite particles each contain two or more kinds of metal components. The melting point T1(° C.) of the first metal composite particles, the melting point T2(° C.) of the second metal composite particles and the melting point T3(° C.) of the third metal composite particles satisfy a relationship of T1>T2>T3.

Abstract: A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal.

Abstract: In a method for manufacturing an electronic component, when conductive paste used to form outer electrodes is applied to a component body, a side surface of the component body is subjected to an affinity-reducing process to reduce an affinity for solvent, and then an end surface of the component body is dipped into the conductive paste. Accordingly, spreading of the conductive paste stops at ridge portions of the component body, and the conductive paste is applied to a large thickness. After that, the end surface of the component body is dipped deeper into the conductive paste. Also in this step, the affinity-reducing process prevents upward spreading of the conductive paste along the side surface.

Abstract: There is provided a multilayer ceramic capacitor, including a ceramic body, a plurality of first and second internal electrodes, and first and second external electrodes, wherein the first and second external electrodes include first and second internal layers including first and second internal head portions and first and second internal bands formed on both main surfaces of the ceramic body, and first and second external layers including first and second external head portions and first and second external bands formed on the first and second internal bands and having a distance shorter than a distance of the first and second internal bands, the first and second external layers having viscosity higher than that of the first and second internal layers.

Abstract: Thickening a contact grid of a solar cell for increased efficiency. A mold containing soldering material is heated. The mold is aligned with the contact grid such that the soldering material is in physical contact with the contact grid. The mold is re-heated, transferring the solder material from the mold to the contact grid to create a thickened contact grid.

Abstract: A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.

Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

Abstract: An iridium interfacial stack (“IrIS”) and a method for producing the same are provided. The IrIS may include ordered layers of TaSi2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.

Abstract: Articles containing a matrix material and plurality of copper nanoparticles in the matrix material that have been at least partially fused together are described. The copper nanoparticles are less than about 20 nm in size. Copper nanoparticles of this size become fused together at temperatures and pressures that are much lower than that of bulk copper. In general, the fusion temperatures decrease with increasing applied pressure and lowering of the size of the copper nanoparticles. The size of the copper nanoparticles can be varied by adjusting reaction conditions including, for example, surfactant systems, addition rates, and temperatures. Copper nanoparticles that have been at least partially fused together can form a thermally conductive percolation pathway in the matrix material.

Abstract: A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Abstract: A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.

Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.

Abstract: A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.

Abstract: According to one embodiment, the semiconductor device in the embodiment has an assembly substrate, a semiconductor chip, and a jointing layer. The semiconductor chip is joined to the assembly substrate via the jointing layer. An intervening diffusion barrier layer may be interposed between the chip and jointing layer. The jointing layer is an alloy layer mainly made of any metal selected from Sn, Zn and In or an alloy of Sn, Zn and In, and any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V or an alloy of any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V and any metal selected from Sn, Zn and In, where the alloy has a higher melting temperature than that of Sn, Zn and In or an alloy of Sn, Zn and/or In.

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract: A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.

Abstract: A semiconductor device according to the present invention includes: a power semiconductor element that is a semiconductor element; bonding parts provided for bonding of an upper surface and a lower surface of the semiconductor element; and metal plates bonded to the power semiconductor element from above and below through the bonding parts, wherein the bonding part includes a mesh metal body disposed between the semiconductor element and the metal plate, and a bonding member in which the mesh metal body is embedded.

Abstract: Integrated circuits having electrically conductive traces are described. The electrically conductive traces may be formed of multiple electrically conductive layers. One or more of the multiple electrically conductive layers may have a cut formed therein to form a gap in that electrically conductive layer. One or more electrical conductive layers of the electrical conductive traces may bridge the gap.

Abstract: A bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of a substrate. The first bump includes a lower portion having a first width, a middle portion having a second width smaller than the first width, and an upper portion having a third width greater than the second width. The second bump is disposed on the upper portion of the first bump.

Abstract: Hybrid solder for solder balls and filled paste are described. A solder ball may be formed of a droplet of higher temperature solder and a coating of lower temperature solder. This may be used with a solder paste that has an adhesive and a filler of low temperature solder particles, the filler comprising less than 80 weight percent of the paste. The solder balls and paste may be used in soldering packages for microelectronic devices. A package may be formed by applying a solder paste to a bond pad of a substrate, attaching a hybrid solder ball to each pad using the paste, and attaching the package substrate to a microelectronic substrate by reflowing the hybrid solder balls to form a hybrid solder interconnect.

Abstract: A semiconductor device includes a first electrode, a second electrode, and an endothermic layer. The first electrode, the second electrode and the endothermic layer are formed on a semiconductor substrate. The first electrode is electrically conductive with an element formed inside of the semiconductor substrate. The endothermic layer is in contact with the first electrode and has electric conductivity. The second electrode is in contact with at least one of the first electrode and the endothermic layer and soldered to a metal electric conductor. Herein, at least one of a work function and contact resistivity of the first electrode is smaller than that of the endothermic layer. A heat of melting of the endothermic layer is larger than that of the first electrode. Solder joinability of the second electrode is higher than that of the endothermic layer.

Abstract: A semiconductor device is provided which has internal bonds which do not melt at the time of mounting on a substrate. A bonding material is used for internal bonding of the semiconductor device. The bonding material is obtained by filling the pores of a porous metal body having a mesh-like structure and covering the surface thereof with Sn or an Sn-based solder alloy.

Abstract: A lead-free solder alloy which can be used for soldering of vehicle-mounted electronic circuits and which exhibits high reliability is provided. The alloy consists essentially of Ag: 2.8-4 mass %, In: 3-5.5 mass %, Cu: 0.5-1.1 mass %, if necessary Bi: 0.5-3 mass %, and a remainder of Sn. In is at least partially in solid solution in the Sn matrix.

Abstract: Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

Abstract: According to a lead-free solder bump bonding structure, by causing the interface (IMC interface) of the intermetallic compound layer at a lead-free-solder-bump side to have scallop shapes of equal to or less than 0.02 [portions/?m] without forming in advance an Ni layer as a barrier layer on the surfaces of respective Cu electrodes of first and second electronic components like conventional technologies, a Cu diffusion can be inhibited, thereby inhibiting an occurrence of an electromigration. Hence, the burden at the time of manufacturing can be reduced by what corresponds to an omission of the formation process of the Ni layer as a barrier layer on the Cu electrode surfaces, and thus a lead-free solder bump bonding structure can be provided which reduces a burden at the time of manufacturing in comparison with conventional technologies and which can inhibit an occurrence of an electromigration.

Abstract: A semiconductor device includes a semiconductor element on which electrode pads are laid out. A wiring substrate includes connecting pads respectively arranged in correspondence with the electrode pads. Pillar-shaped electrode terminals are respectively formed on the electrode pads of the semiconductor element. A solder joint electrically connects a distal portion of each electrode terminal and the corresponding connecting pad on the wiring substrate. Each electrode terminal includes a basal portion, which is connected to the corresponding electrode pad, and a guide, which is formed in the distal portion. The guide has a smaller cross-sectional area than the basal portion as viewed from above. The guide has a circumference and the basal portion has a circumference that is partially flush with the circumference of the guide. The guide is formed to guide solder toward the circumference of the guide.

Abstract: The present invention relates to a terminal structure and an electronic device having the terminal structure. The terminal structure includes: a terminal having: a conductor layer containing at least one metal selected from gold, silver, and copper; a first layer containing nickel and phosphorus, laid on the conductor layer; a second layer having a smaller atomic ratio of nickel to phosphorus than the first layer and containing Ni3P, laid on the first layer; and a third layer containing a first intermetallic compound of an Ni—Cu—Sn type, laid on the second layer; and a solder layer on the third layer of the terminal. A second intermetallic compound of an Ni—P—Sn type partly covers a surface of the second layer on the third layer side and a maximum thickness of the second intermetallic compound in a lamination direction is from 0.05 to 0.7 ?m.

Abstract: Provided are a stacked package, a method of fabricating a stacked package, and a method of mounting the stacked package fabricated by the same.

Abstract: A solder includes zinc as a main component and the solder contains 6 to 8 mass percent of indium. A solder includes zinc as a main component, wherein the solder contains only indium. In a die-bonding structure in which a semiconductor chip is connected to a bonded member by a solder, the solder made of zinc as a main component and contains indium.

Abstract: A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.

Abstract: In a provided mounting structure, an electronic component such as a semiconductor chip having a fragile film is mounted on a substrate such as a circuit board with higher connection reliability. A junction that connects an electrode terminal (4) of an electronic component (1) and an electrode terminal (5) of a substrate (2) contains an alloy (8) and a metal (9) having a lower modulus of elasticity than the alloy (8). The junction has a cross section structure in which the alloy (8) is surrounded by the metal (9) having the lower modulus of elasticity.