Abstract: A wiring substrate comprised of a substrate main body made of glass-ceramic, a pad formed on a surface of the substrate main body and a conductor pin provided in an upright position on the pad. The pad is comprised of a ceramic that is the same as the ceramic constituting the glass-ceramic, Fe converted into Fe2O3 and Cu. The Fe2O3 comprises 1 to 28 parts by weight with respect to 100 parts by weight of the Cu.

Abstract: A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

Abstract: Disclosed are an integrated circuit component capable of simply mounting at low cost a chip part which adjusts impedance of wiring patterns as well as capable of effectively reducing switching noise from an integrated circuit, and a method for mounting the chip part. The integrated circuit component of the present invention has a constitution that a bypass capacitor is mounted on a wiring board side of a gap between the wiring board and an LSI chip. Therefore, as compared with a case where the capacitor is mounted on the LSI chip side, a transmission path through the capacitor can be extremely shortened. As a result, inductance components of the feeder line can be reduced, so that a response delay of power transmitted through the feeder line can be sufficiently suppressed.

Abstract: An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions are selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module.

Abstract: A semiconductor package assembly comprises a first conductive pad on a semiconductor substrate; a second conductive pad on a package substrate; a bump physically coupled between the first conductive pad and the second conductive pad, wherein the bump is substantially lead-free or high-lead-containing; the bump has a first interface with the first conductive pad, the first interface having a first linear dimension; the bump has a second interface with the second conductive pad, the second interface having a second linear dimension; and wherein the ratio of the first linear dimension and the second linear dimension is between about 0.7 and about 1.7.

Abstract: A method for forming a bump includes the steps of forming a resist layer so that a through-hole formed therein is located on a pad; and forming a metal layer to be electrically connected to the pad conforming to the shape of the through-hole. The metal layer is formed so as to have a shape in which is formed a region for receiving a soldering or brazing material.

Abstract: A semiconductor package includes a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps. An encapsulant encapsulates the die, the electrical connections, and the plurality of lead fingers to expose a lower surface of the plurality of lead fingers. The plurality of stud bumps may include a plurality of clusters of stud bumps.

Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.

Abstract: In one embodiment, a photo-imageable material is deposited on a circuit structure. The photo-imageable material is then exposed to a pattern of radiation, thereby polymerizing portions of the photo-imageable. Un-polymerized portions of the photo-imageable material are then removed to define a solder mask having solder deposition areas. Solder is then deposited in the solder deposition areas. A circuit structure that may be produced in accordance with this method is also disclosed.

Abstract: A device having a substrate, a pair of ferromagnetic leads on a surface of the substrate, laterally separated by a gap, and one or more ferromagnetic microparticles comprising a conductive coating at least partially within the gap. The conductive coating forms at least part of an electrical connection between the leads. A molecular junction may connect the leads to the microparticle.

Abstract: A flip chip package, apparatus and technique in which a ball grid array composed of a doped eutectic Pb/Sn solder composition is used. The dopant in the Pb/Sn solder forms a compound or complex with the phosphorous residue from the electroless nickel plating process that is mixable with the Pb/Sn solder. The phosphorous containing compound or complex prevents degradation of the solder/under bump metallization bond associated with phosphorus residue. The interfacial solder/under bump metallization bond is thereby strengthened. This results in fewer fractured solder bonds and greater package reliability.

Abstract: A submount that enables the reliable mounting of a semiconductor light-emitting device on it, and a semiconductor unit incorporating the submount. A submount 3 comprises (a) a substrate 4; and (b) a solder layer 8 formed on the top surface 4f of the substrate 4. The solder layer 8 before melting has a surface roughness, Ra, of at most 0.18 ?m. It is more desirable that the solder layer 8 before melting have a surface roughness, Ra, of at most 0.15 ?m, yet more desirably at most 0.10 ?m. A semiconductor unit 1 comprises the submount 3 and a laser diode 2 mounted on the solder layer 8 of the submount 3.

Abstract: A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention comprise adding copper to non-copper based solder, such as tin-lead solder. The embodiments may further comprise using the copper-bearing solder as a solder interconnect on a gold-nickel pad.

Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.

Abstract: In one embodiment, the present invention includes a semiconductor package including a first semiconductor die with first active circuitry and a second semiconductor die with second active circuitry. An intermediate substrate may be located in the package between the first and second semiconductor dies to provide power to at least one of the dies. In this way, improved stacking within a single package is afforded. Other embodiments are described and claimed.

Abstract: In a semiconductor module connecting a semiconductor element and a passive element to a printed board, each of connection portions between the semiconductor element and the printed board and between the passive element and the printed board includes a metal with a melting point of 260° C. or higher and an intermetallic compound with a melting point of 260° C. or higher. Specifically, by connecting them using Pb-free solder with a melting point of 260° C. or lower, the printed board capable of lowering in cost, lightening, and reducing back height can be applied to a module board.

Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Abstract: A liquid crystal display device includes a liquid crystal panel including a pad electrode, a tape circuit substrate and an anisotropic conductive film. The pad electrode receives one of a driving signal and a power supply voltage signal. The tape circuit substrate includes a base film made of an insulating material, and a signal line formed on the base film and having a slit at a portion of the signal line which overlaps the pad electrode of the liquid crystal panel. The anisotropic conductive film connects the outer lead with the pad electrode.

Abstract: An assembly includes a substrate, a device coupled to the substrate; a ring formed on the substrate; and one or more bonding pads formed on the substrate, wherein the ring and bonding pads are formed of a same material.

Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, etc., and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.

Abstract: In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of resin, electrodes of the semiconductor chip and the lead terminals are connected by Pb-free connection parts each having a configuration of connection layer/stress buffer layer/connection layer. In each connection part, the connection layer is formed of an inter-metallic compound layer having a melting point of 260° C. or higher or Pb-free solder having a melting point of 260° C. or higher, and the stress buffer layer is formed of a metal layer having a melting point of 260° C. or higher and having a function to buffer the thermal stress.

Abstract: A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is provided on the one side of the base member around the semiconductor constructing body. An adhesion increasing film is formed between the insulating layer, and at least one of the semiconductor constructing body and the base member around the semiconductor constructing body, for preventing peeling between the insulating layer and the at least one of the semiconductor constructing body and base member.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: Example embodiments of the present invention relate to an alloy solder and a semiconductor device using the alloy solder. Other example embodiments relate to an alloy solder capable of increasing reliability of a junction between a semiconductor chip and a substrate. According to still other example embodiments of the present invention, there may be a tin-bismuth (Sn—Bi) family alloy solder between a semiconductor chip and a substrate, and a semiconductor device using the alloy solder. The semiconductor device may include a semiconductor chip formed with a plurality of gold (Au) bumps, a substrate having metal wirings connected to the gold (Au) bumps, and a junction including a tin-bismuth (Sn—Bi) family alloy solder interposed between and connecting the gold (Au) bump and the metal wiring.

Abstract: A buffer layer is formed on a substrate and then electronic devices are packed on the buffer layer in the present invention, and problems of lower hermeticity and complex process in the conventional arts can be avoided. Therefore, the present invention provides a packaging structure and method with a better hermeticity and a simpler process. Especially, due to the buffer layer, the planarization for flip-chip bonding can be improved and reduce negative effects of the packing process.

Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device.

Abstract: There is provided a surface treatment method for an electronic part, which uses a metal not containing lead and tin and having excellent solder wettability, is economical and has high reliability. In the surface treatment method for the electronic part in which a soldered part is subjected to a surface treatment of structure of three layers of nickel, palladium and gold, the palladium layer and the gold layer are formed by an electrolytic plating treatment, a thickness of the palladium layer is in a range of 0.007 to 0.1 ?m, a thickness of the gold layer is in a range of 0.003 to 0.02 ?m, and a relation of the thickness of the gold layer<the thickness of the palladium layer is established.

Abstract: A circuit device is provided in which the bonding reliability of a brazing material such as soft solder is improved. A circuit device of the present invention includes conductive patterns, a bonding material which fixes circuit elements to the conductive patterns, and sealing resin which covers the circuit elements. The circuit device has a structure in which Pb-free solder containing Bi is used as the bonding material. Since the melting temperature of Bi is high in comparison with that of a general solder, the melting of the bonding material is suppressed when the circuit device is mounted. Further, Ag or the like may be mixed into the bonding material in order to enhance the wettability of the bonding material.

Abstract: Embodiments of the invention provide a low-melting temperature comprised primarily of a bulk intermetallic phase material. This solder may allow reflow with less of a chance to damage microelectronic devices due to coefficient of thermal expansion mismatches, and may be creep resistant even at high homologous temperatures.

Abstract: Crystal growth performed in situ facilitates interconnection of prefabricated nano-structures. The nano-structures are immersed in a growth solution having a controllable saturation condition. Changing the saturation condition of the solution modifies a size of the immersed nanowires. The solution includes a solute of a nano-structure precursor material. The saturation condition is changed to one or both etch material from a surface of the nano-structures and initiate crystal growth on the nano-structure surface. A nano-structure interconnection system includes the growth solution and equipment to deposit the prefabricated nano-structures on a substrate. An interconnected structure includes a plurality of nano-structures disposed on a substrate in a cluster and a liquid phase-grown crystal lattice on surfaces of the nano-structures to form physical interconnections between the plurality. An ink formulation includes the plurality of nano-structures suspended in the growth solution.

Abstract: A semiconductor device comprises a bonding surface to be mounted with adhesive or solder on a mounting surface of a mounting member. One or more grooves are provided on the bonding surface that extend in a direction substantially parallel to one side surface of the semiconductor device.

Abstract: A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximately 4 wt % to approximately 8 wt % bismuth, approximately 2 wt % to approximately 4 wt % silver, approximately 0 wt % to approximately 0.7 wt % copper, and approximately 87 wt % to approximately 92 wt % tin. The die solder pads might comprise between approximately 7 wt % to approximately 20 wt % indium, between approximately 2 wt % to approximately 4.5 wt % silver, between approximately 0 wt % to approximately 0.7 wt % copper, between approximately 0 wt % to approximately 0.5 wt % antimony, and between approximately 74.3 wt % to approximately 90 wt % tin.

Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.

Abstract: A semiconductor device comprises a semiconductor element which is flip-chip bonded to a circuit substrate. The semiconductor element and the circuit substrate are flip-chip bonded using a sealing resin having flux function. The semiconductor element includes a solder bump formed on a first electrode pad through a first low melting point solder layer. The circuit substrate includes a second electrode pad corresponding to the first electrode pad, and a second low melting point solder layer is formed on the second electrode pad. The solder bump is bonded to the first and second electrode pads through the first and second low melting point solder layers.

Abstract: An electronic device has at least one semiconductor chip, which has mutually opposing contact sides, of which one first contact side is electroconductively surface-bonded via a first, solid soldering-agent layer to at least one first metallic conductor part. The semiconductor chip is electroconductively surface-bonded on its second contact side facing opposite the first contact side via a second soldering-agent layer to at least one second metallic conductor part. The softening temperature of the second soldering-agent layer is adapted to an operating temperature that occurs in this soldering-agent layer during operation of the device in such a way that the second soldering-agent layer is doughy or liquid at the operating temperature. The second soldering-agent layer is laterally bounded by a flow-off protection device.

Abstract: The present invention provides a submount that allows a semiconductor light-emitting element to be attached with a high bonding strength. A submount 3 is equipped with a substrate 3 and a solder layer 8 formed on a primary surface 4f of the substrate 4. The density of the solder layer 8 is at least 50% and no more than 99.9% of the theoretical density of the material used in the solder layer 8. The solder layer 8 contains at least one of the following list: gold-tin alloy; silver-tin alloy; and lead-tin alloy. The solder layer 8 before it is melted is formed on the substrate 4 and includes an Ag film 8b and an Sn film 8a formed on the Ag film 8b. The submount 3 further includes an Au film 6 formed between the substrate 4 and the solder layer 8.

Abstract: A mold type semiconductor device includes a semiconductor chip including a semiconductor part; a metallic layer; a solder layer; and a metallic member connecting to the semiconductor chip through the metallic layer and the solder layer. The solder layer is made of solder having yield stress smaller than that of the metallic layer. Even when the semiconductor chip is sealed with a resin mold, the metallic layer is prevented from cracking.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a pillar, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The routing line extends laterally from the pillar towards the chip, the pillar includes tapered sidewalls, and the chip and the pillar are embedded in the encapsulant and extend vertically beyond the routing line in the same direction.

Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.

Abstract: An electronic component includes a substrate with outer contact areas comprising copper. Lead-free solder bumps are disposed on the outer contact areas of the electronic component. An electronic configuration includes an electronic component and a printed circuit board. The electronic component is mounted on the printed circuit board by lead-free solder electrical connections.

Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.

Abstract: A method and apparatus for packaging a semiconductor die with an interposer substrate. The semiconductor device assembly includes a conductively bumped semiconductor die and an interposer substrate having multiple recesses formed therein. The semiconductor die is mounted to the interposer substrate with the conductive bumps disposed in the multiple recesses so that the active surface of the semiconductor die is directly mounted to a facing surface of the interposer substrate. One or more openings may be provided in an opposing surface of the interposer substrate which extends to the multiple recesses and the bumps disposed therein and dielectric filler material introduced through the one or more openings into to the recesses.

Abstract: Pads to be used for flip chip bonding and wire bonding are pattern-formed on a surface of a substrate. The pads to be used for flip chip bonding are shielded. Plating is applied to each of the pads to be used for wire bonding. Bonding pads for wire bonding is shielded by a masking tape. An adhesive layer is applied to the surface of each of pads to be used for flip chip bonding. Solder powder is provided to adhere to the surface of each of pads to be used for flip chip bonding with the adhesive layer. The masking tape is peeled off from the bonding pads for wire bonding. The solder powder is melted by reflowing so that the solder covers the pads to be used for flip chip bonding.

Abstract: A method for fabricating an electrical connection structure of a circuit board is proposed. A patterned resist layer is formed on the circuit board having a plurality of conductive pads, and a plurality of openings is formed in the resist layer to expose the conductive pads. A first conductive material and a second conductive material are successively deposited in the openings of the resist layer and on each of the conductive pads. Then, the resist layer is removed. Subsequently, a protective layer is applied on the circuit board and covers the first and second conductive materials formed on each of the conductive pads. Finally, the protective layer is thinned to expose the second conductive material corresponding in position to each of the conductive pads. Thus, the circuit board can be electrically connected to an external device via the second conductive material.

Abstract: A semiconductor module solder bonding of high reliability in which the heat resisting properties of the circuit substrate and electronic parts are taken into consideration. In order to achieve this, there are provided semiconductor devices each having solder bumps as external pads, and a circuit substrate bonded to the external pads of each of the semiconductor devices through a solder paste, each of the solder bumps being made of a first lead-free solder, the solder paste being made of a second lead-free solder having a melting point lower than that of the first lead-free solder.

Abstract: A semiconductor device including: a semiconductor chip; a wiring board on which the semiconductor chip is mounted; and a plurality of external terminals provided on the wiring board. The external terminals include at least one first external terminal and two or more second external terminals. The first external terminal is formed of a soldering material. Each of the second external terminals includes a soldering material and a plurality of particles formed of a resin and dispersed in the soldering material. The second external terminals are a pair of external terminals among the external terminals, and a distance between the pair of external terminals is greater than a distance between any other pair of external terminals among the external terminals.

Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Abstract: This invention is a method of manufacturing printed circuit boards using a contact block packaging to provide and support electrical contact blocks relative to a printed circuit board panel. The contact block packaging is situated adjacent to the printed circuit board panel, so that electrical contact blocks of the contact block packaging are aligned with circuit boards of the printed circuit board panel, but breakaway stems supporting the electrical contact blocks are offset from webbing of the printed circuit board panel. The electrical contact blocks are then soldered to the printed circuit boards. Thereafter, the breakaway stems of the contact block packaging and the webs of the printed circuit board panel are broken, so that the electronic contact blocks are decoupled from the rest of the contact block packaging and the printed circuit boards are decoupled from the rest of the printed circuit board panel.

Abstract: A wiring substrate incorporating nickel-plated copper terminal pads for solder bumps, wherein a nickel plating layer constituting the nickel plated copper terminal pads has a phosphorus content of 8.5 to 15.0% by mass and is covered with a gold plating layer.