Abstract: A semiconductor device is provided, the semiconductor device including a semiconductor chip having a first metal heat-conductive medium in the inside thereof, a substrate having a second metal heat-conductive medium thermally connected to the first metal heat-conductive medium, and a temperature control device of which at least a part is disposed on the substrate, thermally connected to the second metal heat-conductive medium, and configured to control the temperature within the semiconductor chip.

Abstract: A method of fabricating electroplate solder on an organic circuit board for forming flip chip joints and board to board solder joints is disclosed. In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact pad. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer with at least an opening located at the pad is formed over the metal seed layer. A solder material is then formed in the opening by eletroplating. Finally, the resist and the metal seed layer beneath the resist are removed.

Abstract: A process of production of a semiconductor apparatus which can suppress a rise in the electrical resistance and a decline in the joint strength at the bump connection interfaces and improve the connection reliability when using the method of reinforcing the bases of the bumps by a resin film. Bumps are formed on a semiconductor wafer formed with a pattern circuit of a semiconductor chip so as to connect to the circuit pattern, a resin film is formed on the bump forming surface of the semiconductor wafer to a thickness giving a surface lower than the height of the bumps while sealing the spaces between the bumps, plasma cleaning etc., is used to remove the sealing resin components deposited on the surface portions of the bumps or natural oxides or other insulating impurities to clean and activate the surfaces of the bumps, and the chip is mounted on a mounting board.

Abstract: A soldered assembly for a microelectronic element includes a microelectronic element, solder columns extending from a surface of the microelectronic element and terminals connected to distal ends of the columns. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may be inclined relative to the chip surface, and may contain long, columnar inclusions preferentially oriented along the lengthwise axes of the columns.

Abstract: A solder system includes a lead (Pb) indicator and a solder flux. A method for forming a semiconductor device includes providing a carrier, applying the solder system to the carrier, coupling the terminal to the carrier via the solder system, melting the solder system to attach the terminal to the carrier and form a completed semiconductor device, and determining if the completed semiconductor device has a different predetermined property from the solder system.

Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu etc. and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.

Abstract: An interconnect structure of a semiconductor device includes a tungsten plug (14) deposited in a via or contact window (11). A barrier layer (15) separates the tungsten plug (14) from the surface of a dielectric material (16) within which the contact window or via (11) is formed. The barrier layer (15) is a composite of at least two films. The first film formed on the surface of the dielectric material (16) within the via (11) is a tungsten silicide film (12). The second film is a tungsten film (13) formed on the tungsten silicide film (12). A tungsten plug (14) is formed on the tungsten film (13) to complete interconnect structure. The barrier layer (15) is deposited using a sputtering technique performed in a deposition chamber. The chamber includes tungsten silicide target (19) from which the tungsten silicide film (12) is deposited, and a tungsten coil (20) from which the tungsten film (20) is deposited.

Abstract: Electronic contacts, including spherical cores and attachment layers on the cores, are provided for attaching a semiconductor package substrate to a printed circuit board. The spherical cores are made of high-melting-temperature copper, and the attachment layers are made of a low-melting-temperature eutectic. The attachment layers melt in a reflow process. The spherical cores do not melt, and thereby control movement or “collapsing” of the package substrate toward the printed circuit board.

Abstract: Enhanced ACF bonding pads for use in conjunction with anisotropic conductive film (ACF) in electronic devices, such as, liquid crystal display panels and plasma display panels have at least two finger-like portions. Such bonding pads, typically provided on a flexible wiring lead, when bonded to other metal structures via the ACF film, make better electrical contact with the other metal structures because the spaces between the finger-like portions of the improved bonding pads allow the ACF film's binder material to reside between the finger-like portions preventing the bonding pad metal in the center region of the bonding pad from separating away from the other metal structures.

Abstract: A self supported underfill film adhesively bonds surface mount integrated circuit packages to a printed circuit board. The printed circuit board has conductive traces and exposed conductive pads on the surface. Solder paste is printed on the conductive pads, and one or more additional solder paste deposits are printed in an area outside the conductive pads to serve as tack pads for a film adhesive. The film adhesive is strategically positioned on the printed circuit board over the tack pads and near the conductive pads, and the surface mount integrated circuit package is then placed on the board so that the conductive pads on the package align with the conductive pads on the board. The film adhesive softens when the package is soldered to the board, and the film ultimately serves as an underfill to increase the mechanical integrity of the solder joints.

Abstract: A submount can mount on it a semiconductor light-emitting device with high bonding strength, and a semiconductor unit incorporates the submount. The submount comprises (a) a submount substrate, (b) a solder layer formed at the top surface of the submount substrate, and (c) a solder intimate-contact layer that is formed between the submount substrate and the solder layer and that has a structure in which a transition element layer consisting mainly of at least one type of transition element and a precious metal layer consisting mainly of at least one type of precious metal are piled up. In the above structure, the transition element layer is formed at the submount-substrate side. The semiconductor unit is provided with a semiconductor light-emitting device mounted on the solder layer of the submount.

Abstract: The present invention relates to a lead-free bump with suppressed formation of voids, obtained by reflowing a plated film of Sn—Ag solder alloy having an adjusted Ag content, and a method of forming the lead-free bump. The lead-free bump of the present invention is obtained by forming an Sn—Ag alloy film having a lower Ag content than that of an Sn—Ag eutectic composition by plating and reflowing the plated alloy film.

Abstract: An improved method and solder composition for kinetically controlled part bonding. The method involves applying at least a first chemical element layer of an intermetallic compound to a first part and applying at least a second chemical element layer of the intermetallic compound to a second part. The first and second parts are placed together so that the chemical element layers contact each other. The parts are heated from a storage temperature to a bonding temperature which is slightly above a first melting temperature that melts the chemical element layer of one of the first and second parts into a liquid mixture. The composition of liquid mixture varies with time during heating due to the formation of the intermetallic compound therein by progressive incorporation of the other one of the first and second chemical element layers into the mixture.

Abstract: There is provided a mask for use in printing solder on a plurality of terminals formed on a substrate so as to correspond to a plurality of terminals of an IC package. The mask has openings through which the solder is applied, and the openings are larger than the terminals. Although a wiring line adjacent to the terminals may be covered with the solder, a reflow process causes the solder to be divided into a first portion and a second portion, thus preventing short-circuits between the wiring line and the terminals.

Abstract: A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention comprise adding copper to non-copper based solder, such as tin-lead solder. The embodiments may further comprise using the copper-bearing solder as a solder interconnect on a gold-nickel pad.

Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: A method of producing a wiring board includes a preliminary plating step of forming a solder resist layer such that the main layer of each metal pad of the board is exposed in each corresponding opening and covering the surface of the exposed main layer with a preliminary Sn plated layer. A solder paste application step involves applying a solder paste, containing solder powder comprised of the high temperature Sn solder and thicker than the preliminary Sn plated layer, on the preliminary Sn plated layer. A subsequent solder melting step involves forming the Sn solder covering layer by melting the solder paste layer together with the preliminary Sn plated layer by heating the solder paste layer to a temperature higher than the liquid phase line temperature of the high temperature Sn solder. This wettingly extends the melted layers over the surface of the main layer.

Abstract: A flip chip package, apparatus and technique in which a ball grid array composed of a doped eutectic Pb/Sn solder composition is used. The dopant in the Pb/Sn solder forms a compound or complex with the phosphorous residue from the electroless nickel plating process that is mixable with the Pb/Sn solder. The phosphorous containing compound or complex prevents degradation of the solder/under bump metallization bond associated with phosphorus residue. The interfacial solder/under bump metallization bond is thereby strengthened. This results in fewer fractured solder bonds and greater package reliability.

Abstract: The invention relates to a method for making an integrated circuit (40) of the surface-mount type the comprising, first of all, manufacture of a package having a rear face and a pin grid array extending under this rear face perpendicular thereto, and a ball (44) of low melting point alloy is then formed at the end of each pin surrounding this end and soldered thereto. The invention also relates to an integrated circuit (40) of the surface-mount type, comprising a package having a rear face and a pin grid array, of a cross section roughly constant along the pin (42), extending under the rear face perpendicular thereto. A ball (44) of low melting point alloy is soldered to the end of each pin (42) surrounding this end.

Abstract: Improved apparatus and methods for stacking integrated circuit packages having leads are disclosed. According to one embodiment, the leads of an integrated circuit package are exposed and provided with solder balls so that corresponding leads of another integrated circuit package being stacked thereon can be electrically connected. The stacking results in increased integrated circuit density with respect to a substrate, yet the stacked integrated circuit packages are able to still enjoy having an overall thin or low profile.

Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.

Abstract: A semiconductor integrated circuit device which requires high packaging density adopts a method for forming bumps in a terminal section of a semiconductor chip and bonding the semiconductor chip directly on a substrate. In this case, in order to prevent damage to the semiconductor integrated chip, which would otherwise be caused by bonding pressure employed at the time of bonding operation, non-connected dummy bumps are provided at corner sections of the semiconductor chip. Even when the dummy bumps are provided, there arises a necessity for preventing an increase in the size of the semiconductor chips, which would otherwise arise when the dummy bumps are provided on the chip.

Abstract: A ball grid array electronic package is attached to a substrate by means of solder balls and solder paste. Connection is made between a contact on the ball grid array and a solder ball by means of a first joining medium, such as a solder paste. Connection is made between a solder ball and a contact arranged on the substrate by means of a second joining medium. The contact arranged on the substrate is substantially quadrilateral in shape, and preferably substantially square in shape. Connection to the substrate, e.g., using round solder balls, is much more easily detected, e.g., by x-ray, than when using round pads, especially those having a smaller diameter than the balls.

Abstract: A device including a first solder pad and a second solder pad comprised of a post-soldering alloy composition on a substrate is provided. The alloy composition comprises two or more elements, and the post soldering alloy composition of the first solder pad has different amounts of the two or more elements than the alloy composition of the second solder pad. A method of making a solder pad comprises masking a substrate comprising at least a first solder pad and a second solder pad, wherein the mask exposes a greater area of the first solder pad so that the deposited element becomes part of an alloy composition of the first solder pad upon soldering thereby changing the melting point of the first solder pad.

Abstract: A lead free solder hierarchy structure for electronic packaging that includes organic interposers. The assembly may also contain passive components as well as underfill material. The lead free solder hierarchy also provides a lead free solder solution for the attachment of a heat sink to the circuit chip with a suitable lead free solder alloy.

Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.

Abstract: A carrier for an integrated chip is embedded into a substrate, so that stresses due to thermal expansion are uniformly distributed over an interface between the substrate and the carrier (hereinafter “embedded carrier”). Such an embedded carrier may be formed of a material having a coefficient of thermal expansion similar or identical to the coefficient of thermal expansion of an integrated circuit chip to be mounted thereon, so as to eliminate stresses (due to thermal expansion) at joints between the carrier and the integrated circuit chip. The just-described joints may be formed by any method well known in the art, e.g. flip-chip bonding. Such packaging of one or more integrated circuit chip(s) eliminates reliability issues associated with conventional flip chip bonded components, which are caused by, for example, concentration of stresses in conventional solder ball interconnections between a chip and a substrate.

Abstract: A method of making a semiconductor device is provided. The method includes the following steps. First, a semiconductor chip is mounted on a lower conductor, with first solder material applied between the chip and the lower conductor. Then, an upper conductor is placed on the chip, with second solder material applied between the chip and the upper conductor. Then, the first and the second solder materials are heated up beyond their respective melting points. Finally, the first and the second solder materials are allowed to cool down, so that the first solder material solidifies earlier than the second solder material.

Abstract: An electronic component includes an organic interposer (160, 460, 560, 660, 760, 860, 960), a semiconductor chip (220) mounted over the organic interposer, copper pads (250, 751, 851) under the organic interposer, a solder attachment (110, 510, 610, 910) between certain ones of the copper pads, and solder interconnects (120, 420) between certain other ones of the copper pads and located around an outer perimeter (111, 511, 911) of the solder attachment. The solder attachment is placed at locations within the electronic component that experience the greatest stress, which may include, for example, locations adjacent to at least a portion of a perimeter (221) of the semiconductor chip. In one embodiment, a surface area of the solder attachment is larger than a surface area of each one of the solder interconnects. In the same or another embodiment, the electronic component includes multiple solder attachments.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom.

Abstract: A semiconductor device is arranged such that a semiconductor chip having electrodes is flip chip mounted on printed substrate pads on a printed wiring substrate by a bump formed on each electrode. The semiconductor chip and the printed wiring substrate are fixed with a thermo-setting resin. A penetration hole is formed within an area where the printed substrate pad contacts each gold bump, and the gold bump has a joint section also on a side face of the penetration hole of the printed substrate pad. With this structure, the semiconductor device has a secure electrical connection between the bump and the metal pattern.

Abstract: A method of glass frit bonding wafers to form a package, in which the width of the glass bond line between the wafers is minimized to reduce package size. The method entails the use of a glass frit material containing a particulate filler material that establishes the stand-off distance between wafers, instead of relying on discrete structural features on one of the wafers dedicated to this function. In addition, the amount of glass frit material used to form the glass bond line between wafers is reduced to such levels as to reduce the width of the glass bond line, allowing the overall size of the package to be minimized. To accommodate the variability associated with screening processes when low volume lines of paste are printed, the invention further entails the use of storage regions defined by walls adjacent the glass bond line to accommodate excess glass frit material without significantly increasing the width of the bond line.

Abstract: A method is provided for forming a wafer stack. This may include providing a first wafer having a first plurality of metalized trenches on a surface of the first wafer. A second wafer may be provided having a second plurality of metalized trenches on a surface of the second wafer facing the first wafer. The first plurality of metalized trenches may be solder bonded to the second plurality of metalized trenches.

Abstract: A metal interconnection structure for semiconductor chips has a metal interface layer (105), preferably nickel, deposited over the metal of the chip contact pad (104, usually aluminum or copper). A subsequent metal layer (106) is an alloy of a metal such as copper or gold with nickel, wherein the quantity of nickel is selected so that it diminishes the interdiffusion rate of the nickel from the interface layer (105) during the reflow and annealing processes. Reflowable metal (107) for interconnection completes the structure. In another embodiment, the reflowable metal (107) contains an admixture of the interface metal in a quantity to diminish the interdiffusion rate of metal from the interface layer during the annealing process. In either embodiment, the formation of voids in the interface layer (105) is diminished.

Abstract: A carrier has a metal area that is essentially composed of copper. A chip has a rear side metallization layer. A buffer layer, essentially composed of nickel and having a thickness of between 5 ?m and 10 ?m, is arranged on the metal area. The chip does not have a chip housing and is arranged on the metal area, which has been provided with the buffer layer, such that only one connecting medium is arranged between the rear side metallization layer of the chip and the buffer layer.

Abstract: A semiconductor device includes a semiconductor element having a plurality of element electrodes and a ball electrode electrically connected to at least one element electrode out of the plurality of element electrodes. The ball electrode is made of a Sn—Zn-based lead-free solder including 7 through 9.5 wt % of zinc and the remaining of tin.

Abstract: A solder interconnection uses preferably lead-rich solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a thin cap layer of preferably pure tin is deposited on a surface of the solder balls. An interconnecting eutectic alloy is formed upon reflow. Subsequent annealing causes tin to diffuse into the lead, or vice versa, and intermix, thereby raising the melting point temperature of the cap layer of the resulting assembly. This structure and process avoids secondary reflow problems during subsequent processing.

Abstract: An object of the invention is to prevent the color on a surface of a plated metal layer from changing. The invention is a wiring substrate obtained by forming a wiring conductor made of a metal having a high melting point on an insulator, and coating a surface of the wiring conductor with an electroless plated metal layer, wherein the electroless plated metal layer contains an element of Group 1B and is free from lead.

Abstract: A thermal-stress-absorbing interface structure is provided between a semiconductor integrated circuit chip and a surface-mount structure. The interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The pad has an interconnection line extending from the side thereof intermediate the first and the second ends. The interconnection line is electrically connected to the chip. The interface structure further includes a first polymer layer having an exposed surface, and a second polymer layer, each having a different modulus of elasticity, disposed below the pad. The second polymer layer extends over substantially the entire exposed surface of the first polymer layer to absorb a thermal stress during thermal cycling.

Abstract: A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Abstract: There is provided a bonding material and a bonding method which enable lead-free bonding that can replace high-temperature soldering. The bonding material of the present invention comprises a dispersion in an organic solvent of composite metallic nano-particles having such a structure that a metal core of a metal particle having an average particle diameter of not more than 100 nm. The bonding material can be advantageously used in a stepwise bonding process containing at least two bonding steps.

Abstract: A solder, in particular a thin-film solder, for joining microelectromechanical components, wherein the solder is a eutectic mixture of gold and bismuth. Components and devices joined by a solder of this type are also disclosed, in addition to processes for producing such components or devices.

Abstract: A thinned semiconductor die is coupled to an integrated heat spreader with thermal interface material to form a semiconductor package. The method for forming the package comprises forming a metallization layer on a backside of a thinned semiconductor die. A thermal interface portion, including a solder layer including a fluxlessly-capable solder such as AuSn, is formed on a topside of the integrated heat spreader. The metallization layer and the solder layer are then forced together under load and heat without flux to bond the semiconductor die to the integrated heat spreader.

Abstract: An under-ball-metallurgy layer between a bonding pad on a chip and a solder bump made with tin-based material is provided. The under-ball-metallurgy layer at least includes an adhesion layer over the bonding pad, a nickel-vanadium layer over the adhesion layer, a wettable layer over the nickel-vanadium layer and a barrier layer over the wettable layer. The barrier layer prevents the penetration of nickel atoms from the nickel-vanadium layer and reacts with tin within the solder bump to form inter-metallic compound. This invention also provides an alternative under-ball-metallurgy layer that at least includes an adhesion layer over the bonding pad, a wettable layer over the adhesion layer and a nickel-vanadium layer over the wettable layer. The nickel within the nickel-vanadium layer may react with tin within the solder bump to form an inter-metallic compound.

Abstract: In an electronic component provided with an electric contact(s) producing an electric conduction by contacting with a contact(s) of a second electronic component, the electric contact comprises a lead-free alloy layer containing tin and silver, and a surface layer portion of the alloy layer at least contacting with the contact of the second electronic component is a tin-rich layer having a tin content higher than that of the other portion of the alloy layer.

Abstract: A metal interconnection structure for semiconductor chips has a metal interface layer (105), preferably nickel, deposited over the metal of the chip contact pad (104, usually aluminum or copper). A subsequent metal layer (106) is an alloy of a metal such as copper or gold with nickel, wherein the quantity of nickel is selected so that it diminishes the interdiffusion rate of the nickel from the interface layer (105) during the reflow and annealing processes. Reflowable metal (107) for interconnection completes the structure. In another embodiment, the reflowable metal (107) contains an admixture of the interface metal in a quantity to diminish the interdiffusion rate of metal from the interface layer during the annealing process. In either embodiment, the formation of voids in the interface layer (105) is diminished.

Abstract: Low stress concentration solder bumps are created on a semiconductor wafer by the removal of metal oxides on the edges of under bump metallurgy, (UBM). The removal of the oxides from the circular edge of the UBM allow the solder of the solder bump to wet the sides of the UBM, mainly the plated copper portion, thereby resulting in a solder bump structure with a filled undercut. This results in a lower stress concentration solder bump structure. This solder bump structure is obtained after the solder bumps have been reflowed on the wafer.

Abstract: A lead free solder hierarchy structure for electronic packaging that includes organic interposers. The assembly may also contain passive components as well as underfill material. The lead free solder hierarchy also provides a lead free solder solution for the attachment of a heat sink to the circuit chip with a suitable lead free solder alloy.

Abstract: An electronic component includes an organic interposer (160, 460, 560, 660, 760, 860, 960), a semiconductor chip (220) mounted over the organic interposer, copper pads (250, 751, 851) under the organic interposer, a solder attachment (110, 510, 610, 910) between certain ones of the copper pads, and solder interconnects (120, 420) between certain other ones of the copper pads and located around an outer perimeter (111, 511, 911) of the solder attachment. The solder attachment is placed at locations within the electronic component that experience the greatest stress, which may include, for example, locations adjacent to at least a portion of a perimeter (221) of the semiconductor chip. In one embodiment, a surface area of the solder attachment is larger than a surface area of each one of the solder interconnects. In the same or another embodiment, the electronic component includes multiple solder attachments.

Abstract: A lead material for an electronic part having no adverse effect on the environment, having excellent solderability, desirable welding strength during welding and a low degree of nonuniform thickness of the plated layer during reflow processing. The lead material has a first plated layer and a second plated layer, both of which do not contain Pb, laminated on the surface of a conductive substrate in such order. The melting point of the second plated layer is lower than that of the first plated layer. The first and second plated layers are made of a Sn substance and a Sn alloy, respectively or vice versa.