Varying Width Or Thickness Of Conductor Patents (Class 257/775)
  • Patent number: 10850518
    Abstract: Techniques are provided for making a funnel-shaped nozzle in a substrate. The process can include forming a first opening having a first width in a top layer of a substrate, forming a patterned layer of photoresist on the top surface of the substrate, the patterned layer of photoresist including a second opening, the second opening having a second width larger than the first width, reflowing the patterned layer of photoresist to form curved side surfaces terminating on the top surface of the substrate, etching a second layer of the substrate through the first opening in the top layer of the substrate to form a straight-walled recess, the straight-walled recess having the first width and a side surface substantially perpendicular to the top surface of the semiconductor substrate.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 1, 2020
    Assignee: FUJIFILM Dimatix, Inc.
    Inventors: Gregory DeBrabander, Mark Nepomnishy
  • Patent number: 10854622
    Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Bae Yoon, Joong-Shik Shin, Kwang-Ho Kim, Hyun-Mog Park
  • Patent number: 10818497
    Abstract: The present invention provides a patterned structure for an electronic device and a manufacturing method thereof. The patterned structure includes a patterned layer, a blocking structure, a cantilever structure, and a connection structure. The patterned layer is disposed on a substrate. The blocking structure is disposed on the substrate at one side of the patterned layer, wherein a thickness of the blocking structure is smaller than a thickness of the patterned layer. The cantilever structure is disposed on the substrate and located between the patterned layer and the blocking structure. The cantilever structure is connected with the patterned layer and the blocking structure. The connection structure is connected between the patterned layer and the substrate at one side of the patterned layer, and located on the cantilever structure and the blocking structure.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 27, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Yen-Jui Chu, Hsin-Hung Chou, Ming-Chih Tsai
  • Patent number: 10818357
    Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Haitao Liu, Changhyun Lee
  • Patent number: 10734333
    Abstract: Semiconductor packages including a lateral interconnect having an arc segment to increase self-inductance of a signal line is described. In an example, the lateral interconnect includes a circular segment extending around an interconnect pad. The circular segment may extend around a vertical axis of a vertical interconnect to introduce an inductive circuitry to compensate for an impedance mismatch of the vertical interconnect.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Khang Choong Yong, Howard Lincoln Heck
  • Patent number: 10727113
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • Patent number: 10665471
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. A core structure and a first material layer are formed on a substrate in order. A top surface of the first material layer is lower than a top surface of the core structure. A second pattern is formed on an exposed surface of the core structure. The method of forming the second pattern includes forming a second material layer on the exposed surface of the core structure and the top surface of the first material layer and performing an anisotropic etching on the second material layer. The first material layer is patterned by using the second pattern as a mask to form a first pattern. The step of forming the second material layer and the step of performing an anisotropic etching on the second material layer are performed in the same etching chamber.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 26, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Shu-Ming Li, Tzu-Ming Ou Yang, Ko-Po Tseng
  • Patent number: 10600746
    Abstract: A multi-cell transistor includes a semiconductor structure and a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor including a gate finger that extends in a first direction on the semiconductor structure. The gate fingers are spaced apart from each other along a second direction and arranged on the semiconductor structure in a plurality of groups. A first distance in the second direction between adjacent gate fingers in a first of the groups is less than a second distance in the second direction between a first gate finger that is at one end of the first group and a second gate finger that is in a second of the groups, where the second gate finger is adjacent the first gate finger.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 24, 2020
    Assignee: Cree, Inc.
    Inventors: Frank Trang, Qianli Mu
  • Patent number: 10522404
    Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 31, 2019
    Assignee: Micromaterials LLC
    Inventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung Hwang
  • Patent number: 10515895
    Abstract: A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1<y1), a top and bottom width (x2, y2) of a second conducting feature has a dimension of (x2<y2; x2=y2; or x2>y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-yuan Ting, Chung-Wen Wu, Jeng-Shiou Chen, Jang-Shiang Tsai, Jyu-Horng Shieh
  • Patent number: 10497566
    Abstract: A circuit structure comprises a plurality of first conducting lines extending in a first direction, the first conducting lines having a first pitch in a second direction orthogonal to the first direction; a plurality of linking lines extending in the second direction, the linking lines having a second pitch in the first direction, the second pitch being greater than the first pitch; and a plurality of connection structures connecting respective first conducting lines for current flow to respective linking lines, the connection structures each including a plurality of segments extending in the first direction, segments in the plurality of segments having a transition pitch in the second direction relative to adjacent segments in the plurality of segments greater than or equal to the first pitch, and less than the second pitch.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 3, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chin-Cheng Yang, Chi-Hao Huang, Wei-Hung Wang
  • Patent number: 10471718
    Abstract: Techniques are provided for making a funnel-shaped nozzle in a substrate. The process can include forming a first opening having a first width in a top layer of a substrate, forming a patterned layer of photoresist on the top surface of the substrate, the patterned layer of photoresist including a second opening, the second opening having a second width larger than the first width, reflowing the patterned layer of photoresist to form curved side surfaces terminating on the top surface of the substrate, etching a second layer of the substrate through the first opening in the top layer of the substrate to form a straight-walled recess, the straight-walled recess having the first width and a side surface substantially perpendicular to the top surface of the semiconductor substrate.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 12, 2019
    Assignee: FUJIFILM Dimatix, Inc.
    Inventors: Gregory DeBrabander, Mark Nepomnishy
  • Patent number: 10410921
    Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: September 10, 2019
    Assignee: Micromaterials LLC
    Inventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung David Hwang
  • Patent number: 10381368
    Abstract: A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kotaro Noda
  • Patent number: 10318694
    Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 11, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Joon Hyung Chung, Mikhail Popovich, Gudoor Reddy
  • Patent number: 10276539
    Abstract: A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a pillar. The semiconductor device assembly includes a semiconductor device disposed over another semiconductor device. At least one pillar extends from one semiconductor device towards a pad on the other semiconductor device. The barrier on the exterior of the pillar may be a standoff to control a bond line between the semiconductor devices. The barrier may reduce solder bridging and may prevent reliability and electromigration issues that can result from the IMC formation between the solder and copper portions of a pillar. The barrier may help align the pillar with a pad when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of the semiconductor devices. Windows or slots in the barrier may permit the expansion of solder in predetermined directions while preventing bridging in other directions.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Benjamin L. McClain, C. Alexander Ernst, Jeremy E. Minnich
  • Patent number: 10229906
    Abstract: Provided is a semiconductor device that occupies a small area, a highly integrated semiconductor device, or a semiconductor device with high productivity. To fabricate an integrated circuit, a first insulating film is formed over a p-channel transistor; a transistor including an oxide semiconductor is formed over the first insulating film; a second insulating film is formed over the transistor; an opening, that is, a contact hole part of a sidewall of which is formed of the oxide semiconductor of the transistor, is formed in the first insulating film and the second insulating film; and an electrode connecting the p-channel transistor and the transistor including an oxide semiconductor to each other is formed.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Shinya Sasagawa
  • Patent number: 10217756
    Abstract: A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: February 26, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Hui Yang, Chow-Yee Lim
  • Patent number: 10211149
    Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyoung Moo Harr, Kyung Seob Oh, Hyoung Joon Kim
  • Patent number: 10178768
    Abstract: A mounting substrate includes a substrate, a connection electrode, which is formed on a front surface of the substrate and on which an electronic component is mounted via a conductive bonding material, a resist film, formed on the front surface of the substrate so as to cover a peripheral edge portion of the connection electrode, and a receiving portion, formed in the resist film so as to expose a portion of the peripheral edge portion of the connection electrode and arranged to receive an excess portion of the conductive bonding material.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: January 8, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Katsuya Matsuura, Hiroshi Tamagawa
  • Patent number: 10090256
    Abstract: A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a top surface and a bottom surface opposite to the top surface. The stepped conductive vias are disposed at the insulating layer to electrically connect the top surface and the bottom surface. Each of the stepped conductive vias includes a head portion and a neck portion connected to the head portion. The head portion is disposed on the top surface, and an upper surface of the head portion is coplanar with the top surface. A minimum diameter of the head portion is greater than a maximum diameter of the neck portion. The patterned circuit layer is disposed on the top surface and electrically connected to the stepped conductive vias.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: October 2, 2018
    Assignee: IBIS Innotech Inc.
    Inventors: Wen-Chun Liu, Wei-Jen Lai
  • Patent number: 9922994
    Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: March 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Hodo, Motomu Kurata, Shinya Sasagawa, Satoru Okamoto, Shunpei Yamazaki
  • Patent number: 9911626
    Abstract: A method of fabricating an interposer substrate provides a carrier having a first wiring layer. The first wiring layer has a plurality of first conductive pillars. A first insulating layer is formed on the carrier. The first conductive pillars are exposed from the first insulating layer. External connection pillars are formed above the first conductive pillars and electrically connected to the first conductive pillars. Then the carrier is removed. The process of fabricating the via can be bypassed in the process by forming a coreless interposer substrate on the carrier, such that the overall cost of the process can be decreased, and the process is simple. The interposer substrate is also provided.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: March 6, 2018
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventor: Pao-Hung Chou
  • Patent number: 9876028
    Abstract: The memory string comprises: a plurality of control gate electrodes stacked on the substrate and extending in a first direction and a second direction parallel to the substrate; a semiconductor layer that has one end thereof connected to the substrate, has as its longitudinal direction a third direction perpendicular to the substrate, and faces the plurality of control gate electrodes; and a charge accumulation layer positioned between the control gate electrode and the semiconductor layer. The contact includes, in the third direction, a first portion, a second portion which is more to a substrate side than is the first portion, and a third portion which is more to the substrate side than is the second portion. A width of the second portion is larger than a width of the first portion, and larger than a width of the third portion.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Satoshi Konagai
  • Patent number: 9814135
    Abstract: A wiring board includes a substrate, pads formed on an electronic-component mounting surface of the substrate, and a resin insulation layer covering the electronic-component mounting surface and having opening portions such that the opening portions are exposing the pads, respectively. The pads include a non-solder mask defined pad having a wiring portion and a non-solder mask defined pad having no wiring portion, and the opening portions are formed such that the non-solder mask defined pads have exposed conductor areas which have substantially same areas inside the opening portions.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 7, 2017
    Assignee: IBIDEN CO., LTD.
    Inventor: Takenobu Nakamura
  • Patent number: 9799594
    Abstract: The present invention is to provide a microstructure capable of improving the withstand voltage of an insulating substrate while securing fine conductive paths, a multilayer wiring board, a semiconductor package, and a microstructure manufacturing method. The microstructure of the present invention has an insulating substrate having a plurality of through holes, and conductive paths consisting of a conductive material containing metal filling the plurality of through holes, in which an average opening diameter of the plurality of through holes is 5 nm to 500 nm, an average value of the shortest distances connecting the through holes adjacent to each other is 10 nm to 300 nm, and a moisture content is 0.005% or less with respect to the total mass of the microstructure.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: October 24, 2017
    Assignee: FUJIFILM Corporation
    Inventor: Kosuke Yamashita
  • Patent number: 9786640
    Abstract: A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 10, 2017
    Assignee: Ampleon Netherlands B.V.
    Inventors: Petra Christina Anna Hammes, Josephus Henricus van der Zanden, Rob Mathijs Heeres, Albert Gerardus Wilhelmus Philipus van Zuijlen
  • Patent number: 9704721
    Abstract: Provided are a method of forming key patterns and a method of fabricating a semiconductor device using the same. The method of forming key patterns may include forming gate and key patterns on a cell region and a scribe lane region, respectively. Here, the key patterns may be formed to have a large width and a larger pitch than those of the gate patterns.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: July 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunchang Lee, Boo-Hyun Ham, Yongkug Bae, Ja-Min Koo, Jonghwa Baek, Heeju Shin, Rankyung Jung
  • Patent number: 9659772
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a first line pattern that includes a first main line having a first width and a first subline having a second width, and a second line pattern that includes a second main line having the first width and a second subline having a third width. The first line pattern may include a first width changer whose width increases from the first width to the second width. The second line pattern may include a second width changer whose width increases from the first width to the third width.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-jun Seong, Jee-hoon Han
  • Patent number: 9610580
    Abstract: Provided in one embodiment is a dynamically tunable structure including an elastic layer, and a plurality of ferromagnetic micropillars disposed over the elastic layer. The elastic layer may have an elasticity that is greater than an elasticity of the micropillars.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: April 4, 2017
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Evelyn N. Wang, Yangying Zhu, Rong Xiao
  • Patent number: 9576888
    Abstract: A device comprises a bottom package comprising a plurality of metal bumps formed on a first side of the bottom package and a plurality of first bumps formed on a second side of the bottom package, a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps, and wherein second bumps and respective metal bumps form a joint structure and an underfill layer formed between the top package and the bottom package, wherein the metal bumps are embedded in the underfill layer.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Wei-Yu Chen, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9536848
    Abstract: Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke England, Christian Klewer
  • Patent number: 9536850
    Abstract: A package and method of making the package are provided. An embodiment package includes an integrated circuit supporting a conductive pillar, a substrate having a landing pad on each embedded metal trace, a landing pad width greater than a corresponding embedded metal trace width, and a conductive material electrically coupling the conductive pillar to the landing pad. In an embodiment, the landing pad overlaps the metal trace in one direction.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Chen-Shien Chen, Yu-Jen Tseng
  • Patent number: 9324915
    Abstract: A light-emitting device includes first and second semiconductor layers and a light-emitting layer between the first and second semiconductor layers. The light-emitting device also includes an improved electrode structures.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Steven D. Lester, Chao-Kun Lin
  • Patent number: 9299624
    Abstract: A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: March 29, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Ming Hou, Ji-Fu Kung
  • Patent number: 9257641
    Abstract: Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: February 9, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Frederick T. Chen, Tai-Yuan Wu, Yu-Sheng Chen, Wei-Su Chen, Pei-Yi Gu, Yu-De Lin
  • Patent number: 9246083
    Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: January 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kilho Lee, Ki Joon Kim, Se Woong Park
  • Patent number: 9230919
    Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: January 5, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
  • Patent number: 9196642
    Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Han Tsai, Allen Tseng, Yen-Hsung Ho, Chun-Hao Chou, Kuo-Cheng Lee, Volume Chien, Chi-Cherng Jeng
  • Patent number: 9197803
    Abstract: A camera module includes an image sensor IC, a resin multilayer board including thermoplastic resin layers stacked in a direction perpendicular or substantially perpendicular to a light receiving surface of the image sensor IC, a mounting electrode which is stacked on the thermoplastic resin layer and on which the image sensor IC is mounted, and a via-hole conductor electrically connected to the mounting electrode. The resin multilayer board includes a flat plate portion including a surface on which the mounting electrode is mounted, and a rigid portion including a greater number of thermoplastic resin layers than that of the flat plate portion, and the via-hole conductor is arranged in the flat plate portion so as to avoid the thermoplastic resin layer on which the mounting electrode is stacked.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: November 24, 2015
    Assignee: Murata Manufactruing Co., Ltd.
    Inventors: Nobuo Ikemoto, Atsushi Kumano, Jerry Hsieh, Jun Sasaki
  • Patent number: 9114993
    Abstract: A method for making one or more nanostructures is disclosed, the method comprising: depositing a conducting layer on an upper surface of a substrate; depositing a patterned layer of catalyst on the conducting layer; growing the one or more nanostructures on the layer of catalyst; and selectively removing the conducting layer between and around the one or more nanostructures. A device is also disclosed, comprising a substrate, wherein the substrate comprises one or more exposed metal islands separated by one or more insulating areas; a conducting helplayer disposed on the substrate covering at least some of the one or more exposed metal islands or insulating areas; a catalyst layer disposed on the conducting helplayer; and one or more nanostructures disposed on the catalyst layer.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: August 25, 2015
    Assignee: Smoltek AB
    Inventors: Jonas T. Berg, Vincent Desmaris, Mohammad Shafiqul Kabir, Muhammad Amin Saleem, David Brud
  • Patent number: 9105552
    Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a bump region and a tail region coupled to the bump region. The metal stud bumps are embedded in solder joints.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Hsiun Lee, Chen Yung Ching
  • Patent number: 9099471
    Abstract: A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: August 4, 2015
    Assignee: International Business Machines Corporation
    Inventors: David H. Allen, Douglas M Dewanz, David P. Paulsen, John E. Sheets, II, Kelly L. Williams
  • Patent number: 9087884
    Abstract: According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern is formed along an inner periphery of the opening of the second core pattern, the first core pattern and the second core pattern are removed, and the process target film is processed to transfer the sidewall pattern and the sidewall dummy pattern.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: July 21, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yuya Matsuda
  • Patent number: 9070834
    Abstract: A semiconductor light emitting device includes a light emitting structure, a first electrode unit, and a second electrode unit. The light emitting structure includes a first and second conductivity-type semiconductor layer, an active layer. The first electrode unit includes a first electrode pad and a first electrode finger extending from the first electrode pad, and having an annular shape with an open portion. The second electrode unit includes a second electrode pad and a second electrode finger extending from the second electrode pad, and has an annular shape with an open portion. One of the first and second electrode units substantially surrounds the other, and the center of the annular shape of at least one of the first and second electrode units is spaced apart from the center of the upper surface of the light emitting structure.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: June 30, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Sung Kim, Yong Min Kim, Dong Myung Shin, Soo Jin Jung
  • Patent number: 9041216
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Jen Sung, Yi-Nien Su
  • Patent number: 9041203
    Abstract: A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: May 26, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Zubin Patel, Nian Yang, Fan Wan Lai, Alok Nandini Roy
  • Patent number: 9041204
    Abstract: A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is formed in a second dielectric layer and disposed over the first conductive island. A second conductive island is formed in a third dielectric layer and disposed over the first via array. A bonding pad is disposed over the second conductive island. The first conductive island, the first via array, and the second conductive island are electrically connected to the bonding pad. The first via array is connected to no other conductive island in the first dielectric layer except the first conductive island. No other conductive island in the third dielectric layer is connected to the first via array except the second conductive island.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han Tsai, Jung-Chi Jeng, Yueh-Ching Chang, Volume Chien, Huang-Ta Huang, Chi-Cherng Jeng
  • Patent number: 9034755
    Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo A. Vega
  • Patent number: 9030018
    Abstract: Provided are test vehicles for evaluating various semiconductor materials. These materials may be used for various integrated circuit components, such as embedded resistors of resistive random access memory cells. Also provided are methods of fabricating and operating these test vehicles. A test vehicle may include two stacks protruding through an insulating body. Bottom ends of these stacks may include n-doped poly-silicon and may be interconnected by a connector. Each stack may include a titanium nitride layer provided over the poly-silicon end, followed by a titanium layer over the titanium nitride layer and a noble metal layer over the titanium layer. The noble metal layer extends to the top surface of the insulating body and forms a contact surface. The titanium layer may be formed in-situ with the noble metal layer to minimize oxidation of the titanium layer, which is used as an adhesion and oxygen getter.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: May 12, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Mihir Tendulkar, David Chi