Varying Width Or Thickness Of Conductor Patents (Class 257/775)
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Patent number: 9196642Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.Type: GrantFiled: December 7, 2012Date of Patent: November 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Han Tsai, Allen Tseng, Yen-Hsung Ho, Chun-Hao Chou, Kuo-Cheng Lee, Volume Chien, Chi-Cherng Jeng
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Patent number: 9114993Abstract: A method for making one or more nanostructures is disclosed, the method comprising: depositing a conducting layer on an upper surface of a substrate; depositing a patterned layer of catalyst on the conducting layer; growing the one or more nanostructures on the layer of catalyst; and selectively removing the conducting layer between and around the one or more nanostructures. A device is also disclosed, comprising a substrate, wherein the substrate comprises one or more exposed metal islands separated by one or more insulating areas; a conducting helplayer disposed on the substrate covering at least some of the one or more exposed metal islands or insulating areas; a catalyst layer disposed on the conducting helplayer; and one or more nanostructures disposed on the catalyst layer.Type: GrantFiled: September 18, 2014Date of Patent: August 25, 2015Assignee: Smoltek ABInventors: Jonas T. Berg, Vincent Desmaris, Mohammad Shafiqul Kabir, Muhammad Amin Saleem, David Brud
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Patent number: 9105552Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a bump region and a tail region coupled to the bump region. The metal stud bumps are embedded in solder joints.Type: GrantFiled: May 30, 2012Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chien-Hsiun Lee, Chen Yung Ching
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Patent number: 9099471Abstract: A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.Type: GrantFiled: March 12, 2013Date of Patent: August 4, 2015Assignee: International Business Machines CorporationInventors: David H. Allen, Douglas M Dewanz, David P. Paulsen, John E. Sheets, II, Kelly L. Williams
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Patent number: 9087884Abstract: According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern is formed along an inner periphery of the opening of the second core pattern, the first core pattern and the second core pattern are removed, and the process target film is processed to transfer the sidewall pattern and the sidewall dummy pattern.Type: GrantFiled: March 17, 2015Date of Patent: July 21, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yuya Matsuda
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Patent number: 9070834Abstract: A semiconductor light emitting device includes a light emitting structure, a first electrode unit, and a second electrode unit. The light emitting structure includes a first and second conductivity-type semiconductor layer, an active layer. The first electrode unit includes a first electrode pad and a first electrode finger extending from the first electrode pad, and having an annular shape with an open portion. The second electrode unit includes a second electrode pad and a second electrode finger extending from the second electrode pad, and has an annular shape with an open portion. One of the first and second electrode units substantially surrounds the other, and the center of the annular shape of at least one of the first and second electrode units is spaced apart from the center of the upper surface of the light emitting structure.Type: GrantFiled: April 24, 2014Date of Patent: June 30, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Sung Kim, Yong Min Kim, Dong Myung Shin, Soo Jin Jung
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Patent number: 9041204Abstract: A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is formed in a second dielectric layer and disposed over the first conductive island. A second conductive island is formed in a third dielectric layer and disposed over the first via array. A bonding pad is disposed over the second conductive island. The first conductive island, the first via array, and the second conductive island are electrically connected to the bonding pad. The first via array is connected to no other conductive island in the first dielectric layer except the first conductive island. No other conductive island in the third dielectric layer is connected to the first via array except the second conductive island.Type: GrantFiled: March 30, 2012Date of Patent: May 26, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Han Tsai, Jung-Chi Jeng, Yueh-Ching Chang, Volume Chien, Huang-Ta Huang, Chi-Cherng Jeng
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Patent number: 9041203Abstract: A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.Type: GrantFiled: October 10, 2008Date of Patent: May 26, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Zubin Patel, Nian Yang, Fan Wan Lai, Alok Nandini Roy
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Patent number: 9041216Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.Type: GrantFiled: June 19, 2013Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Patent number: 9034755Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.Type: GrantFiled: December 4, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Emre Alptekin, Reinaldo A. Vega
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Patent number: 9030018Abstract: Provided are test vehicles for evaluating various semiconductor materials. These materials may be used for various integrated circuit components, such as embedded resistors of resistive random access memory cells. Also provided are methods of fabricating and operating these test vehicles. A test vehicle may include two stacks protruding through an insulating body. Bottom ends of these stacks may include n-doped poly-silicon and may be interconnected by a connector. Each stack may include a titanium nitride layer provided over the poly-silicon end, followed by a titanium layer over the titanium nitride layer and a noble metal layer over the titanium layer. The noble metal layer extends to the top surface of the insulating body and forms a contact surface. The titanium layer may be formed in-situ with the noble metal layer to minimize oxidation of the titanium layer, which is used as an adhesion and oxygen getter.Type: GrantFiled: September 21, 2012Date of Patent: May 12, 2015Assignee: Intermolecular, Inc.Inventors: Mihir Tendulkar, David Chi
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Patent number: 9030019Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.Type: GrantFiled: December 14, 2010Date of Patent: May 12, 2015Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Ludwig Heitzer
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Patent number: 9018750Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.Type: GrantFiled: August 10, 2012Date of Patent: April 28, 2015Assignee: Flipchip International, LLCInventors: Robert Forcier, Douglas Scott
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Patent number: 9006100Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.Type: GrantFiled: August 7, 2012Date of Patent: April 14, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook Kye, Rod Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20150091191Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a stepped region.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
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Publication number: 20150091192Abstract: A semiconductor device connected by an anisotropic conductive film including a first insulation layer, a conductive layer, and a second insulation layer one above another, wherein the conductive layer has an expansion length of 20% or less in a width direction thereof, and the second insulation layer has an expansion length of 50% or more in a width direction thereof, the expansion length is calculated according to Equation 1, below, after glass substrates are placed on upper and lower sides of the anisotropic conductive film respectively, followed by compression at 110° C. to 200° C. for 3 to 7 seconds under a load of 1 MPa to 7 MPa per unit area of a sample, Increased ratio of expansion length(%)=[(length of corresponding layer in width direction after compression?length of corresponding layer in width direction before compression)/length of corresponding layer in width direction before compression]×100.Type: ApplicationFiled: September 29, 2014Publication date: April 2, 2015Inventors: Young Ju SHIN, Kyoung Ku KANG, Ji Yeon KIM, Kyoung Soo PARK, Woo Jung SHIN, Kwang Jin JUNG, Ja Young HWANG
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Patent number: 8993429Abstract: To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch.Type: GrantFiled: October 3, 2013Date of Patent: March 31, 2015Assignee: Macronix International Co., Ltd.Inventor: Shih-Hung Chen
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Patent number: 8994175Abstract: To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.Type: GrantFiled: December 24, 2013Date of Patent: March 31, 2015Assignee: Renesas Electronics CorporationInventors: Masaki Watanabe, Shinji Baba, Muneharu Tokunaga, Toshihiro Iwasaki
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Patent number: 8994189Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.Type: GrantFiled: May 12, 2014Date of Patent: March 31, 2015Assignee: Micron Technology, Inc.Inventor: Luan C. Tran
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Patent number: 8981572Abstract: To form a semiconductor device, a through electrode is formed in a semiconductor die, and a dielectric layer is then formed to cover the through electrode. The dielectric layer has an opening by being partially etched to allow the through electrode to protrude to the outside, or has a thickness thinner overall so as to allow the through electrode to protrude to the outside. Subsequently, a conductive pad is formed on the through electrode protruding to the outside through the dielectric layer by using an electroless plating method.Type: GrantFiled: September 4, 2013Date of Patent: March 17, 2015Inventors: Won Chul Do, Yong Jae Ko
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Patent number: 8970048Abstract: A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects.Type: GrantFiled: December 30, 2011Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Masahiro Inohara
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Publication number: 20150054176Abstract: Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided.Type: ApplicationFiled: October 1, 2014Publication date: February 26, 2015Inventors: Jae-Hwang Sim, Jinhyun Shin
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Publication number: 20150054177Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.Type: ApplicationFiled: October 30, 2014Publication date: February 26, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
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Patent number: 8957523Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.Type: GrantFiled: January 10, 2013Date of Patent: February 17, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Fan Zhang, Wei Shao, Juan Boon Tan, Yeow Kheng Lim, Mahesh Bhatkar, Soh Yun Siah
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Patent number: 8952538Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.Type: GrantFiled: December 22, 2010Date of Patent: February 10, 2015Assignee: Fujitsu Semiconductor LimitedInventor: Hirohisa Matsuki
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Patent number: 8952547Abstract: A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.Type: GrantFiled: July 9, 2007Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon-Jhy Liaw
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Patent number: 8946087Abstract: A method for providing metal filled features in a layer is provided. A metal seed layer is deposited on tops and bottoms of the features. Metal seed layer on tops of the features and overhangs is removed without removing metal seed layer on bottoms of features. An electroless deposition of metal is provided to fill the features, wherein the electroless deposition first deposits on the metal seed layer on bottoms of the features.Type: GrantFiled: February 2, 2012Date of Patent: February 3, 2015Assignee: Lam Research CorporationInventor: Praveen Reddy Nalla
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Patent number: 8946908Abstract: Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD.Type: GrantFiled: August 7, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 8940634Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.Type: GrantFiled: June 29, 2011Date of Patent: January 27, 2015Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc., STMicroelectronics, Inc.Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
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Publication number: 20150021790Abstract: According to one embodiment, a semiconductor device includes a first conductive line and a second conductive line including a first extension region in which the first conductive line and the second conductive line extend in a first direction, and a bend region in which the first conductive line and the second conductive line bend with respect to the first direction, a first dummy pattern and a second dummy pattern arranged on extension regions beyond the bend region of the first conductive line and the second conductive line, respectively, in the first direction, a first contact pad and a second contact pad formed beyond the bend region in the first direction, and connected to the first conductive line and the second conductive line, respectively.Type: ApplicationFiled: March 7, 2014Publication date: January 22, 2015Applicants: San Disk Corporation, KABUSHIKI KAISHA TOSHIBAInventors: Satoshi NAGASHIMA, Atsushi SHIMODA, Naoyuki IIDA
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Publication number: 20150014862Abstract: Semiconductor packages are provided. A semiconductor package may include a wiring board and a first semiconductor chip on the wiring board. Moreover, the semiconductor package may include a metal layer on the first semiconductor chip and a second semiconductor chip on the metal layer. The metal layer may be between the first and second semiconductor chips.Type: ApplicationFiled: May 29, 2014Publication date: January 15, 2015Inventors: Heungkyu Kwon, Sangho An
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Patent number: 8933343Abstract: An electronic structure includes a substrate body, an electronic package structure and a conductive unit. The electronic package structure is disposed on the substrate body. The electronic package structure includes a first inner electrode portion, a second inner electrode portion, a first outer electrode portion electrically connected to the first inner electrode portion, and a second outer electrode portion electrically connected to the second inner electrode portion. The conductive unit includes a first conductive body and a second conductive body respectively electrically contacting the first and the second outer electrode portions. The electronic package structure has a first notch and a second notch, the first outer electrode portion is extended into the first notch to contact the top surface of the first inner electrode portion, and the second outer electrode portion is extended into the second notch to contact the top surface of the second inner electrode portion.Type: GrantFiled: March 4, 2013Date of Patent: January 13, 2015Assignee: Inpaq Technology Co., Ltd.Inventors: Ming-Fung Hsieh, Yu-Chia Chang, Chun-Pin Huang, Yung-Chang Peng
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Patent number: 8927410Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.Type: GrantFiled: December 9, 2013Date of Patent: January 6, 2015Assignee: Micron Technology, Inc.Inventors: Dave Pratt, Andy Perkins
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Patent number: 8928136Abstract: A lead frame includes: a chip-mounting region provided on a front surface; a lead region including a plurality of concave and convex sections arranged in an in-plane direction of the chip-mounting region; and a terminal arranged in the concave section. A thickness of the lead region from the front surface is smaller than a thickness of the terminal from the front surface.Type: GrantFiled: October 24, 2012Date of Patent: January 6, 2015Assignee: Sony CorporationInventors: Shinji Watanabe, Akihisa Eimori
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Patent number: 8918988Abstract: Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.Type: GrantFiled: September 6, 2012Date of Patent: December 30, 2014Assignee: International Business Machines CorporationInventors: Mohammed Fazil Fayaz, Jeffery Burton Maxson, Anthony Kendall Stamper, Daniel Scott Vanslette
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Patent number: 8922010Abstract: Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.Type: GrantFiled: April 4, 2013Date of Patent: December 30, 2014Assignee: Rohm Co., Ltd.Inventors: Tadahiro Morifuji, Shigeyuki Ueda
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Patent number: 8916979Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.Type: GrantFiled: February 7, 2013Date of Patent: December 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang
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Publication number: 20140367864Abstract: A method for producing a semiconductor device includes: a process for forming a first conductor on a first interlayer insulating film provided on a semiconductor substrate, a process for forming in order a first stopper interlayer film, a second interlayer insulating film, a second stopper interlayer film, and a third interlayer insulating film on the first interlayer insulating film to cover the first conductor, a process for penetrating the third interlayer insulating film, the second stopper interlayer film, and the second interlayer insulating film, and forming a first contact hole having a first inner diameter on a position corresponding to the first conductor, a process for expanding the inner diameter of the first contact hole on the second interlayer insulating film to a second inner diameter larger than the first inner diameter, and a process for forming on the first stopper interlayer film a second contact hole.Type: ApplicationFiled: June 13, 2014Publication date: December 18, 2014Inventor: Hiroyuki FUJIMOTO
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Patent number: 8912655Abstract: When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.Type: GrantFiled: March 21, 2012Date of Patent: December 16, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Shingo Nakajima
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Patent number: 8912671Abstract: A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern.Type: GrantFiled: May 16, 2013Date of Patent: December 16, 2014Assignees: Himax Technologies Limited, Himax Semiconductor, Inc.Inventors: Po-Yang Tsai, Chan-Liang Wu
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Patent number: 8912540Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: GrantFiled: March 13, 2013Date of Patent: December 16, 2014Assignee: Renesas Electronics CorporationsInventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Patent number: 8912660Abstract: An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer located on the top surface of the semiconductor substrate. An ESD protection circuit is provided in the top layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post-shaped electrodes. First ends of the interlayer wiring lines provided in the thickness direction are connected to the input/output electrodes provided on the top surface of the semiconductor substrate and the second ends are connected to first ends of the in-plane wiring lines extending in the plane direction. The distance between the centers of the first and second post-shaped electrodes is larger than the distance between the centers of the first and second input/output electrodes.Type: GrantFiled: February 8, 2013Date of Patent: December 16, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Noboru Kato, Jun Sasaki, Kosuke Yamada
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Patent number: 8907496Abstract: Circuit structures and methods of fabrication are provided with enhanced electrical connection between, for instance, a first metal level and a contact surface of a conductive structure. Enhanced electrical connection is achieved using a plurality of contact vias which are differently-sized, and disposed over and electrically coupled to the contact surface. The differently-sized contact vias include at least one center region contact via disposed over a center region of the contact surface, and at least one peripheral region contact via disposed over a peripheral region of the contact surface, where the at least one center region contact via is larger than the at least one peripheral region contact via.Type: GrantFiled: June 4, 2013Date of Patent: December 9, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: GuoXiang Ning, Xiang Hu, Sarasvathi Thangaraju, Paul Ackmann
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Patent number: 8907493Abstract: A first through hole 16 and a second through hole 17 are formed which penetrate from a rear surface 10a side of an element formation surface 10b of a semiconductor substrate (silicon substrate 10) in which an element section Ra is formed, to the element formation surface. An outer circumference insulation film 12 is formed on the side wall of the bottom of the second through hole 17 to surround the outer circumference of the second through hole 17 having a larger opening diameter among these through holes.Type: GrantFiled: February 7, 2013Date of Patent: December 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kengo Uchida, Kazuyuki Higashi
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Patent number: 8901743Abstract: A method of fabricating a semiconductor device includes forming a first insulation film over a semiconductor substrate, the semiconductor substrate including an outer region and an inner region located at an inner side of the outer region, forming a first wiring over the first insulation film in the inner region, forming a second insulation film over the first wiring and over the first insulation film, decreasing a film thickness of the second insulation film in the inner region with regard to a film thickness of the second insulation film in the outer region, and polishing the second insulation film after the decreasing of the film thickness of the second insulation film.Type: GrantFiled: January 8, 2013Date of Patent: December 2, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Tomiyasu Saito, Tatsuya Mise, Hiromichi Ichikawa, Tetsuya Takeuchi, Genshi Okuda
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Patent number: 8901746Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.Type: GrantFiled: March 27, 2014Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jang-ho Park, Jae-kwan Park, Dong-hwa Kwak, So-wi Jin, Byung-jun Hwang, Nam-su Lim
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Patent number: 8901745Abstract: A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.Type: GrantFiled: February 20, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Hwang, Hansoo Kim, Wonseok Cho, Jaehoon Jang
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Patent number: 8901554Abstract: A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.Type: GrantFiled: May 31, 2012Date of Patent: December 2, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Hiroshi Fujiki, Yoshinori Ieda
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Patent number: 8896120Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: GrantFiled: April 27, 2010Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
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Patent number: 8890324Abstract: A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width.Type: GrantFiled: September 28, 2010Date of Patent: November 18, 2014Assignee: Freescale Semiconductor, Inc.Inventor: Thuy B. Dao