Flip Chip Patents (Class 257/778)
  • Patent number: 10304751
    Abstract: An electronic sub-module includes a leadframe, a semiconductor chip disposed on the leadframe and an encapsulation material disposed on the leadframe and on the semiconductor chip. The semiconductor chip has a first contact pad on a first main face of the semiconductor chip. The sub-module also includes a first contact element on a first main face of the electronic sub-module. The first contact element is electrically connected with the first contact pad. A surface area of the first contact element is greater than a surface area of the first contact pad.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Grassmann, Juergen Hoegerl
  • Patent number: 10287161
    Abstract: An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 14, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Xiaojie Xue, Michael J. Zylinski, Thomas M. Goida, Kathleen O. O'Donnell
  • Patent number: 10283428
    Abstract: A semiconductor package including at least one integrated circuit component, a glue material, an insulating encapsulation, and a redistribution circuit structure is provided. The glue material encapsulates the at least one integrated circuit component and has a first surface and a second surface opposite to the first surface, wherein the at least one integrated circuit component is exposed by the first surface of the glue material, and an area of the first surface is smaller than an area of the second surface. The insulating encapsulation encapsulates the glue material, wherein an interface is between the glue material and the insulating encapsulation. The redistribution circuit structure is disposed on the at last one integrated circuit component, the glue material and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the at least one integrated circuit component.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 10269774
    Abstract: In a semiconductor device, a first semiconductor chip having a main surface provided with a first terminal group including terminals, and a rear face mounted on a surface of a support. A second semiconductor chip has a main surface provided with a second terminal group including terminals, the main surface of the second semiconductor chip facing the main surface of the first semiconductor chip, and each of the terminals in the second terminal group being connected to a corresponding one of the terminals in the first terminal group of the first semiconductor chip. The first semiconductor chip is connected to an external terminal of the semiconductor device via a conductor containing a single metal.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 23, 2019
    Assignee: Socionext Inc.
    Inventor: Takashi Yamada
  • Patent number: 10269750
    Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Yian-Liang Kuo, Tsung-Fu Tsai, Ru-Ying Huang, Ming-Song Sheu, Hsien-Wei Chen
  • Patent number: 10270948
    Abstract: A substrate for a camera module includes: a first substrate; an image sensor installed on the first substrate and a memory chip installed to be embedded in the first substrate. The first substrate includes a soft substrate portion disposed at a central portion of the first substrate, and a hard substrate portion formed on upper and lower portions of the soft substrate portion, and at least a portion of the memory chip is disposed in an installation hole formed in the soft substrate portion.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Eun Lee, Jin Seon Park, Yul Kyo Chung, Chul Choi, Dae Young Jung, Seung Yeop Kook
  • Patent number: 10262899
    Abstract: A wafer has a plurality of projected dicing lines on a face side thereof, a plurality of devices formed in respective areas demarcated on the face side of the wafer by the projected dicing lines, a plurality of grooves defined in the projected dicing lines, and a molding resin laid on the devices and embedded in the grooves. An outer circumferential portion of the molding resin is removed, exposing the molding resin embedded in the grooves. The molding resin embedded in the grooves exposed on an outer circumferential portion of the wafer is detected, and a laser beam is focused at a transversely central point on the molding resin embedded in the grooves. The laser beam is applied to the molding resin along the grooves, thereby forming dividing grooves in the wafer to allow the wafer to be divided into individual devices.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: April 16, 2019
    Assignee: DISCO CORPORATION
    Inventors: Xin Lu, Atsushi Kubo
  • Patent number: 10242948
    Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 26, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Jun Mo Koo, Pandi C. Marimuthu, Yaojian Lin, See Chian Lim
  • Patent number: 10242968
    Abstract: A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 26, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Eric A. Dauler
  • Patent number: 10236244
    Abstract: Provided is a semiconductor device having a wiring structure on a semiconductor element and capable of securing high quality and high reliability in response to the desire for high-temperature operations, a large-current specification, thinner wafers, smaller device size, and reduced loss. A semiconductor device that includes an insulating circuit board; a semiconductor element implemented on the insulating circuit board; a first insulating resin layer laminated on the insulating circuit board; a copper-plated wiring which contacts the semiconductor element via a window portion formed in the first insulating resin layer, which enables contact with the semiconductor element; and a second insulating resin layer laminated so as to seal the copper-plated wiring, and a method for producing the semiconductor device are provided.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: March 19, 2019
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Keisuke Ogura
  • Patent number: 10236263
    Abstract: One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Luke England, Tanya Atanasova, Daniel Smith, Daniel Fisher, Sukeshwar Kannan
  • Patent number: 10236267
    Abstract: Forming the chip attachment system includes obtaining a chip having a bump core on a die. The method also includes obtaining an intermediate structure having a transfer pad on a substrate. The method further includes transferring the transfer pad from the substrate to the bump core such that the transfer pad becomes a solder layer on the bump core.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: March 19, 2019
    Assignee: Kyocera International, Inc.
    Inventor: Dinah Lieu
  • Patent number: 10231339
    Abstract: An electronic apparatus is provided including a substrate, a conductive land formed on a surface of the substrate, an electronic component including an electrode, at least one insulating protrusion formed on the land in an overlapping region between the land and the electrode in plan view, and a solder that bonds the electronic component to the land, the solder being formed between the electrode and the land in the overlapping region in a normal direction to the surface of the substrate.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: March 12, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takashi Nagai, Hiroyuki Kumagai
  • Patent number: 10224255
    Abstract: Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package surface and having a shielding layer surface and a plurality of openings that extends between the shielding layer surface and the plurality of electrically conductive package pads, and a plurality of electrical conductors that extends from the plurality of electrically conductive package pads and projects from the shielding layer surface. The electronic assemblies include a printed circuit board with a board surface and a plurality of electrically conductive board pads arranged on the board surface, the shielded and packaged electronic device, and an underfill dielectric layer. The methods include methods of manufacturing the electronic assemblies.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: March 5, 2019
    Assignee: NXP USA, Inc.
    Inventor: Walter Parmon
  • Patent number: 10217726
    Abstract: Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. In some embodiments, a semiconductor device comprises a substrate, a first die mounted to the substrate and including first inductors, and a second die mounted to the first die in an offset position and including second inductors. The first inductors are at an active side of the first die, and the second inductors are at an active side of the second die. At least a portion of the first inductors are proximate and inductively coupled to the second inductors. The semiconductor device further comprises a first plurality of interconnects electrically coupling the substrate to the first die, and a second plurality of interconnects electrically coupling the second die to the substrate.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 10211174
    Abstract: A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Audet, Luc G. Guerin, Richard Langlois, Stephan L. Martel, Sylvain E. Ouimet
  • Patent number: 10211143
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventor: Ravindra V. Tanikella
  • Patent number: 10204865
    Abstract: An electronic package is provided, which includes: an insulator; an electronic element embedded in the insulator and having a sensing area exposed from the insulator; and a conductive structure disposed on the insulator and electrically connected to the electronic element, thereby reducing the thickness of the overall structure.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: February 12, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chu-Chin Hu, Shih-Ping Hsu
  • Patent number: 10205298
    Abstract: A packaging structure for a four-channel integrated tunable laser array chip (100) comprises a carrier (200), a cryogenic refrigerator (300), a lens assembly (400), an isolator assembly (500), a package (600), a transition ring (700), and a thermistor. The packaging structure for the four-channel integrated tunable laser array chip (100) can realize a flexible tuning upon an active coupling of optical paths and ensure a reasonable switching of optical paths between optical assemblies, thereby improving a coupling efficiency for the optical paths and increasing a transmission distance of a digital signal. Furthermore, a design of a radio frequency circuit ensures integrity of a transmitted signal and reduces loss during the transmission.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: February 12, 2019
    Assignee: Hebei Hymax Optoelectronics Inc.
    Inventor: Chao Liu
  • Patent number: 10187998
    Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Brandon M. Rawlings, Henning Braunisch
  • Patent number: 10181458
    Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 15, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Liang Shih, Chun-Chong Chien, Hsin-Lung Chun, Te-Fang Chu
  • Patent number: 10177060
    Abstract: A chip package structure includes a substrate, a chip, an encapsulant, a plurality of solder balls and a patterned metal layer. The substrate includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the substrate. The encapsulant encapsulates the chip and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the substrate. The patterned metal layer s disposed on the encapsulant. The patterned metal layer includes at least one concave portion and at least one convex portion defined by the concave portion. The convex portion faces the encapsulant. The adhesion layer is disposed between the patterned metal layer and the encapsulant. The adhesion layer is filled in the concave portion.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: January 8, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Chi-An Wang, Hung-Hsin Hsu
  • Patent number: 10177120
    Abstract: Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. In some embodiments, a semiconductor device comprises a substrate, a first die mounted to the substrate and including first inductors, and a second die mounted to the first die in an offset position and including second inductors. The first inductors are at an active side of the first die, and the second inductors are at an active side of the second die. At least a portion of the first inductors are proximate and inductively coupled to the second inductors. The semiconductor device further comprises a first plurality of interconnects electrically coupling the substrate to the first die, and a second plurality of interconnects electrically coupling the second die to the substrate.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 10175733
    Abstract: One embodiment is directed towards a molded insulator substrate. The molded insulator substrate includes a first insulator having a first surface and a second surface. A recess in said first surface of the first insulator is configured to facilitate venting of a second insulator over exposed regions of the first surface. A first conductive terminal is exposed through the first surface. A second conductive terminal is exposed through the second surface and electrically coupled to the first terminal.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: January 8, 2019
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Randolph Cruz
  • Patent number: 10163735
    Abstract: A printed electrical connection structure includes a substrate having one or more electrical connection pads and a micro-transfer printed component having one or more connection posts. Each connection post is in electrical contact with a connection pad. A resin is disposed between and in contact with the substrate and the component. The resin has a reflow temperature less than a cure temperature. The resin repeatedly flows at the reflow temperature when temperature-cycled between an operating temperature and the reflow temperature but does not flow after the resin is exposed to a cure temperature. A solder can be disposed on the connection post or the connection pad. After printing and reflow, the component can be tested and, if the component fails, another component is micro-transfer printed to the substrate, the resin is reflowed again, the other component is tested and, if it passes the test, the resin is finally cured.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: December 25, 2018
    Assignee: X-Celeprint Limited
    Inventors: Christopher Andrew Bower, Ronald S. Cok, Matthew Meitl, Carl Ray Prevatte, Jr.
  • Patent number: 10163859
    Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 10157900
    Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Liang, Hsin-Yu Pan, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao
  • Patent number: 10134705
    Abstract: As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load. In addition, the method of manufacturing a semiconductor device includes a step of, after the first step, applying the ultrasonic waves to the ball portion while pressing the ball portion with a second load larger than the first load, thereby bonding the ball portion and the first electrode.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuko Matsubara
  • Patent number: 10128212
    Abstract: A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. A redistribution layer (RDL) structure may be coupled to the first logic die, the second logic die, and the bridge memory die. The bridge memory die may be interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die and the RDL structure. A molding compound may at least partially encapsulate the first logic die, the second logic die, and the bridge memory die.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Tieh-Chiang Wu
  • Patent number: 10128219
    Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: November 13, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Richard Saye, Takahiko Kudoh, Satyendra Singh Chauhan
  • Patent number: 10109567
    Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 10106700
    Abstract: A protection membrane-forming film (1) containing a filler, wherein the average particle size of the filler is not more than 0.4 ?m, a protection membrane-forming sheet (2), a production method and an inspection method for a workpiece or a processed product which use the film and the sheet, and a workpiece and a processed product determined as adequate products by the inspection method. The protection membrane-forming film and the protection membrane-forming sheet of the invention enable the formation of a protection membrane having excellent print legibility when subjected to print processing by laser irradiation.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: October 23, 2018
    Assignee: Lintec Corporation
    Inventors: Daisuke Yamamoto, Hiroyuki Yoneyama, Youichi Inao
  • Patent number: 10105926
    Abstract: A device and method for reinforcing, baffling or sealing a vehicle structure, comprising the steps of providing a flexible carrier and plurality of parallel strips located on opposing surfaces of the carrier.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: October 23, 2018
    Assignee: ZEPHYROS, INC.
    Inventor: Dean Quaderer
  • Patent number: 10104780
    Abstract: A flexible printed circuit board includes a thin film electrical insulation substrate made of heat-curable resin having heat resistance and electrical insulation properties, an electrically conductive pattern composed of an electric conductor formed on the thin film electrical insulation substrate in a prescribed shape, and a thin film cover lay made of heat-curable resin placed and cured on the thin film electrical insulation substrate to cover the electrically conductive pattern.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: October 16, 2018
    Assignee: RICOH COMPANY, LTD.
    Inventor: Toshiaki Nakajima
  • Patent number: 10096534
    Abstract: Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a first substrate, a high-power chip disposed on a first side of the first substrate, a thermal conductive pad disposed on a second side of the first substrate, one or more thermal conductive features formed in the first substrate, wherein the thermal conductive features thermally connect the high-power chip and the thermal conductive pad, and a heat sink attached to a surface of the thermal conductive pad, wherein the heat sink is in thermal communication with the thermal conductive pad. By having thermal conductive features formed through the first substrate to thermally connect the high-power chip and the thermal conductive pad, heat generated by the high-power chip can be effectively dissipated into the heat sink.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: October 9, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Abraham F. Yee, Jayprakash Chipalkatti, Shantanu Kalchuri
  • Patent number: 10096763
    Abstract: An elastic wave device includes elastic wave elements, each including a piezoelectric layer directly or indirectly supported by a supporting substrate and an electrode disposed in contact with the piezoelectric layer, and a highly heat-conductive member stacked on a surface of the supporting substrate, opposite to the surface supporting the piezoelectric layer, in which the thermal conductivity of the supporting substrate is higher than the thermal conductivity of the piezoelectric layer, the coefficient of linear expansion of the supporting substrate is lower than the coefficient of linear expansion of the piezoelectric layer, the highly heat-conductive member has a larger area than the surface of the supporting substrate supporting the piezoelectric layer, and the thermal conductivity of the highly heat-conductive member is higher than that of the piezoelectric layer.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: October 9, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Iwamoto
  • Patent number: 10086573
    Abstract: A liquid material application method for filling, based on a capillary action, a liquid material ejected from an ejection device, the method includes a step of preparing a plurality of cycles and allocating the cycles to the application regions, the cycles each including one ejection pulse combined with a plurality of pause pulses at a predetermined ratio, a correction amount calculation step of measuring an ejection amount at timing of a correction period that is set in advance, and calculating a correction amount of the ejection amount, and a step of adjusting a ratio of the pause pulses to one ejection pulse for one or more cycles based on the correction amount calculated in the correction amount calculation step, wherein a length of the pause pulse is set to be sufficiently shorter than a length of the ejection pulse.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: October 2, 2018
    Assignee: MUSASHI ENGINEERING, INC.
    Inventor: Kazumasa Ikushima
  • Patent number: 10083913
    Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
  • Patent number: 10083942
    Abstract: An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: September 25, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Bastien Letowski, Jean-Christophe Crebier, Nicolas Rouger, Julie Widiez
  • Patent number: 10068871
    Abstract: A semiconductor device includes a semiconductor substrate with a wiring layer formed thereon, an insulating film formed on the semiconductor substrate so as to cover the wiring layer and having a pad opening exposing a portion of the wiring layer as a pad, a front surface protection film formed on the insulating film and being constituted of an insulating material differing from the insulating film and having a second pad opening securing exposure of at least a portion of the pad, a seed layer formed on the pad, and a plating layer formed on the seed layer.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: September 4, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Motoharu Haga, Kaoru Yasuda
  • Patent number: 10050003
    Abstract: A 3DIC includes a die and a substrate. The die includes multiple bumps to provide electrical connection the substrate. The substrate includes multiple elongated contact pads. The elongated contact pads making electrical contact with the bumps and shaped to maintain alignment with the bumps over a temperature range.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: August 14, 2018
    Assignee: eSilicon Corporation
    Inventor: Javier DeLaCruz
  • Patent number: 10039188
    Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: July 31, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Yun, Francesco Carobolante, Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Lawrence D. Smith, Matthew M. Nowak
  • Patent number: 10017870
    Abstract: A method for fabricating a heat sink including providing a carbon metal composite having a plurality of metal-coated carbon fibers and a plurality of openings, the openings leading from a first side of the carbon metal composite to a second side of the carbon metal composite, disposing the carbon metal composite over a semiconductor element such that the first side of the carbon metal composite faces the semiconductor element, and bonding the carbon metal composite to the semiconductor element by means of an electroplating process, wherein a metal electrolyte is supplied to an interface between the carbon metal composite and the semiconductor element via the plurality of openings.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: July 10, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Friedrich Kroener
  • Patent number: 10014270
    Abstract: An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Min Liang, Jiun Yi Wu
  • Patent number: 10013272
    Abstract: Instead of transferring a large original file, such as a virtual-machine image file, from a source system to a target system, the original file is encoded to define a recipe file that is transferred. The recipe is then decoded to yield a duplicate of the original file on the target system. Encoding involves identifying standard blocks in the original file and including standard-block identifiers for the standard blocks in the recipe in lieu of the original blocks. Decoding involves an exchange with a standard-block identifier server system, which provides standard blocks in response to received standard-block identifiers.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 3, 2018
    Assignee: VMware, Inc.
    Inventors: Matthew Aasted, Meera Shah, Saman P. Amarasinghe, Timothy Garnett
  • Patent number: 10002837
    Abstract: A semiconductor device includes a metal member, a first semiconductor chip, a second semiconductor chip, a first solder and a second solder. A quantity of heat generated in the first semiconductor chip is greater than the second semiconductor chip. The second semiconductor chip is formed of a material having larger Young's modulus than the first semiconductor chip. The first semiconductor chip has a first metal layer connected to the metal member through a first solder at a surface facing the metal member. The second semiconductor chip has a second metal layer connected to the metal member through a second solder at a surface facing the metal member. A thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder corresponding to a part of an outer peripheral edge of the second metal layer.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: June 19, 2018
    Assignee: DENSO CORPORATION
    Inventors: Kenji Onoda, Syoichirou Oomae
  • Patent number: 9997482
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a solder stud formed over the metal pad, and the solder stud has a flat top surface parallel to a top surface of the first substrate.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Guo Lee, Yi-Chen Liu, Yung-Sheng Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
  • Patent number: 9991206
    Abstract: A package method includes disposing a chip and a plurality of solder bumps on a substrate by disposing a plurality of chip interfaces and the plurality of solder bumps on a plurality of first interfaces of the substrate respectively; forming a mold layer configured to encapsulate the chip and the plurality of solder bumps; grinding the mold layer to obtain a grinded mold layer and expose a top side of the chip; drilling the grinded mold layer to form a plurality of through holes corresponding to the plurality of solder bumps; and applying a conductive material to fill the plurality of through holes with the conductive material to form a plurality of electrical paths through the grinded mold layer and electrically couple to the plurality of solder bumps.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 5, 2018
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Lien-Chia Chang, Chih-Ming Ko, Hung-Hsin Hsu
  • Patent number: 9980367
    Abstract: An apparatus may be provided. The apparatus may comprise a substrate and a circuit board. A ball grid array structure may be disposed between the substrate and the circuit board. In addition, a stand-off structure may be disposed between the substrate and the circuit board. The stand-off structure may be adjacent to the ball grid array structure.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: May 22, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Shih Fung Perng, Weidong Xie, Nguyet-Anh Nguyen
  • Patent number: 9978658
    Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.
    Type: Grant
    Filed: November 27, 2016
    Date of Patent: May 22, 2018
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla