Flip Chip Patents (Class 257/778)
  • Patent number: 11121006
    Abstract: A semiconductor package and a manufacturing method of a semiconductor package are provided. The semiconductor package includes a device die, a redistribution structure, a heat dissipation module and a molding compound. The redistribution structure is disposed at a front side of the device die. The heat dissipation module includes a thermal interfacial layer and a metal lid. The thermal interfacial layer is in direct contact with a back side of the device die, and located between the device die and the metal lid. The molding compound is disposed between the redistribution structure and the heat dissipation module, and has a body portion and an extended portion. The device die is located in the extended portion. The body portion laterally surrounds the extended portion. The extended portion is thicker than the body portion.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 11121102
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: September 14, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jong Sik Paek, No Sun Park
  • Patent number: 11121089
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure being electrically connect to the integrated circuit die, the redistribution structure including a pad; a passive device including a conductive connector physically and electrically connected to the pad; and a protective structure disposed between the passive device and the redistribution structure, the protective structure surrounding the conductive connector, the protective structure including an epoxy flux, the protective structure having a void disposed therein.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Jui Yu, Hao-Jan Pei, Wei-Yu Chen, Chia-Lun Chang, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Patent number: 11114363
    Abstract: Electronic package arrangements and related methods are disclosed that provide one or more of improved thermal management and electromagnetic shielding. Electronic packages are disclosed that include arrangements of one or more electronic devices, overmold bodies, and heat spreaders or metal frame structures. The heat spreaders or metal frame structures may be arranged over the electronic devices to form heat dissipation paths that draw operating heat away from the electronic devices in one or more directions including above and below the electronic packages. The heat spreaders or metal frame structures may also be arranged to form electromagnetic shields that reduce crosstalk between the electronic devices within the electronic packages and to suppress unwanted emissions from either escaping or entering the electronic packages.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 7, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Deepukumar M. Nair, Robert Charles Dry, Jeffrey Dekosky
  • Patent number: 11107995
    Abstract: A novel organic compound that is effective in improving the element characteristics and reliability is provided. The organic compound, which is represented by General Formula (G1), has a structure in which a dibenzoquinazoline ring is bonded to a skeleton with a hole-transport property via one or more arylene groups. Any one of R1 to R9 in General Formula (G1) is bonded to any one of R10 to R14 in General Formula (G1-1). Note that n is any of 0 to 3; m is 1 or 2; A represents a single bond, or an arylene group; B represents a ring having a dibenzofuran skeleton, dibenzothiophene skeleton, or carbazole skeleton; and each of R1 to R15 independently represents any of hydrogen, an alkyl group, a cycloalkyl group, and an aryl group.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 31, 2021
    Inventors: Tomoka Hara, Hideko Inoue, Tatsuyoshi Takahashi, Satoshi Seo
  • Patent number: 11101840
    Abstract: A chip radio frequency package includes a substrate including a first cavity, first and second connection members, a core member, a radio frequency integrated circuit (RFIC) disposed on an upper surface of the substrate, and a first front-end integrated circuit (FEIC) disposed in the first cavity. The core member includes a core insulating layer and a core via that penetrates the core insulating layer. The first connection member has a structure in which a first insulating layer and a first wiring layer are stacked. The second connection member has a second structure in which a second insulating layer and a second wiring layer are stacked. The RFIC inputs or outputs a base signal and a first radio frequency (RF) signal having a frequency higher than a frequency of the base signal, and the first FEIC inputs or outputs the first RF signal and a second RF signal.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 24, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hak Gu Kim, Ho Kyung Kang, Seong Jong Cheon, Young Sik Hur, Jin Seon Park, Yong Duk Lee
  • Patent number: 11094665
    Abstract: A chip package structure, comprises a first chip having a plurality of first chip joints at a lower side thereof; a circuit board below the first chip; an upper side of the circuit board being arranged with a plurality of circuit board joints; in packaging, the first chip joints being combined with the circuit board joints of the circuit board so that the first chip is combined to the circuit board by a way of ACF combination or convex joint combination; and wherein in the ACF combination, ACFs are used as welding points to be combined to the pads at another end so that the chip is combined to the circuit board; and wherein in the convex pad combination, a convex pad is combined with a flat pad by chemically methods or physical methods; and these pads are arranged on the circuit board and the first chip.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 17, 2021
    Inventor: Shih-Chi Chen
  • Patent number: 11081418
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 3, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11081456
    Abstract: In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 3, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rafael Jose Lizares Guevara, Aniceto Tabangcura Rabilas, Jr., Ray Fredric Solis de Asis, Sylvester Tigno Sanchez, Alvin Lopez Andaya
  • Patent number: 11075133
    Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
  • Patent number: 11069562
    Abstract: A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chiang Chen, Chun-Ting Wu, Ching-Hou Su, Chih-Pin Wang
  • Patent number: 11069666
    Abstract: A semiconductor package includes a frame having a through-hole, and a first semiconductor chip disposed in the through-hole of the frame and having an active surface on which a connection pad is disposed, an inactive surface opposing the active surface, and a side surface connecting the active and inactive surfaces. A first encapsulant covers at least a portion of each of the inactive surface and the side surface of the first semiconductor chip. A connection structure has a first surface having disposed thereon the active surface of the first semiconductor chip, and includes a redistribution layer electrically connected to the connection pad of the first semiconductor chip. A first passive component is disposed on a second surface of the connection structure opposing the first surface, the first passive component being electrically connected to the redistribution layer and having a thickness greater than a thickness of the first semiconductor chip.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chui Kyu Kim, Dae Hyun Park, Jung Ho Shim, Jae Hyun Lim, Mi Ja Han, Sang Jong Lee, Han Kim
  • Patent number: 11071207
    Abstract: The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 20, 2021
    Assignee: IMBERATEK, LLC
    Inventors: Risto Tuominen, Petteri Palm
  • Patent number: 11069638
    Abstract: An electronic component includes a circuit substrate, a connecting electrode, a micro-element, and a solder. The connecting electrode is located on the circuit substrate. The connecting electrode has a first transparent conductive layer. A surface of the first transparent conductive layer is located opposite the circuit substrate, and has a plurality of micrometers or nanometer particles. The micro-element is electrically connected to the connecting electrode. The solder is located between the connecting electrode and the micro-element, and fixes the micro-element on the connecting electrode.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: July 20, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Cheng Liu, Ho-Cheng Lee, Chung-Chan Liu
  • Patent number: 11050792
    Abstract: A method performed by an endpoint connected to a network. The method includes computing a security score for the endpoint and providing the security score and a requested domain name to a domain name service (DNS) resolver using a DNS request. The endpoint obtains a DNS response including an Internet Protocol (IP) address resolved by the DNS resolver based on the security score and the requested domain name. The endpoint then accesses the IP address obtained from the DNS resolver.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: June 29, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventor: Premkrishnan Venkatasubramanian
  • Patent number: 11043439
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 22, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11043449
    Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, and having the active surface disposed on the connection structure to face the connection structure, and an encapsulant covering at least a portion of the semiconductor chip, wherein the semiconductor chip includes a groove formed in the active surface, and the groove has a shape in which a width of a region of at least a portion of an internal region located closer to a central portion of the semiconductor chip than the active surface is greater than a width of an entrance region.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Woo Myung, Ha Kyeong Lee, Hyun Mi Kang
  • Patent number: 11043464
    Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 22, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jong Sik Paek, Doo Hyun Park
  • Patent number: 11037971
    Abstract: There are provided a fan-out sensor package and an optical fingerprint sensor module including the same. The fan-out sensor package includes: a connection member having a 5 through-hole; an image sensor disposed in the through-hole of the connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the connection member, the image sensor, and 10 an optical lens; and a redistribution layer disposed on the connection member, the image sensor, and the optical lens. The connection member includes a wiring layer, and the redistribution layer electrically connects the wiring layer and the connection pads to each other.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Ho Baek, Jung Hyun Cho, Min Keun Kim, Young Sik Hur, Tae Hee Han
  • Patent number: 11018067
    Abstract: In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 25, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Kyeong Tae Kim, Yi Seul Han, Jae Beom Shim, Tae Yong Lee
  • Patent number: 11018105
    Abstract: A semiconductor device includes a semiconductor chip, a bump contract, and encapsulating layer, an insulating layer, and a connection terminal.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 25, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Masanori Onodera, Junichi Kasai
  • Patent number: 10992024
    Abstract: A system comprising synchronization circuitry, a first interrogator, and a second interrogator. The first interrogator includes a transmit antenna; a first receive antenna, and circuitry configured to generate, using radio-frequency (RF) signal synthesis information received from the synchronization circuitry, a first RF signal for transmission by the transmit antenna, and generate, using the first RF signal and a second RF signal received from a target device by the first receive antenna, a first mixed RF signal indicative of a distance between the first interrogator and the target device. The second interrogator includes a second receive antenna, and circuitry configured to generate, using the RF signal synthesis information, a third RF signal; and generate, using the third RF signal and a fourth RF signal received from the target device by the second receive antenna, a second mixed RF signal indicative of a distance between the second interrogator and the target device.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 27, 2021
    Assignee: Humatics Corporation
    Inventors: Gregory L. Charvat, David A. Mindell
  • Patent number: 10973128
    Abstract: The flexible printed circuit includes a first insulator including a first insulating layer, a second insulator including a second insulating layer, and a wiring layer formed of a conductive material. Each of the first insulator and the second insulator meets IEC 60950. The flexible printed circuit includes a region where insulation of the wiring layer is required, the region is hermetically sealed by the first insulator and the second insulator.
    Type: Grant
    Filed: August 4, 2018
    Date of Patent: April 6, 2021
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Hiroki Kasugai
  • Patent number: 10964616
    Abstract: A semiconductor package structure includes a first semiconductor die, an encapsulant surrounding the first semiconductor die, and a redistribution layer (RDL) electrically coupled to the first semiconductor die. The encapsulant has a first surface over the first semiconductor die and a second surface under the first semiconductor die. The RDL has a first portion under the first surface of the encapsulant and a second portion over the first surface of the encapsulant.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 30, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10937709
    Abstract: A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 2, 2021
    Assignee: Infineon Technologies AG
    Inventors: Carlo Marbella, Kheng-Jin Chan
  • Patent number: 10937743
    Abstract: A method includes forming an interposer, which includes a semiconductor substrate, and an interconnect structure over the semiconductor substrate. The method further includes bonding a device die to the interposer, so that a first metal pad in the interposer is bonded to a second metal pad in the device die, and a first surface dielectric layer in the interposer is bonded to a second surface dielectric layer in the device die. The method further includes encapsulating the device die in an encapsulating material, forming conductive features over and electrically coupling to the device die, and removing the semiconductor substrate. A part of the interposer, the device die, and portions of the conductive features in combination form a package.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Chih-Chia Hu, Chen-Hua Yu
  • Patent number: 10937761
    Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Ming Hung, Meng-Jen Wang, Tsung-Yueh Tsai, Jen-Kai Ou
  • Patent number: 10921727
    Abstract: An exposure head configured to expose a photosensitive drum to light includes a circuit board on which a plating layer is formed, a semiconductor chip, which is provided on the plating layer, and includes a light emitting element configured to emit the light for exposing the photosensitive drum, a lens array configured to condense the light emitted from the light emitting element onto the photosensitive drum, and a housing to which the lens array and the circuit board are fixed, wherein the plating layer and a part of the housing abut against each other in an optical axis direction of the lens array, and wherein the light emitting element and the lens array are opposed to each other in the optical axis direction.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 16, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hidefumi Yoshida
  • Patent number: 10916459
    Abstract: A holding table for holding a wafer includes plural pins, and a wafer holding surface includes the tips of the plural pins. Therefore, small dust enters between the pins and thus is less readily left between the wafer holding surface and the wafer. Therefore, when the wafer is sucked and held, a gap is less readily made between the wafer holding surface and the wafer. Thus, the occurrence of the situation in which the wafer is held in a waving state is suppressed. For this reason, when a liquid resin is pushed to spread over the lower surface of the wafer, an air bubble enters less readily between the liquid resin and the wafer. This can suppress entry of the air bubble in a protective member obtained by curing the liquid resin.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 9, 2021
    Assignee: DISCO CORPORATION
    Inventor: Shinichi Namioka
  • Patent number: 10916688
    Abstract: A light emitting diode includes: a light emitting structure including a first semiconductor layer, a light emitting layer, a second semiconductor layer; a first metal layer arranged on at least a portion of the first semiconductor layer and in contact with the first semiconductor layer; and an electrode layer arranged over the light emitting structure, and having a first electrode layer and a second electrode layer. The first electrode layer is electrically coupled to the first and second semiconductor layers; the second electrode layer is configured for bonding with a package substrate, and includes a first and second bonding regions; the first bonding region is electrically coupled to the first semiconductor layer; the second bonding region is electrically coupled to the second semiconductor layer; and the first metal layer is not overlapped with the first bonding region of the second bonding region in a vertical direction.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 9, 2021
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Anhe He, Suhui Lin, Jiansen Zheng, Kangwei Peng, Xiaoxiong Lin, Chenke Hsu
  • Patent number: 10916448
    Abstract: The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: February 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sadia Naseem, Vikas Gupta
  • Patent number: 10910287
    Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Yun Liu, David Gani
  • Patent number: 10903391
    Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: January 26, 2021
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur
  • Patent number: 10879443
    Abstract: The present disclosure provides an LED package structure, a carrier, and a method for manufacturing a carrier. The carrier includes a substrate and an electrode layer disposed on the substrate. The electrode layer includes at least one bonding portion that has a plurality of elongated microstructures recessed in a surface thereof.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: December 29, 2020
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chen-Hsiu Lin, Yu-Yu Chang
  • Patent number: 10872875
    Abstract: A method for bonding a semiconductor package includes loading a semiconductor chip on a substrate, and bonding the semiconductor chip to the substrate by using a bonding tool, the bonding tool including a pressing surface for pressing the semiconductor chip, and an inclined surface extending from one side of the pressing surface. Bonding the semiconductor chip to the substrate includes deforming a bonding agent disposed between the substrate and the semiconductor chip by pressing the bonding tool, and deforming the bonding agent includes generating a fillet by protruding a portion of the bonding agent beyond the semiconductor chip, and growing the fillet in such a way that a top surface of the fillet is grown in an extending direction of the inclined surface.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghoon Lee, Jiwon Shin, Hyunggil Baek, Minkeun Kwak, Jongho Lee
  • Patent number: 10867952
    Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a top surface of the semiconductor substrate; a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively; a first bump disposed between the polymeric pad and the first pad; and a second bump disposed between the active pad and the second pad; wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad. Further, a method of manufacturing the semiconductor structure is disclosed. The method includes providing a circuit board; and forming a polymeric pad and an active pad on a surface of the circuit board, wherein a first thickness of the polymeric pad is substantially greater than a second thickness of the active pad.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu
  • Patent number: 10867973
    Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 10867934
    Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel IP Corporation
    Inventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas
  • Patent number: 10867950
    Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The plurality of solder-including electrodes include at least one gap control electrode. The at least one gap control electrode includes a columnar metal layer and a solder layer in order named from side on which the chip body is disposed, and includes an overlap region where the columnar metal layer and the solder resist layer overlap each other, along part or all of an aperture end of the aperture.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: December 15, 2020
    Assignee: SONY CORPORATION
    Inventors: Makoto Murai, Yuji Takaoka
  • Patent number: 10867957
    Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hung-Jen Lin
  • Patent number: 10868218
    Abstract: There is provided an apparatus including a semiconductor light emitting device formed on a surface of a substrate including a first electrode and a plurality of second electrodes formed adjacent to the first electrode in planar view, a base including an opposite surface facing the surface of the substrate, wherein a third electrode corresponding to the first electrode in positional relationship and a fourth electrode corresponding to the plurality of second electrodes in positional relationship are formed on the opposite surface, first connecting bodies electrically connecting the first electrode with the third electrode, and a second connecting body electrically connecting the plurality of second electrodes with the fourth electrode. The plurality of second electrodes (100) have a belt-like planer shape and centerlines respectively bisecting widths of the plurality of second electrodes are substantially parallel in planar view.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 15, 2020
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventor: Kosuke Sato
  • Patent number: 10867880
    Abstract: A multi-die module includes a first die with a first substrate and a first device formed over the first substrate, wherein the first substrate includes a cavity on a side opposite the first device. The multi-die module also includes a second die with a second substrate and a second device formed over the second substrate, wherein the second die is positioned at least partially in the cavity. The multi-die module also includes a coupler configured to convey signals between the first device and the second device.
    Type: Grant
    Filed: December 23, 2018
    Date of Patent: December 15, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Bichoy Bahr, Baher Haroun
  • Patent number: 10861835
    Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih Ting Lin, Shin-Puu Jeng
  • Patent number: 10856412
    Abstract: A substrate is disclosed. In an embodiment, a substrate includes a ceramic main body, an organic surface structure on at least one first outer face of the ceramic main body and outer redistribution layers integrated into the organic surface structure.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: December 1, 2020
    Assignee: TDK ELECTRONICS AG
    Inventors: Thomas Feichtinger, Katharina Tauber, Roman Geier
  • Patent number: 10854561
    Abstract: A semiconductor package includes: a connection member including a plurality of connection pads and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant sealing the semiconductor chip; a passivation layer disposed on the connection member; a plurality of under bump metallurgy (UBM) pads disposed on the passivation layer; and a plurality of UBM vias connecting the plurality of UBM pads to the plurality of connection pads, respectively, wherein the plurality of UBM pads include a first UBM pad overlapped with the semiconductor chip in a stacking direction, and a second UBM pad located outside of the overlapped region, and the first connection pad has an area larger than an area of an associated first UBM pad while the associated first UBM pad is overlapped in the stacking direction, and has an area larger than an area of the second connection pad.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mi Jin Park, Ji Eun Park, Job Ha
  • Patent number: 10856414
    Abstract: A printed circuit board includes a circuit trace and a connector pad. The connector pad provides electrical and mechanical mounting of a connector lead of a surface mount device and provides a circuit path between the surface mount device and the circuit trace. The connector pad includes 1) a connector pad base electrically coupled to the circuit trace, and 2) a first connector pad island electrically isolated from the connector pad base. The connector pad base has a length that is substantially equal to a length of a contact portion of the connector lead.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: December 1, 2020
    Assignee: Dell Products, L.P.
    Inventors: Chun-Lin Liao, Ching-Huei Chen, Bhyrav M. Mutnury
  • Patent number: 10847699
    Abstract: An optical semiconductor apparatus includes: an optical semiconductor device including a translucent support substrate; a buffer layer on the support substrate, a seal ring in a frame shape provided in an outer region on the buffer layer, an active layer provided on an inner region of the buffer layer, and an electrode provided on the active layer. The optical semiconductor apparatus further including: a package substrate on which the optical semiconductor device is mounted; and a sealing part that seals a space between the seal ring and the package substrate.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 24, 2020
    Assignee: NIKKISO CO., LTD.
    Inventors: Shoichi Niizeki, Hiroyasu Ichinokura
  • Patent number: 10847492
    Abstract: The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jyun-Lin Wu, Liang-Chen Lin, Shiang-Ruei Su
  • Patent number: 10847694
    Abstract: A display substrate comprises a base board and a first bonding pad. The base board comprises a first surface having a first bonding district. The first bonding pad is disposed on the first surface. The first bonding pad is configured to electrically connect to a first electrode of a light emitting component in the first bonding district. The first bonding pad comprises a main bonding portion and an auxiliary bonding portion, wherein at least a part of an orthogonal projection of the main bonding portion on the base board is in the first bonding district. The auxiliary bonding portion electrically connects to the main bonding portion, wherein at least a part of an orthogonal projection of the auxiliary bonding portion on the base board is outside the first bonding district. There is a gap between the main bonding portion and the auxiliary bonding portion.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 24, 2020
    Assignee: PLAYNITRIDE INC.
    Inventors: Yu-Chu Li, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Ying-Tsang Liu
  • Patent number: 10832990
    Abstract: The present invention provides a semiconductor device capable of being miniaturized and preventing reduction of mountability to a wiring substrate. The semiconductor device includes a conductive support having a support surface and a mounting surface facing opposite sides in a thickness direction z, and an end surface intersecting with the mounting surface and facing outside; a semiconductor element having an element back surface facing the support surface and an electrode formed on the element back surface, in which the electrode is connected to the support surface; and an external terminal conducted to the mounting surface and exposed to the outside; wherein the external terminal includes a Ni layer having P and an Au layer, and respectively connected to and laminated with at least one portion of each of the mounting surface and the end surface.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: November 10, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Mamoru Yamagami