Flip Chip Patents (Class 257/778)
  • Patent number: 10720381
    Abstract: To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toyokazu Shibata
  • Patent number: 10714488
    Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Han Huang, Chih-Hung Hsieh
  • Patent number: 10714442
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Hsuan-Ting Kuo, Tsung-Yuan Yu, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10707395
    Abstract: A flip-chip LED chip includes: a substrate; a first semiconductor layer; a light emitting layer; a second semiconductor layer; a local defect region over part of the second semiconductor layer and extending downward to the first semiconductor layer; first and second metal layers respectively over portions of the first and second semiconductor layers; an insulating layer covering the first and second metal layers, the second and first semiconductor layers in the local defect region. The insulating layer has opening structures over the first and second metal layers respectively; a eutectic electrode structure over the insulating layer with openings and including first and second eutectic layers from bottom up at a vertical direction, and including first-type and second-type electrode regions at a horizontal direction. The second eutectic layer does not overlap with the first and second metal layers at the vertical direction.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: July 7, 2020
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Anhe He, Suhui Lin, Jiansen Zheng, Kangwei Peng, Xiaoxiong Lin, Chenke Hsu
  • Patent number: 10703067
    Abstract: A device and method for reinforcing, baffling or sealing a vehicle structure, comprising the steps of providing a flexible carrier and plurality of parallel strips located on opposing surfaces of the carrier.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 7, 2020
    Assignee: ZEPHYROS, INC.
    Inventor: Dean Quaderer
  • Patent number: 10707142
    Abstract: A semiconductor package including at least one integrated circuit component and a glue material is provided. The at least one integrated circuit component has a top surface with conductive terminals and a backside surface opposite to the top surface. The glue material encapsulates the at least one integrated circuit component, wherein a first lateral thickness of the glue material is smaller than a second lateral thickness of the glue material, the second lateral thickness is parallel to the first lateral thickness, and the first lateral thickness is substantially coplanar with the top surface.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 10699984
    Abstract: A semiconductor module includes a substrate composed of electrically insulating material. A structured metal layer for contact with an electrical component is applied to a top side of the substrate. The structured metal layer is applied to the substrate only in a central region of the substrate, so that an edge region which surrounds the central region and in which the structured metal layer is not applied to the substrate remains on the top side of the substrate. A contact layer for making contact with a cooling body is situated opposite the structured metal layer and applied to a bottom side of the substrate in the central region. A structured supporting structure is further applied to the bottom side of the substrate in the edge region and has a thickness which corresponds to a thickness of the contact layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 30, 2020
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Stephan Neugebauer, Stefan Pfefferlein, Ronny Werner
  • Patent number: 10692807
    Abstract: A chip-on-film (COF) package structure includes a first COF and a second COF. The first COF includes a first flexible substrate having a first external terminal and a first internal terminal opposite to each other, first outer leads disposed at the first external terminal, first inner leads disposed at the first internal terminal, and a first chip disposed between the first external terminal and the first internal terminal. The second COF includes a second flexible substrate having a second external terminal and a second internal terminal opposite to each other, second outer leads disposed at the second external terminal, second inner leads disposed at the second internal terminal, and a second chip disposed between the second external terminal and the second internal terminal. The first COF is partially overlapped with the second COF. A display device having the COF package structure is also provided.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 23, 2020
    Assignee: Au Optronics Corporation
    Inventors: Chang-Hui Wu, Yu-Huei Jiang, Hsiao-Chung Cheng
  • Patent number: 10672625
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Sergio A. Chan Arguedas, Joshua D. Heppner, Jimin Yao
  • Patent number: 10672732
    Abstract: An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 2, 2020
    Assignee: Cerebras Systems Inc.
    Inventor: Jean-Philippe Fricker
  • Patent number: 10665574
    Abstract: A semiconductor package includes a bottom package having a lower substrate and a lower semiconductor chip mounted on the lower substrate, an interposer substrate on the bottom package, a first top package and a second top package that are mounted on the interposer substrate, and a heat spreader that is interposed between the first top package and the second top package and separates the first and second top packages from each other. The heat spreader is adhered to the interposer substrate through a plurality of first connection terminals.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunhyeok Im, Kyoung-Min Lee, Kyungsoo Lee, Horang Jang
  • Patent number: 10665518
    Abstract: The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 26, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kunihiro Komiya
  • Patent number: 10651107
    Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a heat dissipation plate including a first region and a second region, a first element disposed on the heat dissipation plate in the first region, and a second element disposed on the heat dissipation plate in the second region. The first element includes a first substrate, the second element includes a second substrate, the first substrate includes a material different from a material of the second substrate, the first substrate contacts the heat dissipation plate, and the second element is bonded to the heat dissipation plate in a flip-chip bonding manner.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 12, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyung Seok Lee, Zin-Sig Kim, Sung-Bum Bae
  • Patent number: 10651055
    Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jen Lin, Tsung-Ding Wang, Chien-Hsun Lee
  • Patent number: 10651365
    Abstract: An electrical contact structure and a method for forming the electrical contact structure are provided. The method includes forming a thin film material layer on a substrate, forming a first barrier layer on the thin film material layer and forming a metal layer on the first barrier layer. The method further includes patterning the metal layer to form a metal pattern, forming a spacer on a sidewall of the metal pattern and covering a portion of the first barrier layer. The method further includes etching the first barrier layer, wherein the portion of the first barrier layer located under the spacer is not completely etched. The method further includes removing the spacer and exposing the sidewall of the metal pattern to form an electrical contact structure on the thin film material layer, wherein the first barrier layer has a protrusion part exceeding the sidewall of the metal pattern.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: May 12, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chien-Hui Li, Chien-Hsun Wu, Yung-Hsiang Chen
  • Patent number: 10629558
    Abstract: An electronic device includes a first dielectric layer, a second dielectric layer and at least one first stud bump. The second dielectric layer is disposed on the first dielectric layer. The first stud bump is disposed in the first dielectric layer and the second dielectric layer. The first stud bump includes a bump portion and a stud portion, and the stud portion is disposed on the bump portion.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10629579
    Abstract: A package includes an interposer, which includes a core dielectric material, a through-opening extending from a top surface to a bottom surface of the core dielectric material, a conductive pipe penetrating through the core dielectric material, and a device die in the through-opening. The device die includes electrical connectors. A top package is disposed over the interposer. A first solder region bonds the top package to the conductive pipe, wherein the first solder region extends into a region encircled by the conductive pipe. A package substrate is underlying the interposer. A second solder region bonds the package substrate to the interposer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jiun Yi Wu
  • Patent number: 10629454
    Abstract: In one or more embodiments, a semiconductor package device includes a substrate, a trace, a structure, a barrier element and an underfill. The substrate has a first surface including a filling region surrounded by the trace. The structure is disposed over the filling region and electrically connected to the substrate. The barrier element is disposed on the trace. The underfill is disposed on the filling region.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chang-Lin Yeh
  • Patent number: 10626301
    Abstract: A light emitting device is manufactured by bonding an LED element on a wiring board using an anisotropic conductive adhesive. In the manufacture, the anisotropic conductive adhesive is disposed on the wiring board, and the LED element is disposed thereon. A polymerizable epoxy-modified silicone resin and a metal chelate compound are contained in the anisotropic conductive adhesive in advance. A pressing unit is pressed against the LED element for a certain pressing time, while the temperature of the wiring board is kept at 160° C. or higher and 210° C. or lower, and the temperature of the pressing unit is set lower than that of the wiring board. Since the reaction between the epoxy-modified silicone resin and the metal chelate compound occurs at a low temperature, the LED element is temporarily connected to the wiring board without collapse of a fluorescent layer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: April 21, 2020
    Assignee: DEXERIALS CORPORATION
    Inventor: Norio Umetsu
  • Patent number: 10615321
    Abstract: A light emitting diode package includes: at least one light emitting diode chip; a housing on which the at least one light emitting diode chip is mounted, the housing being open at at least one surface thereof to allow light emitted from the at least one light emitting diode chip to be discharged through the open surface of the housing; and a plurality of pads disposed on a second surface of the housing different from a first surface of the housing through which light is discharged, the plurality of pads being electrically connected to the at least one light emitting diode chip, wherein the housing has a plurality of grooves formed on a third surface thereof adjacent to the second surface.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 7, 2020
    Assignee: SEOUL SEMICONDUCTOR CO., LTD.
    Inventors: Seung Ri Choi, Hyuck Jun Kim, Se Min Bang, Do Choul Woo, Se Won Tae
  • Patent number: 10607964
    Abstract: A semiconductor device includes a semiconductor chip in which a first bump is provided on a first surface, a plurality of first adhesives are provided on the first surface of the semiconductor chip, and a second adhesive is provided on the first surface of the semiconductor chip, and of which a layout area on the first surface is smaller than a layout area of the plurality of first adhesives. In comparison to a first adhesive that is farthest from the center or a moment of inertia of the first surface of the semiconductor chip among the plurality of the first adhesives, the second adhesive is provided farther from the center or the moment of inertia of the semiconductor chip.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: March 31, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Fukayama, Yukifumi Oyama, Keisuke Taniguchi
  • Patent number: 10593621
    Abstract: A semiconductor device includes an interconnect substrate, an interconnect trace disposed on an upper surface of the interconnect substrate, a semiconductor chip mounted on the upper surface of the interconnect substrate, an adhesive resin layer disposed between the upper surface of the interconnect substrate and a lower surface of the semiconductor chip to bond the interconnect substrate and the semiconductor chip, the adhesive resin layer including an opening at a bottom of which an upper surface of the interconnect trace is situated, a barrier layer covering a sidewall of the opening, and conductive paste disposed inside the opening, wherein an electrode terminal of the semiconductor chip situated at the lower surface thereof is disposed inside the opening, with the conductive paste filling a space between the barrier layer and the electrode terminal.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: March 17, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Keigo Sato, Hiroshi Taneda
  • Patent number: 10593853
    Abstract: A method for binding a micro device on a substrate is provided. The method includes forming a conductive pad on the substrate; forming an elevated bonding layer on the conductive pad; lowering a temperature of the elevated bonding layer in an environment comprising a vapor such that at least a portion of the vapor is condensed to form a liquid layer on the elevated bonding layer; disposing the micro device over the elevated bonding layer such that the micro device is in contact with the liquid layer and is gripped by a capillary force produced by the liquid layer between the micro device and the elevated bonding layer, wherein the micro device comprises an electrode facing the elevated bonding layer; and evaporating the liquid layer such that the electrode is bound to the elevated bonding layer and is in electrical connection with the conductive pad.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 17, 2020
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10584028
    Abstract: A production method includes providing a semiconductor substrate with a wiring layer stack having cutouts on a first main surface region of the semiconductor substrate at which MEMS components are arranged in an exposed manner in the cutouts and projecting through contact elements are arranged at metallization regions of the wiring layer stack; applying a b-stage material layer cured in an intermediate stage on the wiring layer stack, such that the cutouts are covered by the b-stage material layer and the vertically projecting through contact elements are introduced into the b-stage material layer; curing the b-stage material layer to obtain a cured b-stage material layer; thinning the cured b-stage material layer; and applying a redistribution layer (RDL) structure on the thinned, cured b-stage material layer to obtain an electrical connection between the wiring layer stack and the RDL structure via the through contact elements.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 10, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Matthias Steiert, Christian Geissler, Karolina Zogal
  • Patent number: 10580717
    Abstract: A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Boxi Liu, Hemanth K. Dhavaleswarapu, Syadwad Jain, James C. Matayabas, Jr.
  • Patent number: 10580763
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 3, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Patent number: 10573588
    Abstract: A package substrate and a semiconductor package are provided. The package substrate including a substrate body having a first surface on which a semiconductor chip is mounted and a second surface opposite to the first surface, and a conductive pad at the first surface, the conductive pad elongated in a first direction, the conductive pad including a plurality of sub-bar patterns spaced apart from each other in the first direction may be provided.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hohyeuk Im
  • Patent number: 10572622
    Abstract: This application discloses a computing system to export route data and connectivity data from a layout design of a package device. The route data describes a structure of an interconnect in the package device. The connectivity data characterizes an electrical interface between a first integrated circuit and the package device in the layout design. The computing system, based on the connectivity data associated with the first integrated circuit, can correlate the route data to pins of a second integrated circuit and identify net names for the route data and the second integrated circuit. The computing system can import the route data and the connectivity data to the layout design, which selectively realigns the route data in the layout design with the pins in the second integrated circuit, and also can allow the computing system to change net names corresponding to the route data connecting to the second integrated circuit.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 25, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Frank Bader, John Medina
  • Patent number: 10566320
    Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: February 18, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Liang Shih, Chun-Chong Chien, Hsin-Lung Chung, Te-Fang Chu
  • Patent number: 10559541
    Abstract: A semiconductor package includes: a connection member including a plurality of connection pads and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant sealing the semiconductor chip; a passivation layer disposed on the connection member; a plurality of under bump metallurgy (UBM) pads disposed on the passivation layer; and a plurality of UBM vias connecting the plurality of UBM pads to the plurality of connection pads, respectively, wherein the plurality of UBM pads include a first UBM pad overlapped with the semiconductor chip in a stacking direction, and a second UBM pad located outside of the overlapped region, and the first connection pad has an area larger than an area of an associated first UBM pad while the associated first UBM pad is overlapped in the stacking direction, and has an area larger than an area of the second connection pad.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mi Jin Park, Ji Eun Park, Job Ha
  • Patent number: 10525707
    Abstract: A liquid ejecting head includes a flow path forming substrate, a vibration plate that is formed on one surface side of the flow path forming substrate, a plurality of piezoelectric elements that are provided on the vibration plate, a protective substrate that is bonded to the one surface side of the flow path forming substrate and has a flow path, a flow path member that is bonded to a side of the protective substrate opposite to the flow path forming substrate, a drive circuit that is mounted in a space formed so as to be surrounded by the flow path forming substrate, the protective substrate, and the flow path member, a filler that is filled between the drive circuit and the protective substrate, and a protective film that is formed on an inner wall, in which the protective film has an exposure hole exposing a surface of the filler.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 7, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Masao Nakayama, Shunya Fukuda, Eiju Hirai, Shiro Yazaki, Hajime Nakao
  • Patent number: 10529644
    Abstract: A semiconductor device and a method of making the same. The device includes an electrically conductive heat sink having a first surface. The device also includes a semiconductor substrate. The device further includes a first contact located on a first surface of the substrate. The device also includes a second contact located on a second surface of the substrate. The first surface of the substrate is mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the substrate is mountable on a surface of a carrier.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: January 7, 2020
    Assignee: Nexperia B.V.
    Inventors: Shun Tik Yeung, Pompeo Umali, Hans-Juergen Funke, Chi Ho Leung, Wolfgang Schnitt, Zhihao Pan
  • Patent number: 10522440
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a first encapsulant, a second encapsulant, a protection layer, a RDL structure and a connector. The first encapsulant is aside a first sidewall of the die, at least encapsulating a portion of the first sidewall of the die. The second encapsulant is aside a second sidewall of the die, encapsulating the second sidewall of the die. The protection layer is aside the first sidewall of the die and on the first encapsulant. The RDL structure is on a first surface of the die. The connector is electrically connected to the die through the RDL structure.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10522454
    Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Andreas Wolter, Georg Seidemann, Sven Albers, Christian Geissler
  • Patent number: 10522488
    Abstract: A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chen, Ching-Tien Su
  • Patent number: 10510718
    Abstract: A semiconductor structure includes a substrate; a first die disposed over the substrate; a second die disposed over the substrate; a molding disposed over the substrate and surrounding the first die and the second die; an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed over the first die, the second die and the molding, and the conductive member is surrounded by the dielectric layer; and a via extended within the second die and between the dielectric layer and the substrate.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Sung-Feng Yeh
  • Patent number: 10504824
    Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Patent number: 10490659
    Abstract: The present invention provides a semiconductor device that can achieve miniaturization or thinning of the size of the package while maintaining the characteristic of the MOSFET and reducing the on-resistance value, and a portable apparatus using the same. The gate electrodes 26 and 28 of the semiconductor chip 10 are disposed in the vicinity of the two side surfaces of the longitudinal direction (the x axis direction on the page) of the package 2, and the gate terminal 13 and 14 that is mounted with the gate electrodes 26 and 28 in a flip-chip manner are extended in the longitudinal direction of the package 2 and are derived to the outside from the two side surfaces 2A and 2B. Based on the configuration, it is capable of maximizing the size of the semiconductor chip with respect to the size of the package, and it is able to realize the high performance of the element characteristic for the module.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 26, 2019
    Assignee: UPI SEMICONDUCTOR CORP.
    Inventors: Masamichi Yanagida, Masashi Koyano, Nobuyoshi Matsuura, Hiroki Arai
  • Patent number: 10483230
    Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Yi Lim, Yi-Wen Wu, Tzong-Hann Yang, Ming-Che Ho, Chung-Shi Liu
  • Patent number: 10483487
    Abstract: A first product may be provided that comprises a substrate having a first surface, a first side, and a first edge where the first surface meets the first side; and a device disposed over the substrate, the device having a second side, where at least a first portion of the second side is disposed within 3 mm from the first edge of the substrate. The first product may further comprise a first barrier film that covers at least a portion of the first edge of the substrate, at least a portion of the first side of the substrate, and at least the first portion of the second side of the device.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: November 19, 2019
    Assignee: The Trustees of Princeton University
    Inventors: Prashant Mandlik, Ruiqing Ma, Jeffrey Silvernail, Julia J. Brown, Lin Han, Sigurd Wagner, Luke Walski
  • Patent number: 10475779
    Abstract: A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 12, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Seung Wook Yoon
  • Patent number: 10468339
    Abstract: A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Shin-Puu Jeng, Techi Wong
  • Patent number: 10460989
    Abstract: A semiconductor device includes a semiconductor element, a semiconductor substrate on which the semiconductor element is mounted, a conductive layer formed on the substrate, and a sealing resin covering the semiconductor element. The substrate is formed with a recess receding from a main surface of the substrate and including a bottom surface and first and second sloped surfaces spaced apart from each other in a first direction perpendicular to the thickness direction of the substrate. The conductive layer includes first conduction paths on the first sloped surface, second conduction paths on the second sloped surface and bottom conduction paths on the bottom surface. The second sloped surface includes exposed regions line-symmetrical to the first conduction paths with respect to a line perpendicular to both the thickness direction of the substrate and the first direction, and the second conduction paths are not disposed at the exposed regions.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: October 29, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Hirofumi Takeda, Satoshi Kimoto
  • Patent number: 10461149
    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias. Conductive material is formed directly above and directly against the conductive vias. The conductive material has an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section. The conductive material has a second sidewall that is not directly above the individual conductive vias. Covering material is formed directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias. The covering material comprises a composition different from that of at least some of the conductive material.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang
  • Patent number: 10461036
    Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu
  • Patent number: 10446504
    Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: October 15, 2019
    Assignee: XINTEC INC.
    Inventors: Chia-Ming Cheng, Po-Han Lee, Wei-Chung Yang, Kuan-Jung Wu, Shu-Ming Chang
  • Patent number: 10431516
    Abstract: A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 1, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Osamu Miyata, Masaki Kasai, Shingo Higuchi
  • Patent number: 10431564
    Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a chip package over a printed circuit board and multiple conductive bumps between the chip package and the printed circuit board. The chip package structure also includes one or more thermal conductive elements between the chip package and the printed circuit board. The thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: October 1, 2019
    Assignee: MediaTek Inc.
    Inventor: Tzu-Hung Lin
  • Patent number: 10424684
    Abstract: An MSM ultraviolet ray receiving element has a low dark state current value and a good photosensitivity. The MSM ultraviolet ray receiving element has a first nitride semiconductor layer on a substrate, a second nitride semiconductor layer on the first nitride semiconductor layer, and first and second electrodes on the second nitride semiconductor layer. The first nitride semiconductor layer contains AlXGa(1-X)N (0.4?X?0.90). The second nitride semiconductor layer contains AlYGa(1-Y)N with a film thickness t (nm) satisfying 5?t?25. The first electrode and the second electrode contain a material containing at least three elements of Ti, Al, Au, Ni, V, Mo, Hf, Ta, W, Nb, Zn, Ag, Cr, and Zr. Al composition ratios X and Y and a film thickness t satisfy ?0.009×t+X+0.22?0.03?Y??0.009×t+X+0.22+0.03.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 24, 2019
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Akira Yoshikawa, Kazuhiro Nagase, Motoaki Iwaya, Saki Ushida
  • Patent number: 10418350
    Abstract: A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 17, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast