Flip Chip Patents (Class 257/778)
  • Patent number: 11462465
    Abstract: Leadframes for semiconductor devices are manufactured by providing a laminar substrate of laser direct structuring material, the laminar substrate comprising first and second opposed surfaces, applying laser beam processing to the substrate to provide a first pattern of electrically-conductive formations at the first surface, a second pattern of electrically-conductive formations at the second surface and electrically-conductive vias through the substrate between the first surface and the second surface. Electrically-conductive material is formed, for instance via electrolytic or electroless growth of electrically-conductive material such a copper onto the first and second pattern of electrically-conductive formations as well as onto the electrically-conductive vias provided by applying laser beam processing to the substrate.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 4, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventor: Pierangelo Magni
  • Patent number: 11456236
    Abstract: A vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality of wiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: September 27, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Sung Yang, Joon-Sung Lim, Sung-Min Hwang, Ji-Young Kim, Ji-Won Kim
  • Patent number: 11450633
    Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Tse Lin, Chung-Hsing Kuo, Hui-Ling Chen
  • Patent number: 11443999
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 13, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11444014
    Abstract: There are provided semiconductor packages including a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: September 13, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinho Chun, Jin Ho An, Teahwa Jeong, Jeonggi Jin, Ju-Il Choi, Atsushi Fujisaki
  • Patent number: 11430724
    Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 ?m, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Robert L. Sankman, Robert Nickerson, Mitul Modi, Sanka Ganesan, Rajasekaran Swaminathan, Omkar Karhade, Shawna M. Liff, Amruthavalli Alur, Sri Chaitra J. Chavali
  • Patent number: 11424204
    Abstract: A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 23, 2022
    Assignee: MEDIATEK INC.
    Inventors: Po-Chao Tsao, Yu-Hua Huang
  • Patent number: 11410904
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 9, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11410954
    Abstract: Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: August 9, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Chang-Fu Lin, Yuan-Hung Hsu
  • Patent number: 11410910
    Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Tsung Hsiao, Jen Yu Wang, Chung-Jung Wu, Tung-Liang Shao, Chih-Hang Tung
  • Patent number: 11394362
    Abstract: An electronic component housing package includes a base having a first principal face provided with a mounting section for mounting an electronic component; a frame having a second principal face, the frame being disposed on the base so as to surround the mounting section; a frame-shaped metallized layer disposed on the second principal face of the frame; and a side-surface conductor disposed on an inner side surface of the frame, the side-surface conductor connecting the frame-shaped metallized layer and a relay conductor formed on the first principal face, the side-surface conductor being covered with an insulating film from one end to the other end in a width direction of the side-surface conductor.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: July 19, 2022
    Assignee: KYOCERA CORPORATION
    Inventors: Takuo Kisaki, Masaki Suzuki
  • Patent number: 11387400
    Abstract: An electronic module includes a substrate that includes a first main surface and a second main surface, at least one first electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes a hollow portion, at least one second electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes no hollow portion, and a sealing resin. The at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin. The at least one second electronic component is mounted on the second main surface of the substrate and is not sealed with the sealing resin.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 12, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Junpei Yasuda
  • Patent number: 11387183
    Abstract: A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided.
    Type: Grant
    Filed: May 10, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 11373968
    Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: June 28, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Yaoyu Pang, Steven A. Atherton
  • Patent number: 11367700
    Abstract: A device comprising a connecting plate and a circuit element is disclosed. The circuit element is electrically coupled to the connecting plate through a solder connection including a plurality of solder balls disposed between the circuit element and the connecting plate. An underfill layer is formed between the circuit element and the connecting plate and configured to provide bonding between the circuit element and the connecting plate. The solder connection includes a first solder area with a first solder ball density and a second solder area with a second solder ball density. The first solder ball density is less than the second solder ball density. The underfill layer includes a bonding material continuously disposed in the second solder area of the solder connection.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 21, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hongbin Shi, Zhuqiu Wang, Runqing Ye, Haohui Long
  • Patent number: 11362052
    Abstract: A semiconductor device package includes a first electronic component having a first surface and a second surface opposite the first surface. The semiconductor device package further includes a first pad disposed on the first surface of the first electronic component. The first pad has a first surface facing away from the first surface of the first electronic component, a second surface opposite the first surface of the first pad, and a lateral surface extended between the first surface of the first pad and the second surface of the first pad. The semiconductor device package further includes a second pad disposed on the first surface of the first pad. The second pad has a first surface facing away from the first surface of the first pad, a second surface opposite the first surface of the second pad, and a lateral surface extended between the first surface of the second pad and the second surface of the second pad.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: June 14, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Chang Lee, Wen-Long Lu
  • Patent number: 11362061
    Abstract: A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: June 14, 2022
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Lin Hou, Jaber Derakhshandeh, Eric Beyne, Ingrid De Wolf, Giovanni Capuz
  • Patent number: 11362068
    Abstract: A semiconductor package includes a base substrate having a first semiconductor substrate, and a first protective layer covering a top side thereof. A first semiconductor chip is on the first protective layer. A first fillet layer fills a space between the first protective layer and the first semiconductor chip. A first side surface of the base substrate extends in a first direction, and second and third side surfaces extend in a second direction. The base substrate includes two corner regions and a side region between the corner regions. A first protective layer in the side region includes a first side trench which overlaps the first semiconductor chip. A part of the first fillet layer fills the first side trench.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: June 14, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Sick Park, Min Soo Kim
  • Patent number: 11355357
    Abstract: A semiconductor device includes a semiconductor element, an electronic component electrically connected to the semiconductor element, a connection member electrically connecting the electronic component to the semiconductor element, and a sealing resin portion having a first surface and a second surface opposite to the first surface and integrally holding the semiconductor element, the electronic component, and the connection member in a state where a semiconductor top surface as a surface of the semiconductor element and a component surface as a surface of the electronic component are exposed from the sealing resin portion on a side adjacent to the first surface.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: June 7, 2022
    Assignee: DENSO CORPORATION
    Inventor: Kazuaki Mawatari
  • Patent number: 11335640
    Abstract: A microelectronic package may be fabricated having at least one microelectronic die attached to a microelectronic substrate, wherein the microelectronic substrate includes at least one notch formed in at least one side thereof. The microelectronic dice may be attached to a first surface of the microelectronic substrate and in electronic communication with a bond pad on a second surface of the microelectronic substrate with a bond wire which extends through the notch in the microelectronic substrate.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventor: John Meyers
  • Patent number: 11335617
    Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: May 17, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki Tokuya, Yuichi Sano, Toshihiro Tada
  • Patent number: 11337302
    Abstract: A wiring circuit board includes an insulating layer, a wire embedded in the insulating layer, and an alignment mark electrically independent from the wire and disposed in the insulating layer so as to allow a one-side surface in a thickness direction of the alignment mark to be exposed from the insulating layer. A peripheral portion of the alignment mark consists of only the insulating layer and has a thickness of 30 ?m or less.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: May 17, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shusaku Shibata, Takahiro Takano, Hiromoto Haruta, Shuichi Wakaki
  • Patent number: 11329000
    Abstract: A package includes: a package body having an outside housing including first and second package sides and package sidewalls that extend between the first and second package sides; first and second electrically conductive interface layers spaced apart from each other at the outside housing; and first and second power semiconductor chips arranged within the package body, both chips having a respective first load terminal and a respective second load terminal. The first load terminals are electrically connected to each other within the package body. The second load terminal of the first chip is electrically connected to the first electrically conductive interface layer. The second load terminal of the second chip is electrically connected to the second electrically conductive interface layer. The outside housing of the package body further includes a creepage structure having a minimum dimension between the first electrically conductive interface layer and the second electrically conductive interface layer.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 11328939
    Abstract: A method and a device for prefixing substrates, whereby at least one substrate surface of the substrates is amorphized in at least one surface area, characterized in that the substrates are aligned and then make contact and are prefixed on the amorphized surface areas.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 10, 2022
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Friedrich Paul Lindner
  • Patent number: 11328974
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: May 10, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11322468
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: May 3, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt
  • Patent number: 11322478
    Abstract: A semiconductor device includes a wiring substrate and multiple semiconductor chips mounted on the wiring substrate by flip chip bonding with a resin being interposed between the wiring substrate and the semiconductor chips. The wiring substrate includes a chip mounting region in which the semiconductor chips are arranged in a matrix, and a resin injection region protruding from an end of the chip mounting region. The outer edge of the wiring substrate in the chip mounting region is positioned inward of the outer edge of the semiconductor chips arranged in the matrix. The outer edge of the wiring substrate in the resin injection region protrudes outward of the outer edge of the semiconductor chips arranged in the matrix.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: May 3, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takaharu Yamano, Yoshihiro Ihara
  • Patent number: 11316077
    Abstract: A radiation-emitting device includes a semiconductor layer sequence having an active layer that emits a primary radiation during operation, a decoupling surface on a surface of the semiconductor layer sequence, a wavelength conversion layer on a side of the semiconductor layer sequence facing away from the decoupling surface, containing at least one conversion material that converts the primary radiation into secondary radiation, and a mirror layer on the side of the wavelength conversion layer facing away from the semiconductor layer sequence, wherein the at least one conversion material is electrically conductive and/or embedded in an electrically conductive matrix material.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: April 26, 2022
    Assignee: OSRAM OLED GmbH
    Inventors: Britta Göötz, Norwin von Malm
  • Patent number: 11309895
    Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Bahattin Kilic, Jie-Hua Zhao, Kunzhong Hu, Suk-Kyu Ryu
  • Patent number: 11309252
    Abstract: A package substrate including a first redistribution structure, a first bonding layer, a core, a second bonding layer and a second redistribution structure in a sequential order is provided. The first redistribution structure has a first redistribution surface and a first bonding pad disposed on the first redistribution surface. The second redistribution structure has a second redistribution surface and a second bonding pad disposed on the second redistribution surface. The core has a first core pad disposed on a first core surface, and a second core pad disposed on a second core surface opposite to the first core surface. The first core pad and the second core pad are directly bonded to first bonding pad and the second bonding pad, respectively. The first core pad and the second core pad are offset from first bonding pad and the second bonding pad, respectively. The first bonding pad and the first core pad are embedded in the first bonding layer.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 19, 2022
    Inventor: Dyi-Chung Hu
  • Patent number: 11302592
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 12, 2022
    Assignee: MediaTek Inc.
    Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
  • Patent number: 11303263
    Abstract: In a component with component structures generating dissipation heat, it is proposed to apply on an active side of the substrate a heat-conducting means to the back side of the component substrate, which has a second thermal conductivity coefficient ?LS, which is substantially higher than the first thermal conductivity coefficient ?S of the substrate. The heat dissipation then succeeds via the heat-conducting means and via connecting means which connect the substrate to a carrier.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 12, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Tomasz Jewula, Veit Meister
  • Patent number: 11302620
    Abstract: A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, a driving chip disposed on the board and between the first connection pads and the second connection pads, and a first adhesive layer disposed on the board and overlapping with an entirety of the first connection pads in a plan view. The second connection pads are spaced apart from the first connection pads in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Joo-Nyung Jang
  • Patent number: 11296003
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 5, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11291126
    Abstract: A circuit board includes a substrate, a first circuit layer, a second circuit layer, and a third circuit layer. The substrate includes a base layer, a first metal layer formed on the base layer, and a seed layer formed on the first metal layer. The first circuit layer is located on the substrate and includes the first metal layer and a signal layer formed on a surface of the first metal layer. The second circuit layer is coupled to the first circuit layer and includes the first metal layer, the seed layer, and a connection pillar formed on a surface of the first metal layer and the seed layer. The third circuit layer is coupled to the second circuit layer and includes the seed layer and a coil formed on a surface of the seed layer.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: March 29, 2022
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Jun Dai
  • Patent number: 11276658
    Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Gambee, Nhi Doan, Chandra S. Tiwari, Owen R. Fay, Ying Chen
  • Patent number: 11270966
    Abstract: Protruding solder structures are created for electrical attachment of semiconductor devices. A rigid mold having one or more mold openings is attached to and used in combination with a decal structure that has one or more decal holes. The decal structure is disposed on the rigid mold so that the decal openings are aligned over the mold openings. Each of the decal hole and mold opening in contact form a single combined volume. The single combined volumes are filled with solder to form protruding solder structures. Various structures and methods of making and using the structures are disclosed.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jae-Woong Nah, Stephen L. Buchwalter, Peter A. Gruber, Paul Alfred Lauro, Da-Yuan Shih
  • Patent number: 11259133
    Abstract: A microphone assembly includes a substrate defining a port, a MEMS transducer, a guard ring, and a can. The MEMS transducer is coupled to the substrate such that the MEMS transducer is positioned over the port. The guard ring is coupled to the substrate and surrounds the MEMS transducer. The guard ring includes a plurality of edges that further includes a first edge and an opposing second edge. A portion of the first edge and a portion of the second edge have a reduced thickness relative to adjacent ones of the plurality of edges. The can is coupled to the guard ring such that the substrate and the can cooperatively define an interior cavity.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: February 22, 2022
    Assignee: Knowles Electronics, LLC
    Inventors: Norman Dennis Talag, Anthony Schmitz
  • Patent number: 11245075
    Abstract: An organic substrate and method of making with optimal thermal warp characteristics is disclosed. The organic substrate has one or more top layers and one or more bottom layers. A chip footprint region is a surface region on each of the top and bottom layers that is defined as the projection of one or more semiconductor chips (chips) on the surface of each of the top and bottom layers. One or more top removal patterns are located on and may or may not remove material from the surface of one or more of the top layers within the chip footprint region of the respective top layer. One or more bottom removal patterns are located on and remove material from the surface of one or more of the bottom layers outside the chip footprint region of the respective bottom layer. The removal of the material from one or more of the top layers and/or bottom layers changes and optimizes a thermal warp of the organic substrate.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sri Sri-Jayantha, Vijayeshwar Khanna, Arun Sharma, Hien Dang
  • Patent number: 11239201
    Abstract: An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Chung-Shi Liu
  • Patent number: 11239223
    Abstract: In a semiconductor device, a substrate has a main surface. A first semiconductor chip has a first front surface and a first back surface, and is mounted on the main surface via a plurality of bump electrodes. A first spacer has a second front surface and a second back surface that is mounted on the main surface. A height of the second front surface from the main surface is within a range between a highest height and a lowest height of the first back surface from the main surface. A second spacer has a third front surface and a third back surface that is mounted on the main surface. A height of the third front surface from the main surface is within the range between the highest height and the lowest height of the first back surface from the main surface.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: February 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Masayuki Miura
  • Patent number: 11226369
    Abstract: Electrical current flow in a ball grid array (BGA) package can be measured by an apparatus including an integrated circuit (IC) electrically connected to the BGA package. Solder balls connect the BGA package to a printed circuit board (PCB). A current sense loop can be fabricated on a wiring plane of the PCB to encircle a current supply via that supplies current to an IC mounted on the BGA package. A MUX/Sequencer can sequentially connect wires of the current sense loop to an amplifier. The amplifier can amplify a voltage induced on the current sense mesh by current flow into the BGA package. A sensing analog-to-digital converter (ADC) is electrically connected to convert a voltage at the output of the amplifier into digital output signals.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Layne A. Berge, Matthew Doyle, Kyle Schoneck, Thomas W. Liang, Matthew A. Walther, Jason J. Bjorgaard, John R. Dangler
  • Patent number: 11222792
    Abstract: In one or more embodiments, a semiconductor package device includes a substrate, a trace, a structure, a barrier element and an underfill. The substrate has a first surface including a filling region surrounded by the trace. The structure is disposed over the filling region and electrically connected to the substrate. The barrier element is disposed on the trace. The underfill is disposed on the filling region.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: January 11, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chang-Lin Yeh
  • Patent number: 11222829
    Abstract: A chip mounting structure and a chip mounting device are provided. The chip mounting structure includes a circuit substrate and a plurality of micro heaters. The circuit substrate has a plurality of solder pads. A plurality of micro heaters are disposed on the circuit substrate adjacent to the solder pad. The plurality of chips are disposed on the circuit substrate, and the chip is electrically connected to the solder pad by a solder ball. Therefore, the soldering yield of the process can be reduced by the chip mounting structure and the chip mounting device.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: January 11, 2022
    Assignee: Skiileux Electricity Inc.
    Inventor: Chien-Shou Liao
  • Patent number: 11222836
    Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Veronica Strong, Aleksandar Aleksov, Brandon Rawlings, Johanna Swan
  • Patent number: 11217501
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 4, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11211310
    Abstract: A package structure is provided. The package structure includes a leadframe, a device, first protrusions, second protrusions, a conductive unit, and an encapsulation material. The device includes a substrate, an active layer, first electrodes, second electrodes and a third electrode. The first electrodes have different potentials than the second electrodes. The first electrodes and the second electrodes are arranged so that they alternate with each other. The first protrusions are disposed on each of the first electrodes. The second protrusions are disposed on each of the second electrodes. The first protrusions and the second protrusions are connected to the leadframe. The first side of the conductive unit is connected to the substrate of the device. The conductive unit is connected to the leadframe. The encapsulation material covers the device and the leadframe. The second side of the conductive unit is exposed from the encapsulation material.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: December 28, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Sheng-Che Chiou, Jen-Chih Li
  • Patent number: 11205612
    Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Patent number: 11201199
    Abstract: A chip on film package includes: a base substrate having an output pad region; a plurality of output pads disposed in the output pad region of the base substrate, wherein the output pads are arranged in a zigzag configuration on the base substrate; a plurality of output pad wirings connected to the output pads, respectively; and a protection layer disposed on the output pad wirings. The protection layer is disposed on the output pad wirings disposed between two adjacent output pads, arranged in a first direction.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 14, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki-Soo Nam, Gi Young Kang
  • Patent number: 11177300
    Abstract: A size reduction of an image pickup module by using resin molding, including a reduction in height, area, or the like thereof is achieved in an actual product. Provided is a module, including a substrate; a semiconductor component in which a first surface of a semiconductor device manufactured by chip-size packaging is provided and fixed along a plate-shaped translucent member, and a second surface of the semiconductor device is fixed with the second surface caused to face the substrate; a frame portion made of resin and formed on the substrate to surround the semiconductor component; and an interposition member which is made of resin and with which a gap between the semiconductor component and the substrate is filled. The interposition member is connected and fixed to the frame portion to be integrated therewith.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: November 16, 2021
    Assignee: SONY CORPORATION
    Inventors: Hirokazu Seki, Go Asayama, Kiyoharu Momosaki, Rei Takamori, Masakazu Baba