Abstract: There are provided a fan-out sensor package and an optical fingerprint sensor module including the same. The fan-out sensor package includes: a connection member having a 5 through-hole; an image sensor disposed in the through-hole of the connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the connection member, the image sensor, and 10 an optical lens; and a redistribution layer disposed on the connection member, the image sensor, and the optical lens. The connection member includes a wiring layer, and the redistribution layer electrically connects the wiring layer and the connection pads to each other.

Abstract: In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor device includes a semiconductor chip, a bump contract, and encapsulating layer, an insulating layer, and a connection terminal.

Abstract: A system comprising synchronization circuitry, a first interrogator, and a second interrogator. The first interrogator includes a transmit antenna; a first receive antenna, and circuitry configured to generate, using radio-frequency (RF) signal synthesis information received from the synchronization circuitry, a first RF signal for transmission by the transmit antenna, and generate, using the first RF signal and a second RF signal received from a target device by the first receive antenna, a first mixed RF signal indicative of a distance between the first interrogator and the target device. The second interrogator includes a second receive antenna, and circuitry configured to generate, using the RF signal synthesis information, a third RF signal; and generate, using the third RF signal and a fourth RF signal received from the target device by the second receive antenna, a second mixed RF signal indicative of a distance between the second interrogator and the target device.

Abstract: The flexible printed circuit includes a first insulator including a first insulating layer, a second insulator including a second insulating layer, and a wiring layer formed of a conductive material. Each of the first insulator and the second insulator meets IEC 60950. The flexible printed circuit includes a region where insulation of the wiring layer is required, the region is hermetically sealed by the first insulator and the second insulator.

Abstract: A semiconductor package structure includes a first semiconductor die, an encapsulant surrounding the first semiconductor die, and a redistribution layer (RDL) electrically coupled to the first semiconductor die. The encapsulant has a first surface over the first semiconductor die and a second surface under the first semiconductor die. The RDL has a first portion under the first surface of the encapsulant and a second portion over the first surface of the encapsulant.

Abstract: A method includes forming an interposer, which includes a semiconductor substrate, and an interconnect structure over the semiconductor substrate. The method further includes bonding a device die to the interposer, so that a first metal pad in the interposer is bonded to a second metal pad in the device die, and a first surface dielectric layer in the interposer is bonded to a second surface dielectric layer in the device die. The method further includes encapsulating the device die in an encapsulating material, forming conductive features over and electrically coupling to the device die, and removing the semiconductor substrate. A part of the interposer, the device die, and portions of the conductive features in combination form a package.

Abstract: A substrate includes a dielectric layer, a first metal bar, a plurality of first traces, a plurality of first openings, a second metal bar, and at least one second opening. The dielectric layer has a first major surface and a second major surface opposite to the first major surface. The first metal bar is on the first major surface. The plurality of first traces are on the first major surface. Each first trace is connected at one end to the first metal bar. The plurality of first openings expose the dielectric layer on the first major surface and intersect a first trace. The second metal bar is on the second major surface. The at least one second opening exposes the dielectric layer on the second major surface and intersects the second metal bar. The first openings are laterally offset with respect to the at least one second opening.

Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.

Abstract: An exposure head configured to expose a photosensitive drum to light includes a circuit board on which a plating layer is formed, a semiconductor chip, which is provided on the plating layer, and includes a light emitting element configured to emit the light for exposing the photosensitive drum, a lens array configured to condense the light emitted from the light emitting element onto the photosensitive drum, and a housing to which the lens array and the circuit board are fixed, wherein the plating layer and a part of the housing abut against each other in an optical axis direction of the lens array, and wherein the light emitting element and the lens array are opposed to each other in the optical axis direction.

Abstract: A light emitting diode includes: a light emitting structure including a first semiconductor layer, a light emitting layer, a second semiconductor layer; a first metal layer arranged on at least a portion of the first semiconductor layer and in contact with the first semiconductor layer; and an electrode layer arranged over the light emitting structure, and having a first electrode layer and a second electrode layer. The first electrode layer is electrically coupled to the first and second semiconductor layers; the second electrode layer is configured for bonding with a package substrate, and includes a first and second bonding regions; the first bonding region is electrically coupled to the first semiconductor layer; the second bonding region is electrically coupled to the second semiconductor layer; and the first metal layer is not overlapped with the first bonding region of the second bonding region in a vertical direction.

Abstract: The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.

Abstract: A holding table for holding a wafer includes plural pins, and a wafer holding surface includes the tips of the plural pins. Therefore, small dust enters between the pins and thus is less readily left between the wafer holding surface and the wafer. Therefore, when the wafer is sucked and held, a gap is less readily made between the wafer holding surface and the wafer. Thus, the occurrence of the situation in which the wafer is held in a waving state is suppressed. For this reason, when a liquid resin is pushed to spread over the lower surface of the wafer, an air bubble enters less readily between the liquid resin and the wafer. This can suppress entry of the air bubble in a protective member obtained by curing the liquid resin.

Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

Abstract: The present disclosure provides an LED package structure, a carrier, and a method for manufacturing a carrier. The carrier includes a substrate and an electrode layer disposed on the substrate. The electrode layer includes at least one bonding portion that has a plurality of elongated microstructures recessed in a surface thereof.

Abstract: A method for bonding a semiconductor package includes loading a semiconductor chip on a substrate, and bonding the semiconductor chip to the substrate by using a bonding tool, the bonding tool including a pressing surface for pressing the semiconductor chip, and an inclined surface extending from one side of the pressing surface. Bonding the semiconductor chip to the substrate includes deforming a bonding agent disposed between the substrate and the semiconductor chip by pressing the bonding tool, and deforming the bonding agent includes generating a fillet by protruding a portion of the bonding agent beyond the semiconductor chip, and growing the fillet in such a way that a top surface of the fillet is grown in an extending direction of the inclined surface.

Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.

Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The plurality of solder-including electrodes include at least one gap control electrode. The at least one gap control electrode includes a columnar metal layer and a solder layer in order named from side on which the chip body is disposed, and includes an overlap region where the columnar metal layer and the solder resist layer overlap each other, along part or all of an aperture end of the aperture.

Abstract: A multi-die module includes a first die with a first substrate and a first device formed over the first substrate, wherein the first substrate includes a cavity on a side opposite the first device. The multi-die module also includes a second die with a second substrate and a second device formed over the second substrate, wherein the second die is positioned at least partially in the cavity. The multi-die module also includes a coupler configured to convey signals between the first device and the second device.

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Abstract: There is provided an apparatus including a semiconductor light emitting device formed on a surface of a substrate including a first electrode and a plurality of second electrodes formed adjacent to the first electrode in planar view, a base including an opposite surface facing the surface of the substrate, wherein a third electrode corresponding to the first electrode in positional relationship and a fourth electrode corresponding to the plurality of second electrodes in positional relationship are formed on the opposite surface, first connecting bodies electrically connecting the first electrode with the third electrode, and a second connecting body electrically connecting the plurality of second electrodes with the fourth electrode. The plurality of second electrodes (100) have a belt-like planer shape and centerlines respectively bisecting widths of the plurality of second electrodes are substantially parallel in planar view.

Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a top surface of the semiconductor substrate; a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively; a first bump disposed between the polymeric pad and the first pad; and a second bump disposed between the active pad and the second pad; wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad. Further, a method of manufacturing the semiconductor structure is disclosed. The method includes providing a circuit board; and forming a polymeric pad and an active pad on a surface of the circuit board, wherein a first thickness of the polymeric pad is substantially greater than a second thickness of the active pad.

Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.

Abstract: A semiconductor package includes: a connection member including a plurality of connection pads and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant sealing the semiconductor chip; a passivation layer disposed on the connection member; a plurality of under bump metallurgy (UBM) pads disposed on the passivation layer; and a plurality of UBM vias connecting the plurality of UBM pads to the plurality of connection pads, respectively, wherein the plurality of UBM pads include a first UBM pad overlapped with the semiconductor chip in a stacking direction, and a second UBM pad located outside of the overlapped region, and the first connection pad has an area larger than an area of an associated first UBM pad while the associated first UBM pad is overlapped in the stacking direction, and has an area larger than an area of the second connection pad.

Abstract: A substrate is disclosed. In an embodiment, a substrate includes a ceramic main body, an organic surface structure on at least one first outer face of the ceramic main body and outer redistribution layers integrated into the organic surface structure.

Abstract: A printed circuit board includes a circuit trace and a connector pad. The connector pad provides electrical and mechanical mounting of a connector lead of a surface mount device and provides a circuit path between the surface mount device and the circuit trace. The connector pad includes 1) a connector pad base electrically coupled to the circuit trace, and 2) a first connector pad island electrically isolated from the connector pad base. The connector pad base has a length that is substantially equal to a length of a contact portion of the connector lead.

Abstract: The present disclosure provides a semiconductor structure, including providing a first chip, disposing a first copper layer having a first thickness over a first side of the first chip, and disposing a first solder having a second thickness over the first copper layer, wherein a ratio of the second thickness and the first thickness is in a range of from about 2 to about 3.5.

Abstract: A display substrate comprises a base board and a first bonding pad. The base board comprises a first surface having a first bonding district. The first bonding pad is disposed on the first surface. The first bonding pad is configured to electrically connect to a first electrode of a light emitting component in the first bonding district. The first bonding pad comprises a main bonding portion and an auxiliary bonding portion, wherein at least a part of an orthogonal projection of the main bonding portion on the base board is in the first bonding district. The auxiliary bonding portion electrically connects to the main bonding portion, wherein at least a part of an orthogonal projection of the auxiliary bonding portion on the base board is outside the first bonding district. There is a gap between the main bonding portion and the auxiliary bonding portion.

Abstract: An optical semiconductor apparatus includes: an optical semiconductor device including a translucent support substrate; a buffer layer on the support substrate, a seal ring in a frame shape provided in an outer region on the buffer layer, an active layer provided on an inner region of the buffer layer, and an electrode provided on the active layer. The optical semiconductor apparatus further including: a package substrate on which the optical semiconductor device is mounted; and a sealing part that seals a space between the seal ring and the package substrate.

Abstract: The present invention provides a semiconductor device capable of being miniaturized and preventing reduction of mountability to a wiring substrate. The semiconductor device includes a conductive support having a support surface and a mounting surface facing opposite sides in a thickness direction z, and an end surface intersecting with the mounting surface and facing outside; a semiconductor element having an element back surface facing the support surface and an electrode formed on the element back surface, in which the electrode is connected to the support surface; and an external terminal conducted to the mounting surface and exposed to the outside; wherein the external terminal includes a Ni layer having P and an Au layer, and respectively connected to and laminated with at least one portion of each of the mounting surface and the end surface.

Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a semiconductor unit, one or more bonding structures, and at least one supporter. The semiconductor unit includes at least one via. The one or more bonding structures are disposed over the semiconductor unit and electrically connected to the at least one via. The at least one supporter is disposed over the semiconductor unit. The at least one supporter is a metal block or a polymer block spaced apart from the one or more bonding structures.

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

Abstract: An arrangement is disclosed. In an embodiment the arrangement includes at least one semiconductor component and a heat sink, wherein the semiconductor component is arranged on the heat sink, wherein the heat sink is configured to dissipate heat from the semiconductor component, wherein the heat sink comprises a thermally conductive material, and wherein the material comprises at least aluminum and silicon.

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

Abstract: A method of fabricating an INFO package may include at least the following steps. A first buffer pattern and a second buffer pattern are formed on a substrate. A first chip is attached on the substrate through the first buffer pattern. A second chip is attached on the substrate through the second buffer pattern. A squeezing force is provided between an exterior surface of the substrate and a top surface of the first chip and between an exterior surface of the substrate and a top surface of the second chip. The squeezed first buffer pattern and the squeezed second buffer pattern are cured. A molding compound is formed surrounding the first chip, the second chip, the squeezed first buffer pattern and the squeezed second buffer pattern. A redistribution circuit structure layer is formed electrically connected to the first chip and the second chip on the molding compound.

Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

Abstract: Integrated semiconductor assemblies and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device assembly comprises a base substrate having a cavity and a perimeter region at least partially surrounding the cavity. The cavity is defined by sidewalls extending at least partially through the substrate. The assembly further comprises a first die attached to the base substrate at the cavity, and a second die over at least a portion of the first die and attached to the base substrate at the perimeter region. In some embodiments, the first and second dies can be electrically coupled to each other via circuitry of the substrate.

Abstract: A computing apparatus including a printed circuit board (PCB) including a first central processing unit (CPU) socket and additional CPU socket(s); a CPU coupled to the first CPU socket; a base interposer coupled to the additional CPU socket(s); and one or more devices connected to the base interposer, wherein the base interposer provides a connection between the CPU and the one or more devices.

Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.

Abstract: To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.

Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.

Abstract: A device and method for reinforcing, baffling or sealing a vehicle structure, comprising the steps of providing a flexible carrier and plurality of parallel strips located on opposing surfaces of the carrier.

Abstract: A flip-chip LED chip includes: a substrate; a first semiconductor layer; a light emitting layer; a second semiconductor layer; a local defect region over part of the second semiconductor layer and extending downward to the first semiconductor layer; first and second metal layers respectively over portions of the first and second semiconductor layers; an insulating layer covering the first and second metal layers, the second and first semiconductor layers in the local defect region. The insulating layer has opening structures over the first and second metal layers respectively; a eutectic electrode structure over the insulating layer with openings and including first and second eutectic layers from bottom up at a vertical direction, and including first-type and second-type electrode regions at a horizontal direction. The second eutectic layer does not overlap with the first and second metal layers at the vertical direction.

Abstract: A semiconductor package including at least one integrated circuit component and a glue material is provided. The at least one integrated circuit component has a top surface with conductive terminals and a backside surface opposite to the top surface. The glue material encapsulates the at least one integrated circuit component, wherein a first lateral thickness of the glue material is smaller than a second lateral thickness of the glue material, the second lateral thickness is parallel to the first lateral thickness, and the first lateral thickness is substantially coplanar with the top surface.

Abstract: A semiconductor module includes a substrate composed of electrically insulating material. A structured metal layer for contact with an electrical component is applied to a top side of the substrate. The structured metal layer is applied to the substrate only in a central region of the substrate, so that an edge region which surrounds the central region and in which the structured metal layer is not applied to the substrate remains on the top side of the substrate. A contact layer for making contact with a cooling body is situated opposite the structured metal layer and applied to a bottom side of the substrate in the central region. A structured supporting structure is further applied to the bottom side of the substrate in the edge region and has a thickness which corresponds to a thickness of the contact layer.

Abstract: A chip-on-film (COF) package structure includes a first COF and a second COF. The first COF includes a first flexible substrate having a first external terminal and a first internal terminal opposite to each other, first outer leads disposed at the first external terminal, first inner leads disposed at the first internal terminal, and a first chip disposed between the first external terminal and the first internal terminal. The second COF includes a second flexible substrate having a second external terminal and a second internal terminal opposite to each other, second outer leads disposed at the second external terminal, second inner leads disposed at the second internal terminal, and a second chip disposed between the second external terminal and the second internal terminal. The first COF is partially overlapped with the second COF. A display device having the COF package structure is also provided.