Abstract: A package substrate including a first redistribution structure, a first bonding layer, a core, a second bonding layer and a second redistribution structure in a sequential order is provided. The first redistribution structure has a first redistribution surface and a first bonding pad disposed on the first redistribution surface. The second redistribution structure has a second redistribution surface and a second bonding pad disposed on the second redistribution surface. The core has a first core pad disposed on a first core surface, and a second core pad disposed on a second core surface opposite to the first core surface. The first core pad and the second core pad are directly bonded to first bonding pad and the second bonding pad, respectively. The first core pad and the second core pad are offset from first bonding pad and the second bonding pad, respectively. The first bonding pad and the first core pad are embedded in the first bonding layer.

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

Abstract: A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, a driving chip disposed on the board and between the first connection pads and the second connection pads, and a first adhesive layer disposed on the board and overlapping with an entirety of the first connection pads in a plan view. The second connection pads are spaced apart from the first connection pads in a second direction perpendicular to the first direction.

Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.

Abstract: In a component with component structures generating dissipation heat, it is proposed to apply on an active side of the substrate a heat-conducting means to the back side of the component substrate, which has a second thermal conductivity coefficient ?LS, which is substantially higher than the first thermal conductivity coefficient ?S of the substrate. The heat dissipation then succeeds via the heat-conducting means and via connecting means which connect the substrate to a carrier.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: A circuit board includes a substrate, a first circuit layer, a second circuit layer, and a third circuit layer. The substrate includes a base layer, a first metal layer formed on the base layer, and a seed layer formed on the first metal layer. The first circuit layer is located on the substrate and includes the first metal layer and a signal layer formed on a surface of the first metal layer. The second circuit layer is coupled to the first circuit layer and includes the first metal layer, the seed layer, and a connection pillar formed on a surface of the first metal layer and the seed layer. The third circuit layer is coupled to the second circuit layer and includes the seed layer and a coil formed on a surface of the seed layer.

Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.

Abstract: Protruding solder structures are created for electrical attachment of semiconductor devices. A rigid mold having one or more mold openings is attached to and used in combination with a decal structure that has one or more decal holes. The decal structure is disposed on the rigid mold so that the decal openings are aligned over the mold openings. Each of the decal hole and mold opening in contact form a single combined volume. The single combined volumes are filled with solder to form protruding solder structures. Various structures and methods of making and using the structures are disclosed.

Abstract: A microphone assembly includes a substrate defining a port, a MEMS transducer, a guard ring, and a can. The MEMS transducer is coupled to the substrate such that the MEMS transducer is positioned over the port. The guard ring is coupled to the substrate and surrounds the MEMS transducer. The guard ring includes a plurality of edges that further includes a first edge and an opposing second edge. A portion of the first edge and a portion of the second edge have a reduced thickness relative to adjacent ones of the plurality of edges. The can is coupled to the guard ring such that the substrate and the can cooperatively define an interior cavity.

Abstract: An organic substrate and method of making with optimal thermal warp characteristics is disclosed. The organic substrate has one or more top layers and one or more bottom layers. A chip footprint region is a surface region on each of the top and bottom layers that is defined as the projection of one or more semiconductor chips (chips) on the surface of each of the top and bottom layers. One or more top removal patterns are located on and may or may not remove material from the surface of one or more of the top layers within the chip footprint region of the respective top layer. One or more bottom removal patterns are located on and remove material from the surface of one or more of the bottom layers outside the chip footprint region of the respective bottom layer. The removal of the material from one or more of the top layers and/or bottom layers changes and optimizes a thermal warp of the organic substrate.

Abstract: In a semiconductor device, a substrate has a main surface. A first semiconductor chip has a first front surface and a first back surface, and is mounted on the main surface via a plurality of bump electrodes. A first spacer has a second front surface and a second back surface that is mounted on the main surface. A height of the second front surface from the main surface is within a range between a highest height and a lowest height of the first back surface from the main surface. A second spacer has a third front surface and a third back surface that is mounted on the main surface. A height of the third front surface from the main surface is within the range between the highest height and the lowest height of the first back surface from the main surface.

Abstract: An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

Abstract: Electrical current flow in a ball grid array (BGA) package can be measured by an apparatus including an integrated circuit (IC) electrically connected to the BGA package. Solder balls connect the BGA package to a printed circuit board (PCB). A current sense loop can be fabricated on a wiring plane of the PCB to encircle a current supply via that supplies current to an IC mounted on the BGA package. A MUX/Sequencer can sequentially connect wires of the current sense loop to an amplifier. The amplifier can amplify a voltage induced on the current sense mesh by current flow into the BGA package. A sensing analog-to-digital converter (ADC) is electrically connected to convert a voltage at the output of the amplifier into digital output signals.

Abstract: In one or more embodiments, a semiconductor package device includes a substrate, a trace, a structure, a barrier element and an underfill. The substrate has a first surface including a filling region surrounded by the trace. The structure is disposed over the filling region and electrically connected to the substrate. The barrier element is disposed on the trace. The underfill is disposed on the filling region.

Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

Abstract: A chip mounting structure and a chip mounting device are provided. The chip mounting structure includes a circuit substrate and a plurality of micro heaters. The circuit substrate has a plurality of solder pads. A plurality of micro heaters are disposed on the circuit substrate adjacent to the solder pad. The plurality of chips are disposed on the circuit substrate, and the chip is electrically connected to the solder pad by a solder ball. Therefore, the soldering yield of the process can be reduced by the chip mounting structure and the chip mounting device.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: A package structure is provided. The package structure includes a leadframe, a device, first protrusions, second protrusions, a conductive unit, and an encapsulation material. The device includes a substrate, an active layer, first electrodes, second electrodes and a third electrode. The first electrodes have different potentials than the second electrodes. The first electrodes and the second electrodes are arranged so that they alternate with each other. The first protrusions are disposed on each of the first electrodes. The second protrusions are disposed on each of the second electrodes. The first protrusions and the second protrusions are connected to the leadframe. The first side of the conductive unit is connected to the substrate of the device. The conductive unit is connected to the leadframe. The encapsulation material covers the device and the leadframe. The second side of the conductive unit is exposed from the encapsulation material.

Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.

Abstract: A chip on film package includes: a base substrate having an output pad region; a plurality of output pads disposed in the output pad region of the base substrate, wherein the output pads are arranged in a zigzag configuration on the base substrate; a plurality of output pad wirings connected to the output pads, respectively; and a protection layer disposed on the output pad wirings. The protection layer is disposed on the output pad wirings disposed between two adjacent output pads, arranged in a first direction.

Abstract: A size reduction of an image pickup module by using resin molding, including a reduction in height, area, or the like thereof is achieved in an actual product. Provided is a module, including a substrate; a semiconductor component in which a first surface of a semiconductor device manufactured by chip-size packaging is provided and fixed along a plate-shaped translucent member, and a second surface of the semiconductor device is fixed with the second surface caused to face the substrate; a frame portion made of resin and formed on the substrate to surround the semiconductor component; and an interposition member which is made of resin and with which a gap between the semiconductor component and the substrate is filled. The interposition member is connected and fixed to the frame portion to be integrated therewith.

Abstract: A method of making a semiconductor device includes determining a temperature profile for a first die of a three-dimensional integrated circuit (3DIC), wherein the first die comprises a plurality of sub-regions of the first die based on the determined temperature profile. The method further includes simulating operation of a circuit in a second die of the 3DIC based on the determined temperature profile and a corresponding sub-region of the plurality of sub-regions.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: A semiconductor chip includes a compound semiconductor substrate having a pair of main surfaces and a side surface therebetween, a circuit on one main surface of the pair of main surfaces, and first metals on the main surface. The first metals are positioned, in plan view of the main surface, closer to an outer edge of the main surface than the circuit, substantially in a ring shape to surround the circuit with gaps between first metals adjacent to each other. The semiconductor chip further includes second metals on the main surface. The second metals are positioned, in plan view of the main surface, between the circuit and the first metals or closer to the outer edge than the first metals. Also, the second metals each are positioned, in plan view of the side surface, such that at least a part thereof overlaps a gap between the first metals.

Abstract: Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.

Abstract: According to one embodiment, a semiconductor device comprises a circuit board and a semiconductor package mounted on the circuit board. The semiconductor package comprises a semiconductor chip, a first connector on a bottom surface of the semiconductor package and electrically connected to the semiconductor chip, and a metal bump coupled to the first connector and electrically connected to a second connector on the circuit board. The first connector has a contact surface facing the second connector. The contact surface has a recessed portion into which the metal bump extends.

Abstract: A method of manufacturing packages includes forming grooves with a depth that reaches a finished thickness of a device chip along planned dividing lines from a front surface of a device wafer, sealing the front surface of the device wafer by a sealant and filling the grooves with the sealant, and grinding a back surface of the device wafer corresponding to a device region to form a recessed part with a depth that reaches the grooves and forms an annular projection part that surrounds the recessed part and corresponds to a peripheral surplus region. The recessed part is filled with the sealant to execute sealing and dividing grooves are formed with a smaller width than the grooves along the grooves from the front surface of the device wafer. The device wafer is divided to form plural packages in each of which the device chip is sealed by the sealant.

Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.

Abstract: An objective is to provide a stretchable conductor sheet which is useful as a material for electrical wiring and electrodes for garment-type electronic devices, the material having excellent durability in terms of washing and durability in terms of perspiration. A fabric provided with an electrode and an electrical wiring, which are formed from a stretchable conductor sheet, is obtained by: providing a film having releasability with a first stretchable conductor layer which is formed from a paste material that uses carbon-based particles as a conductive filler, while using a flexible resin as a binder resin; subsequently forming a second stretchable conductor layer, while using metal-based particles as a conductive filler; laminating a hot melt adhesive layer thereon; superposing the resulting laminate on a fabric after removing unnecessary parts from the laminate by means of partial slits; and subjecting the resulting fabric to hot pressing.

Abstract: An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.

Abstract: A semiconductor package and a manufacturing method of a semiconductor package are provided. The semiconductor package includes a device die, a redistribution structure, a heat dissipation module and a molding compound. The redistribution structure is disposed at a front side of the device die. The heat dissipation module includes a thermal interfacial layer and a metal lid. The thermal interfacial layer is in direct contact with a back side of the device die, and located between the device die and the metal lid. The molding compound is disposed between the redistribution structure and the heat dissipation module, and has a body portion and an extended portion. The device die is located in the extended portion. The body portion laterally surrounds the extended portion. The extended portion is thicker than the body portion.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure being electrically connect to the integrated circuit die, the redistribution structure including a pad; a passive device including a conductive connector physically and electrically connected to the pad; and a protective structure disposed between the passive device and the redistribution structure, the protective structure surrounding the conductive connector, the protective structure including an epoxy flux, the protective structure having a void disposed therein.

Abstract: Electronic package arrangements and related methods are disclosed that provide one or more of improved thermal management and electromagnetic shielding. Electronic packages are disclosed that include arrangements of one or more electronic devices, overmold bodies, and heat spreaders or metal frame structures. The heat spreaders or metal frame structures may be arranged over the electronic devices to form heat dissipation paths that draw operating heat away from the electronic devices in one or more directions including above and below the electronic packages. The heat spreaders or metal frame structures may also be arranged to form electromagnetic shields that reduce crosstalk between the electronic devices within the electronic packages and to suppress unwanted emissions from either escaping or entering the electronic packages.

Abstract: A novel organic compound that is effective in improving the element characteristics and reliability is provided. The organic compound, which is represented by General Formula (G1), has a structure in which a dibenzoquinazoline ring is bonded to a skeleton with a hole-transport property via one or more arylene groups. Any one of R1 to R9 in General Formula (G1) is bonded to any one of R10 to R14 in General Formula (G1-1). Note that n is any of 0 to 3; m is 1 or 2; A represents a single bond, or an arylene group; B represents a ring having a dibenzofuran skeleton, dibenzothiophene skeleton, or carbazole skeleton; and each of R1 to R15 independently represents any of hydrogen, an alkyl group, a cycloalkyl group, and an aryl group.

Abstract: A chip radio frequency package includes a substrate including a first cavity, first and second connection members, a core member, a radio frequency integrated circuit (RFIC) disposed on an upper surface of the substrate, and a first front-end integrated circuit (FEIC) disposed in the first cavity. The core member includes a core insulating layer and a core via that penetrates the core insulating layer. The first connection member has a structure in which a first insulating layer and a first wiring layer are stacked. The second connection member has a second structure in which a second insulating layer and a second wiring layer are stacked. The RFIC inputs or outputs a base signal and a first radio frequency (RF) signal having a frequency higher than a frequency of the base signal, and the first FEIC inputs or outputs the first RF signal and a second RF signal.

Abstract: A chip package structure, comprises a first chip having a plurality of first chip joints at a lower side thereof; a circuit board below the first chip; an upper side of the circuit board being arranged with a plurality of circuit board joints; in packaging, the first chip joints being combined with the circuit board joints of the circuit board so that the first chip is combined to the circuit board by a way of ACF combination or convex joint combination; and wherein in the ACF combination, ACFs are used as welding points to be combined to the pads at another end so that the chip is combined to the circuit board; and wherein in the convex pad combination, a convex pad is combined with a flat pad by chemically methods or physical methods; and these pads are arranged on the circuit board and the first chip.

Abstract: In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.

Abstract: A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.

Abstract: An electronic component includes a circuit substrate, a connecting electrode, a micro-element, and a solder. The connecting electrode is located on the circuit substrate. The connecting electrode has a first transparent conductive layer. A surface of the first transparent conductive layer is located opposite the circuit substrate, and has a plurality of micrometers or nanometer particles. The micro-element is electrically connected to the connecting electrode. The solder is located between the connecting electrode and the micro-element, and fixes the micro-element on the connecting electrode.

Abstract: A semiconductor package includes a frame having a through-hole, and a first semiconductor chip disposed in the through-hole of the frame and having an active surface on which a connection pad is disposed, an inactive surface opposing the active surface, and a side surface connecting the active and inactive surfaces. A first encapsulant covers at least a portion of each of the inactive surface and the side surface of the first semiconductor chip. A connection structure has a first surface having disposed thereon the active surface of the first semiconductor chip, and includes a redistribution layer electrically connected to the connection pad of the first semiconductor chip. A first passive component is disposed on a second surface of the connection structure opposing the first surface, the first passive component being electrically connected to the redistribution layer and having a thickness greater than a thickness of the first semiconductor chip.

Abstract: A method performed by an endpoint connected to a network. The method includes computing a security score for the endpoint and providing the security score and a requested domain name to a domain name service (DNS) resolver using a DNS request. The endpoint obtains a DNS response including an Internet Protocol (IP) address resolved by the DNS resolver based on the security score and the requested domain name. The endpoint then accesses the IP address obtained from the DNS resolver.

Abstract: A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, and having the active surface disposed on the connection structure to face the connection structure, and an encapsulant covering at least a portion of the semiconductor chip, wherein the semiconductor chip includes a groove formed in the active surface, and the groove has a shape in which a width of a region of at least a portion of an internal region located closer to a central portion of the semiconductor chip than the active surface is greater than a width of an entrance region.

Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.