Solder Wettable Contact, Lead, Or Bond Patents (Class 257/779)
  • Patent number: 11322407
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet, pushing up each device chip through the polyester sheet, and picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: May 3, 2022
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11309188
    Abstract: A method of singulating a silicon carbide (SiC) semiconductor wafer can include defining a cut within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation where the SiC semiconductor wafer is aligned along a plane and the cut has a depth less than a first thickness of the SiC semiconductor wafer. The cut is aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the SiC semiconductor wafer. The method can further include defining a cleave, by performing a cleaving operation, through the portion of the SiC semiconductor wafer having the second thickness. The cleave can be aligned with the cut and extending to the outer surface of the SiC semiconductor wafer.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: April 19, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Aira Lourdes Villamor
  • Patent number: 11276610
    Abstract: A wiring board includes a wiring layer; a diffusion suppressing layer that covers the wiring layer and suppresses diffusion of a metal component of the wiring layer; a base metal layer that covers the diffusion suppressing layer; and a passivation layer that covers the base metal layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: March 15, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Masaru Morita
  • Patent number: 11211378
    Abstract: Three-dimensional (3D) semiconductor memory structures and methods of forming 3D semiconductor memory structures are provided. The 3D semiconductor memory structure includes a chip comprising a memory and Through-Silicon Vias (TSVs). The 3D semiconductor memory structure further includes a hardware accelerator arranged on and coupled face-to-face to the above chip. The 3D semiconductor memory structure also includes a substrate arranged under the under the (3D) semiconductor memory structure and the hardware accelerator and attached to the TSVs and external inputs and outputs of the memory chip and the hardware accelerator.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta G. Farooq, Arvind Kumar
  • Patent number: 11202370
    Abstract: The present application discloses an integrated circuit chip. The integrated circuit chip includes an integrated circuit; a bonding pad on the integrated circuit and electrically connected to the integrated circuit; a first insulating layer on a side of the bonding pad distal to the integrated circuit; and a solder bump on a side of the first insulating layer distal to the bonding pad, and electrically connected to the bonding pad. An orthographic projection of the first insulating layer on a plane containing a surface of the integrated circuit substantially covers an orthographic projection of the solder bump on the plane containing the surface of the integrated circuit.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 14, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Liqiang Chen
  • Patent number: 11133236
    Abstract: A structure includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die, and a cavity in the encapsulating material. The cavity penetrates through the encapsulating material.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Hao-Yi Tsai
  • Patent number: 11127708
    Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 11056451
    Abstract: A semiconductor device manufacturing method includes forming an organic insulating layer on a semiconductor on which metal wiring is provided, the organic insulating layer having an opening to expose part of the metal wiring, forming a seed metal covering the part of the metal wiring exposed from the opening, and an inside face and an around portion of the opening of the organic insulating layer, forming a mask covering an edge of the seed metal and exposing part of the seed metal formed in the opening, and forming a barrier metal on the seed metal exposed from the mask by electroless plating. The mask includes an organic material or an inorganic dielectric material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 6, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Keita Matsuda
  • Patent number: 11031364
    Abstract: In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: June 8, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Daniel Lee Revier, Sadia Naseem, Mahmud Halim Chowdhury
  • Patent number: 11011421
    Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 11011494
    Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 18, 2021
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Rajesh Katkar, Ilyas Mohammed, Cyprian Emeka Uzoh
  • Patent number: 10950568
    Abstract: A semiconductor device assembly is provided. The assembly includes a first package element and a second package element disposed over the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface-mounted to the first package element and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad. The first height is about equal to a sum of the solder joint thickness and the second height.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Benjamin L. McClain
  • Patent number: 10923447
    Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, David R. Hembree
  • Patent number: 10872850
    Abstract: A package structure includes a semiconductor device, a first redistribution line, a dielectric layer, a first conductive bump and a first sealing structure. The dielectric layer is over the first redistribution line and has a first opening therein. The first conductive bump is partially embedded in the first opening and electrically connected to the first redistribution line. The first sealing structure surrounds a bottom portion of the first conductive bump. The first sealing structure has a curved surface extending from an outer surface of the bottom portion of the first conductive bump to a top surface of the dielectric layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 10840022
    Abstract: An electronic component includes a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed in a width direction. The capacitor body has first to sixth surfaces, the first and second internal electrodes being exposed through the third and fourth surfaces, respectively. First and second external electrodes are disposed on the third and fourth surfaces and extend to portions of the first surface. A first connection terminal and a second connection terminal are disposed to be respectively connected to be connected to the first and second external electrodes, and each has a shape including at least one indentation in a rectangular outline within which the respective connection terminal is inscribed.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Chul Sim, Gu Won Ji, Heung Kil Park, Young Ghyu Ahn, Se Hun Park
  • Patent number: 10790218
    Abstract: A semiconductor device according to the present invention includes a relay substrate provided on a plurality of semiconductor chips. The relay substrate includes an insulating plate in which a through hole is formed, a lower conductor provided on a lower surface of the insulating plate and having a first lower conductor and a second lower conductor, an upper conductor provided on an upper surface of the insulating plate, a connection part provided in the through hole and connecting the second lower conductor and the upper conductor together, and a protruding part which is a part of one of the first lower conductor and the upper conductor and protrudes outward from the insulating plate, the protruding part is connected to a first external electrode, and another of the first lower conductor and the upper conductor is connected to a second external electrode and is positioned inside the insulating plate.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 29, 2020
    Assignee: Mitsubishi Electric Corpration
    Inventors: Hidetoshi Ishibashi, Hiroshi Yoshida, Daisuke Murata, Takuya Kitabayashi
  • Patent number: 10788385
    Abstract: Provided is a physical quantity measurement device in which a bonding temperature of a bonding layer is lowered to a temperature not affecting an operation of a semiconductor chip and an insulating property of the semiconductor chip and a base is secured. The physical quantity measurement device includes a base (diaphragm), a semiconductor chip (strain detection element) to measure a physical quantity on the basis of stress acting on the base, and a bonding layer to bond the semiconductor chip to the base. The bonding layer has a first bonding layer bonded to the semiconductor chip, a second bonding layer bonded to the base, and an insulating base material disposed between the first bonding layer and the second bonding layer. The first and second bonding layers and contain glass.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: September 29, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Takuya Aoyagi, Takashi Naitou, Tatsuya Miyake, Mizuki Shibata, Hiroshi Onuki, Daisuke Terada, Shigenobu Komatsu
  • Patent number: 10784160
    Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 10777528
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: September 15, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim, Byung Joon Han
  • Patent number: 10741402
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 10692830
    Abstract: A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1<a2. The first Ni alloy layer is between the Cu layer and the second Ni alloy layer. The structure further includes a tin (Sn) layer. The second Ni alloy layer is between the first Ni alloy layer and the Sn layer.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: June 23, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone
  • Patent number: 10651162
    Abstract: A display device including a display panel including a substrate, pixels provided on the substrate, and first lines connected to the pixels, the display device having a bending area where the display panel is bent. The display panel also includes a chip on film overlapping with a portion of the display panel and having second lines, an anisotropic conductive film provided between the chip on film and the display panel connecting the first lines and the second lines, and a coating layer covering the bending area and one end of the chip on film. In such a device, lines of the chip on film may be prevented from being corroded as they may be spaced apart from an edge of an insulating film.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 12, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun Namkung, Soon Ryong Park, Ju Yeop Seong, Hyun Kyu Choi
  • Patent number: 10636759
    Abstract: The disclosure is directed to an integrated circuit structure for joining wafers. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mukta G. Farooq, Tanya A. Atanasova
  • Patent number: 10622287
    Abstract: A semiconductor package is provided, including: a package body; and a plurality of lead terminals exposed from each of at least three side surfaces of the package body, wherein the plurality of lead terminals include: a plurality of lead terminals exposed from a first side surface, half or more of which have tips pointing in a direction along the first side surface; a plurality of lead terminals exposed from a second side surface, all of which have tips pointing in a direction along a direction orthogonal to the second side surface; and a plurality of lead terminals exposed from a third side surface, half or more of which have tips pointing in a direction along the third side surface, or all of which have tips pointing in a direction along a direction orthogonal to the third side surface.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Kogawa, Takahiro Nishijima, Takashi Katsuki, Tadahiko Sato
  • Patent number: 10622285
    Abstract: An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes: preparing a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element having an element main surface and an element back surface that face opposite sides to each other; die bonding the element back surface of the first semiconductor element to a pad main surface by using a first solder; and die bonding the element back surface of the second semiconductor element to the pad main surface by using a second solder having a melting point lower than a melting point of the first solder, after die bonding the element back surface of the first semiconductor element to the pad main surface by using the first solder.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 14, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Koshun Saito, Katsuhiro Iwai
  • Patent number: 10608131
    Abstract: Disclosed is a solar cell including: a solar cell including an electrode; a wiring portion electrically connected to the electrode of the solar cell; a connection member positioned between the electrode and the wiring portion at a connection portion of the electrode and the wiring portion to electrically connect the electrode and the wiring portion; and an insulating layer covering the electrode entirely where the connection member is not positioned to insulate the electrode and the wiring portion at a portion other than the connection portion. The insulating layer includes an organic solderability preservative (OSP).
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 31, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Daeseon Hyun, Ayoung Bak
  • Patent number: 10510643
    Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: December 17, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mark Allen Gerber
  • Patent number: 10475759
    Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Chen-Hua Yu, Jing-Cheng Lin
  • Patent number: 10350712
    Abstract: A solder paste whereby metal does not flow out of a joint during a second or subsequent reflow heating stage. The solder paste exhibits high joint strength at room temperature and at high temperatures, excels in terms of temporal stability, exhibits minimal void formation, and can form highly cohesive joints. The solder paste comprises a powdered metal component and a flux component, the powdered metal component comprising: a powdered intermetallic compound that comprises copper and tin and has metal barrier layers covering the surfaces thereof and a solder powder including tin as a main component. Neither the powdered intermetallic compound nor the solder powder contains a copper-only phase, inhibiting the elution of copper ions into the flux.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 16, 2019
    Assignee: SENJU METAL INDUSTRY CO., LTD.
    Inventors: Motoki Koroki, Shunsaku Yoshikawa, Sakie Okada, Taro Itoyama, Hideyuki Komuro, Naoko Hirai, Keitaro Shimizu
  • Patent number: 10300562
    Abstract: In a solder alloy consisting essentially of tin, silver, copper, bismuth, antimony, indium, and nickel, the content ratio of the silver is 0.05 mass % or more and below 0.2 mass %; the content ratio of the copper is 0.1 mass % or more and 1 mass % or less; the content ratio of the bismuth is above 4.0 mass % and 10 mass % or less; the content ratio of the antimony is 0.005 mass % or more and 8 mass % or less; the content ratio of the indium is 0.005 mass % or more and 2 mass % or less; the content ratio of the nickel is 0.003 mass % or more and 0.4 mass % or less; and the content ratio of the tin is the remaining ratio and the mass ratio (Bi/Ni) of the bismuth content with respect to the nickel content is 35 or more and 1500 or less.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 28, 2019
    Assignee: HARIMA CHEMICALS, INCORPORATED
    Inventors: Shunsuke Ishikawa, Kensuke Nakanishi, Yuka Matsushima, Tadashi Takemoto
  • Patent number: 10269785
    Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 10249565
    Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 2, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Miyagawa, Hideki Fujii, Kenji Furuya
  • Patent number: 10229630
    Abstract: A passive-matrix light-emitting diodes on silicon (LEDoS) micro-display is presented herein. The LEDoS micro-display comprises a passive-matrix micro-light-emitting diode (LED) array comprising passive-matrix micro-light-emitting diodes (LEDs), and a display driver configured to apply column signals to columns of LED pixels of the passive-matrix micro-LED array and scan signals to rows of the LED pixels, wherein the passive-matrix micro-LED array is flip-chip bonded to the display driver based on solder bumps located at peripheral areas of the passive-matrix micro-LED array.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: March 12, 2019
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Kei May Lau, Zhaojun Liu, Wing Cheung Chong, Wai Keung Cho, Chu Hong Wang
  • Patent number: 10213880
    Abstract: In a solder alloy consisting essentially of tin, silver, copper, bismuth, antimony, indium, and nickel, the content ratio of the silver is 0.05 mass % or more and below 0.2 mass %; the content ratio of the copper is 0.1 mass % or more and 1 mass % or less; the content ratio of the bismuth is above 4.0 mass % and 10 mass % or less; the content ratio of the antimony is 0.005 mass % or more and 8 mass % or less; the content ratio of the indium is 0.005 mass % or more and 2 mass % or less; the content ratio of the nickel is 0.003 mass % or more and 0.4 mass % or less; and the content ratio of the tin is the remaining ratio and the mass ratio (Bi/Ni) of the bismuth content with respect to the nickel content is 35 or more and 1500 or less.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 26, 2019
    Assignee: HARIMA CHEMICALS, INCORPORATED
    Inventors: Shunsuke Ishikawa, Kensuke Nakanishi, Yuka Matsushima, Tadashi Takemoto
  • Patent number: 10147690
    Abstract: A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 4, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shuuichi Kariyazaki
  • Patent number: 10141201
    Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a package substrate. A heat dissipation feature is attached on a first side of the first die. A second die is mounted on a second side of the first die, wherein the second die is at least partially disposed in a through hole formed in the package substrate. An encapsulant is formed on the first side of the package substrate around the first die.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chi-Yang Yu, Jung Wei Cheng, Chin-Liang Chen
  • Patent number: 10103095
    Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: October 16, 2018
    Assignee: Compass Technology Company Limited
    Inventors: Kelvin Po Leung Pun, Chee Wah Cheung
  • Patent number: 9991163
    Abstract: A small-aperture-ratio display includes a display substrate and a plurality of spatially separated pixel elements distributed over the display substrate. Each pixel element includes one or more light emitters. An active electrical component is electrically connected to each of the pixel elements and each active electrical component is located on the display substrate at least partly between the pixel elements. The display substrate has a contiguous display substrate area that includes the pixel elements, the light emitters each have a light-emissive area, and the substrate area is greater than or equal to one-quarter the combined light-emissive areas of the light emitters.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 5, 2018
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Robert R. Rotzoll, Matthew Meitl, Ronald S. Cok
  • Patent number: 9966321
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Patent number: 9877386
    Abstract: A substrate structure is provided, including: a carrier having at least a wiring area defined and positioned on a portion of a surface of the carrier; a first insulating layer formed on the wiring area; a wiring layer formed on the first insulating layer formed on the wiring area; and a second insulating layer formed on the wiring area. Therefore, a contact surface between the carrier and the first and second insulating layers is reduced by reducing the areas of the first and second insulating layers, whereby a substrate warpage due to mismatch of coefficients of thermal expansion (CTE) is avoided. The present invention further provides a method of manufacturing the substrate structure as described above.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: January 23, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-An Chang, Sung-Huan Sun, Chien-Hung Wu, Yi-Cheih Chen, Wen-Kai Liao
  • Patent number: 9859227
    Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kenneth P. Rodbell
  • Patent number: 9831210
    Abstract: An electronic device includes an electrode including Cu, a solder including Sn and provided above the electrode, and a joining layer including In and Ag and provided along a boundary between the electrode and the solder. The joining layer including In and Ag prevents Cu—Sn alloy, such as Cu6Sn5, from being formed at the boundary between the electrode and the solder, and prevents generation of voids and cracks resulting from the Cu—Sn alloy. The electrode and the solder are joined with sufficient strength by the joining layer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Taiki Uemura, Seiki Sakuyama
  • Patent number: 9796828
    Abstract: An epoxy resin composition, comprising an epoxy resin, a curing agent, a curing accelerator, an inorganic filler, and a carboxylic acid compound that satisfies at least one selected from the group consisting of the following A, B and C below: A: having at least one carboxy group and at least one hydroxy group; B: having at least two carboxy groups; and C: having a structure in which two carboxy groups are condensed by dehydration.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: October 24, 2017
    Assignee: HITACHI CHEMICAL COMPANY, LTD
    Inventors: Yuta Ono, Mitsuaki Fusumada, Hironori Kobayashi, Yuya Kitagawa, Teruyoshi Hasegawa
  • Patent number: 9704824
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.
    Type: Grant
    Filed: November 2, 2013
    Date of Patent: July 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim, Byung Joon Han
  • Patent number: 9659894
    Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, and buffer layers having a Young's Modulus of 2.5 GPa or less.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 23, 2017
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventor: Simon Jonathan Stacey
  • Patent number: 9640466
    Abstract: A method of manufacturing a packaged semiconductor device includes patterning and plating silver nanoparticles in bonding areas of a lead frame, forming a hydrophilic group while oxidizing the silver nanoparticles, forming wire bonds on the silver nanoparticles, and encapsulating the wire bonds and the silver nanoparticles.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 2, 2017
    Assignee: NXP USA, Inc.
    Inventors: Varughese Mathew, Sheila Chopin
  • Patent number: 9576873
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: February 21, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9548280
    Abstract: A solder ball pad for mounting a solder ball of a semiconductor device for preventing delamination of an overlying dielectric layer, and particularly devices and methods providing improved solder ball pad structures in a device such as a semiconductor device package.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: January 17, 2017
    Assignee: NXP USA, INC.
    Inventors: Vijay Sarihan, Zhiwei Gong, Scott M. Hayes
  • Patent number: 9545013
    Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 10, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9401308
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu