Solder Wettable Contact, Lead, Or Bond Patents (Class 257/779)
  • Patent number: 10840022
    Abstract: An electronic component includes a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed in a width direction. The capacitor body has first to sixth surfaces, the first and second internal electrodes being exposed through the third and fourth surfaces, respectively. First and second external electrodes are disposed on the third and fourth surfaces and extend to portions of the first surface. A first connection terminal and a second connection terminal are disposed to be respectively connected to be connected to the first and second external electrodes, and each has a shape including at least one indentation in a rectangular outline within which the respective connection terminal is inscribed.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Chul Sim, Gu Won Ji, Heung Kil Park, Young Ghyu Ahn, Se Hun Park
  • Patent number: 10790218
    Abstract: A semiconductor device according to the present invention includes a relay substrate provided on a plurality of semiconductor chips. The relay substrate includes an insulating plate in which a through hole is formed, a lower conductor provided on a lower surface of the insulating plate and having a first lower conductor and a second lower conductor, an upper conductor provided on an upper surface of the insulating plate, a connection part provided in the through hole and connecting the second lower conductor and the upper conductor together, and a protruding part which is a part of one of the first lower conductor and the upper conductor and protrudes outward from the insulating plate, the protruding part is connected to a first external electrode, and another of the first lower conductor and the upper conductor is connected to a second external electrode and is positioned inside the insulating plate.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 29, 2020
    Assignee: Mitsubishi Electric Corpration
    Inventors: Hidetoshi Ishibashi, Hiroshi Yoshida, Daisuke Murata, Takuya Kitabayashi
  • Patent number: 10788385
    Abstract: Provided is a physical quantity measurement device in which a bonding temperature of a bonding layer is lowered to a temperature not affecting an operation of a semiconductor chip and an insulating property of the semiconductor chip and a base is secured. The physical quantity measurement device includes a base (diaphragm), a semiconductor chip (strain detection element) to measure a physical quantity on the basis of stress acting on the base, and a bonding layer to bond the semiconductor chip to the base. The bonding layer has a first bonding layer bonded to the semiconductor chip, a second bonding layer bonded to the base, and an insulating base material disposed between the first bonding layer and the second bonding layer. The first and second bonding layers and contain glass.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: September 29, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Takuya Aoyagi, Takashi Naitou, Tatsuya Miyake, Mizuki Shibata, Hiroshi Onuki, Daisuke Terada, Shigenobu Komatsu
  • Patent number: 10784160
    Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 10777528
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: September 15, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim, Byung Joon Han
  • Patent number: 10741402
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 10692830
    Abstract: A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1<a2. The first Ni alloy layer is between the Cu layer and the second Ni alloy layer. The structure further includes a tin (Sn) layer. The second Ni alloy layer is between the first Ni alloy layer and the Sn layer.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: June 23, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone
  • Patent number: 10651162
    Abstract: A display device including a display panel including a substrate, pixels provided on the substrate, and first lines connected to the pixels, the display device having a bending area where the display panel is bent. The display panel also includes a chip on film overlapping with a portion of the display panel and having second lines, an anisotropic conductive film provided between the chip on film and the display panel connecting the first lines and the second lines, and a coating layer covering the bending area and one end of the chip on film. In such a device, lines of the chip on film may be prevented from being corroded as they may be spaced apart from an edge of an insulating film.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: May 12, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun Namkung, Soon Ryong Park, Ju Yeop Seong, Hyun Kyu Choi
  • Patent number: 10636759
    Abstract: The disclosure is directed to an integrated circuit structure for joining wafers. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mukta G. Farooq, Tanya A. Atanasova
  • Patent number: 10622287
    Abstract: A semiconductor package is provided, including: a package body; and a plurality of lead terminals exposed from each of at least three side surfaces of the package body, wherein the plurality of lead terminals include: a plurality of lead terminals exposed from a first side surface, half or more of which have tips pointing in a direction along the first side surface; a plurality of lead terminals exposed from a second side surface, all of which have tips pointing in a direction along a direction orthogonal to the second side surface; and a plurality of lead terminals exposed from a third side surface, half or more of which have tips pointing in a direction along the third side surface, or all of which have tips pointing in a direction along a direction orthogonal to the third side surface.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: April 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Kogawa, Takahiro Nishijima, Takashi Katsuki, Tadahiko Sato
  • Patent number: 10622285
    Abstract: An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes: preparing a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element having an element main surface and an element back surface that face opposite sides to each other; die bonding the element back surface of the first semiconductor element to a pad main surface by using a first solder; and die bonding the element back surface of the second semiconductor element to the pad main surface by using a second solder having a melting point lower than a melting point of the first solder, after die bonding the element back surface of the first semiconductor element to the pad main surface by using the first solder.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 14, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Koshun Saito, Katsuhiro Iwai
  • Patent number: 10608131
    Abstract: Disclosed is a solar cell including: a solar cell including an electrode; a wiring portion electrically connected to the electrode of the solar cell; a connection member positioned between the electrode and the wiring portion at a connection portion of the electrode and the wiring portion to electrically connect the electrode and the wiring portion; and an insulating layer covering the electrode entirely where the connection member is not positioned to insulate the electrode and the wiring portion at a portion other than the connection portion. The insulating layer includes an organic solderability preservative (OSP).
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 31, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Daeseon Hyun, Ayoung Bak
  • Patent number: 10510643
    Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: December 17, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mark Allen Gerber
  • Patent number: 10475759
    Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Chen-Hua Yu, Jing-Cheng Lin
  • Patent number: 10350712
    Abstract: A solder paste whereby metal does not flow out of a joint during a second or subsequent reflow heating stage. The solder paste exhibits high joint strength at room temperature and at high temperatures, excels in terms of temporal stability, exhibits minimal void formation, and can form highly cohesive joints. The solder paste comprises a powdered metal component and a flux component, the powdered metal component comprising: a powdered intermetallic compound that comprises copper and tin and has metal barrier layers covering the surfaces thereof and a solder powder including tin as a main component. Neither the powdered intermetallic compound nor the solder powder contains a copper-only phase, inhibiting the elution of copper ions into the flux.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 16, 2019
    Assignee: SENJU METAL INDUSTRY CO., LTD.
    Inventors: Motoki Koroki, Shunsaku Yoshikawa, Sakie Okada, Taro Itoyama, Hideyuki Komuro, Naoko Hirai, Keitaro Shimizu
  • Patent number: 10300562
    Abstract: In a solder alloy consisting essentially of tin, silver, copper, bismuth, antimony, indium, and nickel, the content ratio of the silver is 0.05 mass % or more and below 0.2 mass %; the content ratio of the copper is 0.1 mass % or more and 1 mass % or less; the content ratio of the bismuth is above 4.0 mass % and 10 mass % or less; the content ratio of the antimony is 0.005 mass % or more and 8 mass % or less; the content ratio of the indium is 0.005 mass % or more and 2 mass % or less; the content ratio of the nickel is 0.003 mass % or more and 0.4 mass % or less; and the content ratio of the tin is the remaining ratio and the mass ratio (Bi/Ni) of the bismuth content with respect to the nickel content is 35 or more and 1500 or less.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 28, 2019
    Assignee: HARIMA CHEMICALS, INCORPORATED
    Inventors: Shunsuke Ishikawa, Kensuke Nakanishi, Yuka Matsushima, Tadashi Takemoto
  • Patent number: 10269785
    Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 10249565
    Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 2, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Miyagawa, Hideki Fujii, Kenji Furuya
  • Patent number: 10229630
    Abstract: A passive-matrix light-emitting diodes on silicon (LEDoS) micro-display is presented herein. The LEDoS micro-display comprises a passive-matrix micro-light-emitting diode (LED) array comprising passive-matrix micro-light-emitting diodes (LEDs), and a display driver configured to apply column signals to columns of LED pixels of the passive-matrix micro-LED array and scan signals to rows of the LED pixels, wherein the passive-matrix micro-LED array is flip-chip bonded to the display driver based on solder bumps located at peripheral areas of the passive-matrix micro-LED array.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: March 12, 2019
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Kei May Lau, Zhaojun Liu, Wing Cheung Chong, Wai Keung Cho, Chu Hong Wang
  • Patent number: 10213880
    Abstract: In a solder alloy consisting essentially of tin, silver, copper, bismuth, antimony, indium, and nickel, the content ratio of the silver is 0.05 mass % or more and below 0.2 mass %; the content ratio of the copper is 0.1 mass % or more and 1 mass % or less; the content ratio of the bismuth is above 4.0 mass % and 10 mass % or less; the content ratio of the antimony is 0.005 mass % or more and 8 mass % or less; the content ratio of the indium is 0.005 mass % or more and 2 mass % or less; the content ratio of the nickel is 0.003 mass % or more and 0.4 mass % or less; and the content ratio of the tin is the remaining ratio and the mass ratio (Bi/Ni) of the bismuth content with respect to the nickel content is 35 or more and 1500 or less.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 26, 2019
    Assignee: HARIMA CHEMICALS, INCORPORATED
    Inventors: Shunsuke Ishikawa, Kensuke Nakanishi, Yuka Matsushima, Tadashi Takemoto
  • Patent number: 10147690
    Abstract: A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 4, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shuuichi Kariyazaki
  • Patent number: 10141201
    Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a package substrate. A heat dissipation feature is attached on a first side of the first die. A second die is mounted on a second side of the first die, wherein the second die is at least partially disposed in a through hole formed in the package substrate. An encapsulant is formed on the first side of the package substrate around the first die.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chi-Yang Yu, Jung Wei Cheng, Chin-Liang Chen
  • Patent number: 10103095
    Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: October 16, 2018
    Assignee: Compass Technology Company Limited
    Inventors: Kelvin Po Leung Pun, Chee Wah Cheung
  • Patent number: 9991163
    Abstract: A small-aperture-ratio display includes a display substrate and a plurality of spatially separated pixel elements distributed over the display substrate. Each pixel element includes one or more light emitters. An active electrical component is electrically connected to each of the pixel elements and each active electrical component is located on the display substrate at least partly between the pixel elements. The display substrate has a contiguous display substrate area that includes the pixel elements, the light emitters each have a light-emissive area, and the substrate area is greater than or equal to one-quarter the combined light-emissive areas of the light emitters.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 5, 2018
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Robert R. Rotzoll, Matthew Meitl, Ronald S. Cok
  • Patent number: 9966321
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Patent number: 9877386
    Abstract: A substrate structure is provided, including: a carrier having at least a wiring area defined and positioned on a portion of a surface of the carrier; a first insulating layer formed on the wiring area; a wiring layer formed on the first insulating layer formed on the wiring area; and a second insulating layer formed on the wiring area. Therefore, a contact surface between the carrier and the first and second insulating layers is reduced by reducing the areas of the first and second insulating layers, whereby a substrate warpage due to mismatch of coefficients of thermal expansion (CTE) is avoided. The present invention further provides a method of manufacturing the substrate structure as described above.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: January 23, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-An Chang, Sung-Huan Sun, Chien-Hung Wu, Yi-Cheih Chen, Wen-Kai Liao
  • Patent number: 9859227
    Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kenneth P. Rodbell
  • Patent number: 9831210
    Abstract: An electronic device includes an electrode including Cu, a solder including Sn and provided above the electrode, and a joining layer including In and Ag and provided along a boundary between the electrode and the solder. The joining layer including In and Ag prevents Cu—Sn alloy, such as Cu6Sn5, from being formed at the boundary between the electrode and the solder, and prevents generation of voids and cracks resulting from the Cu—Sn alloy. The electrode and the solder are joined with sufficient strength by the joining layer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Taiki Uemura, Seiki Sakuyama
  • Patent number: 9796828
    Abstract: An epoxy resin composition, comprising an epoxy resin, a curing agent, a curing accelerator, an inorganic filler, and a carboxylic acid compound that satisfies at least one selected from the group consisting of the following A, B and C below: A: having at least one carboxy group and at least one hydroxy group; B: having at least two carboxy groups; and C: having a structure in which two carboxy groups are condensed by dehydration.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: October 24, 2017
    Assignee: HITACHI CHEMICAL COMPANY, LTD
    Inventors: Yuta Ono, Mitsuaki Fusumada, Hironori Kobayashi, Yuya Kitagawa, Teruyoshi Hasegawa
  • Patent number: 9704824
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.
    Type: Grant
    Filed: November 2, 2013
    Date of Patent: July 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim, Byung Joon Han
  • Patent number: 9659894
    Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, and buffer layers having a Young's Modulus of 2.5 GPa or less.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 23, 2017
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventor: Simon Jonathan Stacey
  • Patent number: 9640466
    Abstract: A method of manufacturing a packaged semiconductor device includes patterning and plating silver nanoparticles in bonding areas of a lead frame, forming a hydrophilic group while oxidizing the silver nanoparticles, forming wire bonds on the silver nanoparticles, and encapsulating the wire bonds and the silver nanoparticles.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 2, 2017
    Assignee: NXP USA, Inc.
    Inventors: Varughese Mathew, Sheila Chopin
  • Patent number: 9576873
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: February 21, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9548280
    Abstract: A solder ball pad for mounting a solder ball of a semiconductor device for preventing delamination of an overlying dielectric layer, and particularly devices and methods providing improved solder ball pad structures in a device such as a semiconductor device package.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: January 17, 2017
    Assignee: NXP USA, INC.
    Inventors: Vijay Sarihan, Zhiwei Gong, Scott M. Hayes
  • Patent number: 9545013
    Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 10, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9401308
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu
  • Patent number: 9373578
    Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 21, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DaeSik Choi, OhHan Kim, SungWon Cho
  • Patent number: 9369066
    Abstract: The present invention concerns a MEMS device comprising an under bump metallization (4)—UBM—to contact the device via flip-chip bonding with a substrate. The UBM (4) is placed on the surface of the MEMS device and close to the corners of the surface. Further, the shape of the UBM (4) is adapted to the shape of the corners.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: June 14, 2016
    Assignee: EPCOS AG
    Inventors: Leif Steen Johansen, Jan Tue Ravnkilde
  • Patent number: 9362134
    Abstract: A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of the wafer is aligned with and communicated with the second opening of the protection layer. A first insulating layer having a first thickness is formed on a conductive pad exposed from the second opening, and a second insulating layer having a second thickness is formed on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening. The first and second insulating layers are etched, such that the first insulating layer is completely removed, and the second thickness of the second insulating layer is reduced.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: June 7, 2016
    Assignee: XINTEC INC.
    Inventor: Chia-Sheng Lin
  • Patent number: 9326372
    Abstract: A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of solder, penetrating through one of the through-holes, and projecting from both ends of the one of the through-holes, so that the first-electrodes are aligned with the through-holes in a plan view; a second-process for melting the relay-members so that the relay-members are connected to the first-electrodes, after the first-process; and a third-process for placing a semiconductor substrate on which a second-electrodes corresponding to the first-electrodes are formed on a side opposite to the first-substrate across the second-substrate, after the second-process, to connect the first-electrodes and the second-electrodes to each other via the relay-m
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: April 26, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Mamoru Kurashina, Daisuke Mizutani
  • Patent number: 9324630
    Abstract: A cooling fin 9 is joined to a semiconductor element 1. A resin 10 encapsulates the semiconductor element 1. A portion of the cooling fin 9 projects from a lower surface of the resin 10. A cooler 11 has an opening 12. The cooling fin 9 projecting from the resin 10 is inserted in the opening 12 of the cooler 11. The lower surface of the resin 10 and the cooler 11 are joined to each other by a joining material 13 such as an adhesive. Therefore, a reduction in the number of component parts and a reduction in weight can be achieved, and compatibility between the heat conductivity and the strength of joining can be ensured.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 26, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Noboru Miyamoto, Masao Kikuchi
  • Patent number: 9312206
    Abstract: A semiconductor package includes a semiconductor die having an active face and dielectric layers disposed on the active face of the semiconductor die. At least one opening is formed through the dielectric layers and extends from a non-bond pad area of the active face to an exterior surface of the dielectric layers. An electrically conductive layer is formed in the opening and is in physical contact with the active face of the semiconductor die. A thermally conductive material fills the opening to form a thermal via for dissipating heat away from the semiconductor die.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 12, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Weng F. Yap, Scott M. Hayes
  • Patent number: 9281286
    Abstract: Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: March 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Weng F. Yap, Alan J. Magnus
  • Patent number: 9257333
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Hsuan-Ting Kuo, Tsung-Yuan Yu, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9252049
    Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Tsung-Min Huang, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9209121
    Abstract: Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: December 8, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Thomas M. Goida, Xiaojie Xue
  • Patent number: 9196754
    Abstract: A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: November 24, 2015
    Assignee: XINTEC INC.
    Inventor: Chia-Sheng Lin
  • Patent number: 9184144
    Abstract: Pillars having a directed compliance geometry are arranged to couple a semiconductor die to a substrate. The direction of maximum compliance of each pillar may be aligned with the direction of maximum stress caused by unequal thermal expansion and contraction of the semiconductor die and substrate. Pillars may be designed and constructed with various shapes having particular compliance characteristics and particular directions of maximum compliance. The shape and orientation of the pillars may be selected as a function of their location on a die to accommodate the direction and magnitude of stress at their location. A method includes fabricating pillars with particular shapes by patterning to increase surface of materials upon which the pillar is plated or deposited.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: November 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongping Bao, James D. Burrell, Shiqun Gu
  • Patent number: 9177931
    Abstract: Embodiments of the present invention provide a semiconductor structure and method to reduce thermal energy transfer during chip-join processing. In certain embodiments, the semiconductor structure comprises a thermal insulating element formed under a first conductor. The semiconductor structure also comprises a solder bump formed over the first conductor. The semiconductor structure further comprises a second conductor formed on a side of the thermal insulating element and in electrical communication with the first conductor and a third conductor. The third conductor is formed to be in thermal or electrical communication with the thermal insulating element. The thermal insulating element includes thermal insulating material and the thermal insulating element is structured to reduce thermal energy transfer during a chip-join process from the solder bump to a metal level included in the semiconductor structure.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Stephen P. Ayotte, Sebastien Quesnel, Glen E. Richard, Timothy D. Sullivan, Timothy M. Sullivan
  • Patent number: 9171802
    Abstract: A semiconductor device includes a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate includes, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: October 27, 2015
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akira Nakayama