Solder Wettable Contact, Lead, Or Bond Patents (Class 257/779)
  • Patent number: 10350712
    Abstract: A solder paste whereby metal does not flow out of a joint during a second or subsequent reflow heating stage. The solder paste exhibits high joint strength at room temperature and at high temperatures, excels in terms of temporal stability, exhibits minimal void formation, and can form highly cohesive joints. The solder paste comprises a powdered metal component and a flux component, the powdered metal component comprising: a powdered intermetallic compound that comprises copper and tin and has metal barrier layers covering the surfaces thereof and a solder powder including tin as a main component. Neither the powdered intermetallic compound nor the solder powder contains a copper-only phase, inhibiting the elution of copper ions into the flux.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 16, 2019
    Assignee: SENJU METAL INDUSTRY CO., LTD.
    Inventors: Motoki Koroki, Shunsaku Yoshikawa, Sakie Okada, Taro Itoyama, Hideyuki Komuro, Naoko Hirai, Keitaro Shimizu
  • Patent number: 10300562
    Abstract: In a solder alloy consisting essentially of tin, silver, copper, bismuth, antimony, indium, and nickel, the content ratio of the silver is 0.05 mass % or more and below 0.2 mass %; the content ratio of the copper is 0.1 mass % or more and 1 mass % or less; the content ratio of the bismuth is above 4.0 mass % and 10 mass % or less; the content ratio of the antimony is 0.005 mass % or more and 8 mass % or less; the content ratio of the indium is 0.005 mass % or more and 2 mass % or less; the content ratio of the nickel is 0.003 mass % or more and 0.4 mass % or less; and the content ratio of the tin is the remaining ratio and the mass ratio (Bi/Ni) of the bismuth content with respect to the nickel content is 35 or more and 1500 or less.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 28, 2019
    Assignee: HARIMA CHEMICALS, INCORPORATED
    Inventors: Shunsuke Ishikawa, Kensuke Nakanishi, Yuka Matsushima, Tadashi Takemoto
  • Patent number: 10269785
    Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • Patent number: 10249565
    Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 2, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Miyagawa, Hideki Fujii, Kenji Furuya
  • Patent number: 10229630
    Abstract: A passive-matrix light-emitting diodes on silicon (LEDoS) micro-display is presented herein. The LEDoS micro-display comprises a passive-matrix micro-light-emitting diode (LED) array comprising passive-matrix micro-light-emitting diodes (LEDs), and a display driver configured to apply column signals to columns of LED pixels of the passive-matrix micro-LED array and scan signals to rows of the LED pixels, wherein the passive-matrix micro-LED array is flip-chip bonded to the display driver based on solder bumps located at peripheral areas of the passive-matrix micro-LED array.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: March 12, 2019
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Kei May Lau, Zhaojun Liu, Wing Cheung Chong, Wai Keung Cho, Chu Hong Wang
  • Patent number: 10213880
    Abstract: In a solder alloy consisting essentially of tin, silver, copper, bismuth, antimony, indium, and nickel, the content ratio of the silver is 0.05 mass % or more and below 0.2 mass %; the content ratio of the copper is 0.1 mass % or more and 1 mass % or less; the content ratio of the bismuth is above 4.0 mass % and 10 mass % or less; the content ratio of the antimony is 0.005 mass % or more and 8 mass % or less; the content ratio of the indium is 0.005 mass % or more and 2 mass % or less; the content ratio of the nickel is 0.003 mass % or more and 0.4 mass % or less; and the content ratio of the tin is the remaining ratio and the mass ratio (Bi/Ni) of the bismuth content with respect to the nickel content is 35 or more and 1500 or less.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 26, 2019
    Assignee: HARIMA CHEMICALS, INCORPORATED
    Inventors: Shunsuke Ishikawa, Kensuke Nakanishi, Yuka Matsushima, Tadashi Takemoto
  • Patent number: 10147690
    Abstract: A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 4, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shuuichi Kariyazaki
  • Patent number: 10141201
    Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a package substrate. A heat dissipation feature is attached on a first side of the first die. A second die is mounted on a second side of the first die, wherein the second die is at least partially disposed in a through hole formed in the package substrate. An encapsulant is formed on the first side of the package substrate around the first die.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chi-Yang Yu, Jung Wei Cheng, Chin-Liang Chen
  • Patent number: 10103095
    Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: October 16, 2018
    Assignee: Compass Technology Company Limited
    Inventors: Kelvin Po Leung Pun, Chee Wah Cheung
  • Patent number: 9991163
    Abstract: A small-aperture-ratio display includes a display substrate and a plurality of spatially separated pixel elements distributed over the display substrate. Each pixel element includes one or more light emitters. An active electrical component is electrically connected to each of the pixel elements and each active electrical component is located on the display substrate at least partly between the pixel elements. The display substrate has a contiguous display substrate area that includes the pixel elements, the light emitters each have a light-emissive area, and the substrate area is greater than or equal to one-quarter the combined light-emissive areas of the light emitters.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 5, 2018
    Assignee: X-Celeprint Limited
    Inventors: Christopher Bower, Robert R. Rotzoll, Matthew Meitl, Ronald S. Cok
  • Patent number: 9966321
    Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Patent number: 9877386
    Abstract: A substrate structure is provided, including: a carrier having at least a wiring area defined and positioned on a portion of a surface of the carrier; a first insulating layer formed on the wiring area; a wiring layer formed on the first insulating layer formed on the wiring area; and a second insulating layer formed on the wiring area. Therefore, a contact surface between the carrier and the first and second insulating layers is reduced by reducing the areas of the first and second insulating layers, whereby a substrate warpage due to mismatch of coefficients of thermal expansion (CTE) is avoided. The present invention further provides a method of manufacturing the substrate structure as described above.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: January 23, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-An Chang, Sung-Huan Sun, Chien-Hung Wu, Yi-Cheih Chen, Wen-Kai Liao
  • Patent number: 9859227
    Abstract: An integrated circuit structure and formation thereof. The integrated circuit structure includes a substrate and a front-end-of-the-line (FEOL) portion. The FEOL portion rests on top of and in contact with the substrate. The integrated circuit structure includes a memory level portion. The memory level portion rests on top of and in contact with the FEOL portion. The integrated circuit structure includes a back-end-of-the-line (BEOL) portion. The BEOL portion rests on top of and in contact with the memory level portion. The integrated circuit structure includes a multiple layer that includes one or more pairs of reactive materials. The multiple layer is one or more of: i) on top of the BEOL portion; ii) within the BEOL portion; iii) within the memory level portion; iv) within the FEOL portion; v) embedded in the substrate; and vi) on bottom of a thinned substrate.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kenneth P. Rodbell
  • Patent number: 9831210
    Abstract: An electronic device includes an electrode including Cu, a solder including Sn and provided above the electrode, and a joining layer including In and Ag and provided along a boundary between the electrode and the solder. The joining layer including In and Ag prevents Cu—Sn alloy, such as Cu6Sn5, from being formed at the boundary between the electrode and the solder, and prevents generation of voids and cracks resulting from the Cu—Sn alloy. The electrode and the solder are joined with sufficient strength by the joining layer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Taiki Uemura, Seiki Sakuyama
  • Patent number: 9796828
    Abstract: An epoxy resin composition, comprising an epoxy resin, a curing agent, a curing accelerator, an inorganic filler, and a carboxylic acid compound that satisfies at least one selected from the group consisting of the following A, B and C below: A: having at least one carboxy group and at least one hydroxy group; B: having at least two carboxy groups; and C: having a structure in which two carboxy groups are condensed by dehydration.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: October 24, 2017
    Assignee: HITACHI CHEMICAL COMPANY, LTD
    Inventors: Yuta Ono, Mitsuaki Fusumada, Hironori Kobayashi, Yuya Kitagawa, Teruyoshi Hasegawa
  • Patent number: 9704824
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.
    Type: Grant
    Filed: November 2, 2013
    Date of Patent: July 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim, Byung Joon Han
  • Patent number: 9659894
    Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, and buffer layers having a Young's Modulus of 2.5 GPa or less.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 23, 2017
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventor: Simon Jonathan Stacey
  • Patent number: 9640466
    Abstract: A method of manufacturing a packaged semiconductor device includes patterning and plating silver nanoparticles in bonding areas of a lead frame, forming a hydrophilic group while oxidizing the silver nanoparticles, forming wire bonds on the silver nanoparticles, and encapsulating the wire bonds and the silver nanoparticles.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 2, 2017
    Assignee: NXP USA, Inc.
    Inventors: Varughese Mathew, Sheila Chopin
  • Patent number: 9576873
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: February 21, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9548280
    Abstract: A solder ball pad for mounting a solder ball of a semiconductor device for preventing delamination of an overlying dielectric layer, and particularly devices and methods providing improved solder ball pad structures in a device such as a semiconductor device package.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: January 17, 2017
    Assignee: NXP USA, INC.
    Inventors: Vijay Sarihan, Zhiwei Gong, Scott M. Hayes
  • Patent number: 9545013
    Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 10, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9401308
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu
  • Patent number: 9373578
    Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 21, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: DaeSik Choi, OhHan Kim, SungWon Cho
  • Patent number: 9369066
    Abstract: The present invention concerns a MEMS device comprising an under bump metallization (4)—UBM—to contact the device via flip-chip bonding with a substrate. The UBM (4) is placed on the surface of the MEMS device and close to the corners of the surface. Further, the shape of the UBM (4) is adapted to the shape of the corners.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: June 14, 2016
    Assignee: EPCOS AG
    Inventors: Leif Steen Johansen, Jan Tue Ravnkilde
  • Patent number: 9362134
    Abstract: A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of the wafer is aligned with and communicated with the second opening of the protection layer. A first insulating layer having a first thickness is formed on a conductive pad exposed from the second opening, and a second insulating layer having a second thickness is formed on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening. The first and second insulating layers are etched, such that the first insulating layer is completely removed, and the second thickness of the second insulating layer is reduced.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: June 7, 2016
    Assignee: XINTEC INC.
    Inventor: Chia-Sheng Lin
  • Patent number: 9324630
    Abstract: A cooling fin 9 is joined to a semiconductor element 1. A resin 10 encapsulates the semiconductor element 1. A portion of the cooling fin 9 projects from a lower surface of the resin 10. A cooler 11 has an opening 12. The cooling fin 9 projecting from the resin 10 is inserted in the opening 12 of the cooler 11. The lower surface of the resin 10 and the cooler 11 are joined to each other by a joining material 13 such as an adhesive. Therefore, a reduction in the number of component parts and a reduction in weight can be achieved, and compatibility between the heat conductivity and the strength of joining can be ensured.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 26, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Noboru Miyamoto, Masao Kikuchi
  • Patent number: 9326372
    Abstract: A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of solder, penetrating through one of the through-holes, and projecting from both ends of the one of the through-holes, so that the first-electrodes are aligned with the through-holes in a plan view; a second-process for melting the relay-members so that the relay-members are connected to the first-electrodes, after the first-process; and a third-process for placing a semiconductor substrate on which a second-electrodes corresponding to the first-electrodes are formed on a side opposite to the first-substrate across the second-substrate, after the second-process, to connect the first-electrodes and the second-electrodes to each other via the relay-m
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: April 26, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Mamoru Kurashina, Daisuke Mizutani
  • Patent number: 9312206
    Abstract: A semiconductor package includes a semiconductor die having an active face and dielectric layers disposed on the active face of the semiconductor die. At least one opening is formed through the dielectric layers and extends from a non-bond pad area of the active face to an exterior surface of the dielectric layers. An electrically conductive layer is formed in the opening and is in physical contact with the active face of the semiconductor die. A thermally conductive material fills the opening to form a thermal via for dissipating heat away from the semiconductor die.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 12, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Weng F. Yap, Scott M. Hayes
  • Patent number: 9281286
    Abstract: Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: March 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Weng F. Yap, Alan J. Magnus
  • Patent number: 9257333
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Hsuan-Ting Kuo, Tsung-Yuan Yu, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9252049
    Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Tsung-Min Huang, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 9209121
    Abstract: Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: December 8, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Thomas M. Goida, Xiaojie Xue
  • Patent number: 9196754
    Abstract: A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: November 24, 2015
    Assignee: XINTEC INC.
    Inventor: Chia-Sheng Lin
  • Patent number: 9184144
    Abstract: Pillars having a directed compliance geometry are arranged to couple a semiconductor die to a substrate. The direction of maximum compliance of each pillar may be aligned with the direction of maximum stress caused by unequal thermal expansion and contraction of the semiconductor die and substrate. Pillars may be designed and constructed with various shapes having particular compliance characteristics and particular directions of maximum compliance. The shape and orientation of the pillars may be selected as a function of their location on a die to accommodate the direction and magnitude of stress at their location. A method includes fabricating pillars with particular shapes by patterning to increase surface of materials upon which the pillar is plated or deposited.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: November 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongping Bao, James D. Burrell, Shiqun Gu
  • Patent number: 9177931
    Abstract: Embodiments of the present invention provide a semiconductor structure and method to reduce thermal energy transfer during chip-join processing. In certain embodiments, the semiconductor structure comprises a thermal insulating element formed under a first conductor. The semiconductor structure also comprises a solder bump formed over the first conductor. The semiconductor structure further comprises a second conductor formed on a side of the thermal insulating element and in electrical communication with the first conductor and a third conductor. The third conductor is formed to be in thermal or electrical communication with the thermal insulating element. The thermal insulating element includes thermal insulating material and the thermal insulating element is structured to reduce thermal energy transfer during a chip-join process from the solder bump to a metal level included in the semiconductor structure.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Stephen P. Ayotte, Sebastien Quesnel, Glen E. Richard, Timothy D. Sullivan, Timothy M. Sullivan
  • Patent number: 9171802
    Abstract: A semiconductor device includes a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate includes, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: October 27, 2015
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akira Nakayama
  • Patent number: 9123704
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: September 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yo Sasaki, Yuuji Hisazato, Kazuya Kodani, Atsushi Yamamoto, Hitoshi Matsumura
  • Patent number: 9117801
    Abstract: A method for manufacturing semiconductor devices includes providing a stack having a semiconductor wafer and a glass substrate with openings and at least one trench attached to the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor devices. The openings of the glass substrate leave respective areas of the semiconductor devices uncovered by the glass substrate and the trench connects the openings. A metal layer is formed at least on exposed walls of the trench and the openings and on the uncovered areas of the semiconductor devices of the semiconductor wafer. A metal region is formed by electroplating metal in the openings and the trench and by subsequently grinding the glass substrate to remove the trenches. The stack of the semiconductor wafer and the attached glass substrate is cut to separate the semiconductor devices.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: August 25, 2015
    Assignee: Infineon Technologies AG
    Inventors: Carsten von Koblinski, Ulrike Fastner, Peter Zorn, Markus Ottowitz
  • Patent number: 9117939
    Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: August 25, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Bo-I Lee, Chien-Hsun Lee
  • Patent number: 9091421
    Abstract: The present invention provides an LED array module having an improved heat-dissipating effect, and a manufacturing method thereof. To this end, an LED array module includes one or more LED unit modules, the LED unit module comprising: an LED; a heat conductive heat-dissipating slug attached to the lower portion of the LED; and leads connected to the cathode and anode of the LED, respectively, wherein the LED array module comprises: a heat-dissipating plate; a heat conductive solder layer disposed and bonded between the upper surface of the heat-dissipating plate and the lower surface of the heat-dissipating slug; a first insulating layer formed on the upper surface of the heat-dissipating plate; and array electrodes which are formed on the upper surface of the insulating layer and are electrically connected to the leads to drive the LED.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: July 28, 2015
    Assignee: Korea Institute of Ceramic Eng. & Tech.
    Inventors: Hyo Tae Kim, Gi Seok Song, Heung Soon Kim
  • Patent number: 9082765
    Abstract: An integrated circuit structure includes a package component, which includes a dielectric layer and a metal trace over and in contact with the dielectric layer. The dielectric layer includes a first dielectric material and a second dielectric material in the first dielectric material. The first dielectric material is a flowable and curable material. The second dielectric material comprises a functional group selected from the group consisting essentially of (—C—N—), (—C—O—), (—N—C?O), and combinations thereof.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jiun Yi Wu
  • Patent number: 9066433
    Abstract: A power module substrate includes an insulating substrate, and a circuit layer that is formed on one surface of the insulating substrate. The circuit layer is formed by bonding a first copper plate onto one surface of the insulating substrate. Prior to bonding, the first copper plate has a composition containing at least either a total of 1 to 100 mol ppm of one or more kinds among an alkaline-earth element, a transition metal element, and a rare-earth element, or 100 to 1000 mol ppm of boron, the remainder being copper and unavoidable impurities.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: June 23, 2015
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Yoshirou Kuromitsu, Yoshiyuki Nagatomo, Nobuyuki Terasaki, Toshio Sakamoto, Kazunari Maki, Hiroyuki Mori, Isao Arai
  • Publication number: 20150145131
    Abstract: A package substrate includes a core layer having a first surface and a second surface which are opposite to each other, a ball land pad disposed on the first surface of the core layer, an opening that penetrates the core layer to expose the ball land pad, and a dummy ball land disposed on the second surface of the core layer to surround the opening. The dummy ball land includes at least one sub-pattern and at least one vent hole. Related semiconductor packages and related methods are also provided.
    Type: Application
    Filed: April 25, 2014
    Publication date: May 28, 2015
    Applicant: SK hynix Inc.
    Inventors: Jong Woo YOO, Qwan Ho CHUNG
  • Publication number: 20150145109
    Abstract: A semiconductor package includes a housing having a bottom surface and an upper surface and a solder pad arranged in the bottom surface of the housing. The solder pad includes a solderable through hole. The housing includes an opening extending from the through hole to the upper surface of the housing.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Inventor: Thomas Bemmerl
  • Patent number: 9041224
    Abstract: A method for producing a solder joint between at least one base part (2) and at least one first component (3) includes the following steps: providing the base part (2); partially blasting a surface of the base part (2) using a SACO blasting agent, the blasting material (50) of which has a silicate coating (52), in such a way that a SACO-blasted region (20) and a non-blasted positioning region (40) are present; and soldering the at least first component (3) onto the non-blasted positioning region (40), wherein the SACO-blasted region (20) acts as a solder resist.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Daniel Michels, Simon Green
  • Patent number: 9041223
    Abstract: A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuh Chern Shieh, Han-Ping Pu, Yu-Feng Chen, Tin-Hao Kuo
  • Patent number: 9035465
    Abstract: Various embodiments include semiconductor structures. In one embodiment, the semiconductor structure includes a chip having a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Timothy J. Dalton, Mukta G. Farooq, John A. Fitzsimmons, Louis L. Hsu
  • Publication number: 20150130084
    Abstract: A fan-out package structure including a heat radiating side edge that includes a semiconductor substrate; a bond pad located on the semiconductor substrate; and a redistribution layer connected with the bond pad and located on the semiconductor substrate, wherein an end of the redistribution layer extends to a sidewall of the semiconductor substrate, and the end is coplanar with the sidewall.
    Type: Application
    Filed: April 7, 2014
    Publication date: May 14, 2015
    Applicant: CHIPMOS TECHNOLOGIES INC
    Inventor: TSUNG JEN LIAO
  • Patent number: 9030028
    Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallization layer is formed on the second surface of the semiconductor substrate. The metallization layer has a thickness which is greater than the device thickness.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Rudolf Zelsacher, Paul Ganitzer
  • Publication number: 20150123276
    Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: Yi-Wen Wu, Ming-Che Ho, Wen-Hsiung Lu, Chia-Wei Tu, Chung-Shi Liu