Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. In the semiconductor device, silver arranged on a semiconductor element and silver arranged on a base are bonded. No void is present or a small void, if any, is present at an interface between the semiconductor element and the silver arranged on the semiconductor element, no void is present or a small void, if any, is present at an interface between the base and the silver arranged on the base, and one or more silver abnormal growth grains and one or more voids are present in a bonded interface between the silver arranged on the semiconductor element and the silver arranged on the base.

Abstract: A semiconductor device includes a semiconductor element on which electrode pads are laid out. A wiring substrate includes connecting pads respectively arranged in correspondence with the electrode pads. Pillar-shaped electrode terminals are respectively formed on the electrode pads of the semiconductor element. A solder joint electrically connects a distal portion of each electrode terminal and the corresponding connecting pad on the wiring substrate. Each electrode terminal includes a basal portion, which is connected to the corresponding electrode pad, and a guide, which is formed in the distal portion. The guide has a smaller cross-sectional area than the basal portion as viewed from above. The guide has a circumference and the basal portion has a circumference that is partially flush with the circumference of the guide. The guide is formed to guide solder toward the circumference of the guide.

Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die.

Abstract: Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

Abstract: Provided are a stacked package, a method of fabricating a stacked package, and a method of mounting the stacked package fabricated by the same.

Abstract: In a method for producing an electronic component device, a heat bonding step is performed in a state in which low melting point metal layers including low melting point metals including, for example, Sn as the main component, are arranged to sandwich, in the thickness direction, a high melting point metal layer including a high melting point metal including, for example, Cu as the main component, which is the same or substantially the same as high melting point metals defining first and second conductor films to be bonded. In order to generate an intermetallic compound of the high melting point metal and the low melting point metal, the distance in which the high melting point metal is to be diffused in each of the low melting point metal layers is reduced. Thus, the time required for the diffusion is reduced, and the time required for the bonding is reduced.

Abstract: Sub-micron precision alignment between two microelectronic components can be achieved by applying energy to incite an exothermic reaction in alternating thin film reactive layers between the two microelectronic components. Such a reaction rapidly distributes localized heat to melt a solder layer and form a joint without significant shifting of components.

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract: The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of the cell arrangement, the arrangement of pads, bumps or the like may be adjusted.

Abstract: Provided is a substrate structure including: a base substrate on which a conductive pattern is formed; a first plating layer covering the conductive pattern; and a second plating layer covering the first plating layer, wherein the first plating layer includes an electroless reduction plating layer.

Abstract: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.

Abstract: An interconnect structure comprises a solder including nickel (Ni) in a range of 0.01 to 0.20 percent by weight. The interconnect structure further includes an intermetallic compound (IMC) layer in contact with the solder. The IMC layer comprises a compound of copper and nickel.

Abstract: A semiconductor device including a first wafer assembly having a first substrate and a first oxide layer over the first substrate. The semiconductor device further includes a second wafer assembly having a second substrate and a second oxide layer over the second substrate. The first oxide layer and the second oxide layer are bonded together by van der Waals bonds or covalent bonds. A method of bonding a first wafer assembly and a second wafer assembly including forming a first oxide layer over a first substrate. The method further includes forming a second oxide layer over a second wafer assembly. The method further includes forming van der Waals bonds or covalent bonds between the first oxide layer and the second oxide layer.

Abstract: An embedded chip package is provided. The embedded chip package includes a plurality of chips; encapsulation material embedding the plurality of chips; at least one electrical redistribution layer electrically connected to the plurality of chips; and a common terminal connected to the at least one electrical redistribution layer, wherein the common terminal provides an interface to at least one of transmit and receive a common electrical signal between the plurality of chips and the common terminal.

Abstract: Provided are a dual-phase intermetallic interconnection structure and a fabricating method thereof. The dual-phase intermetallic interconnection structure includes a first intermetallic compound, a second intermetallic compound, a first solder layer, and a second solder layer. The second intermetallic compound covers and surrounds the first intermetallic compound. The first intermetallic compound and the second intermetallic compound contain different high-melting point metal. The first solder layer and the second solder layer are disposed at the opposite sides of the second intermetallic compound, respectively. The first intermetallic compound is adapted to fill the micropore defects generated during the formation of the second intermetallic compound.

Abstract: A diode arrangement includes a diode and two electrodes. Each electrode is connected to the diode in an electrically conductive manner via a soldered connection on one of two oppositely arranged contact surfaces of the diode. The contact surfaces of the diode are formed substantially by the surfaces of a lower side and an upper side of the diode and are contacted with the contact extensions of the electrodes via the soldered connection. The contact extensions forming counter contact surfaces are substantially congruent with the contact surfaces of the diode.

Abstract: An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips.

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract: According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Abstract: A method for making a liquid barrier includes forming a liquid barrier layer on a substrate, forming a mask layer on the liquid barrier layer such that part of the liquid barrier remains exposed, forming a contact layer on the exposed liquid barrier layer, and removing the mask layer to expose the part of the liquid barrier layer which was covered by the mask layer. A liquid wetting boundary is formed when the wettability on the liquid barrier surface area is less than the wettability of the contact surface area.

Abstract: A chip package includes a PCB, a connecting pad fixed on a surface of the PCB and a chip fixed on the connecting pad. The connecting pad includes a first metal film on its surface facing away from the PCB. The chip includes a second metal film formed on its surface opposite to the PCB. The first and the second metal are connected to each other via a eutectic manner.

Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom side and a lead top side; applying a passivation over the lead with the lead top side exposed from the passivation; forming an interconnect structure directly on the passivation and the lead top side, the interconnect structure having an inner pad and an outer pad with a recess above the lead top side; mounting an integrated circuit over the inner pad and the passivation; and molding an encapsulation over the integrated circuit.

Abstract: A pad (15) is provided on a surface connecting a first substrate (11) of a lower layer module with an upper layer module, the pad is partially covered by an insulating film (20) to form an opening section (3) exposing the pad (15), a first connection terminal (2) is formed on the lower surface of the first substrate (11) of the lower layer module, the planar shape of the opening section (3) is different from the planar shape of the first connection terminal (2), the outer shape of the opening section (3) is larger than the first connection terminal (2), and in a transmissive inspection from above, the shape of the lower end of a second connection terminal (30) spreading in the opening section (3) is not concealed by the other terminal. This configuration enables easy and reliable determination of whether bonding sections are satisfactory by a non-destructive inspection.

Abstract: A tin (Sn)-based solder ball and a semiconductor package including the same are provided. The tin-based solder ball includes about 0.2 to 4 wt. % silver (Ag), about 0.1 to 1 wt. % copper (Cu), about 0.001 to 0.3 wt. % aluminum (Al), about 0.001% to 0.1 wt. % germanium (Ge), and balance of tin and unavoidable impurities. The tin-based solder ball has a high oxidation resistance.

Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.

Abstract: A package substrate has a die mounted on a first side. One or more inner solder pads are on an inner portion of a second side. A perimeter of the inner portion is aligned with a perimeter of the die. The one or more inner solder pads are the only solder pads on the inner portion. The one or more inner solder pads number no more than five. A plurality of outer solder pads are on an outer portion of the second side. An average of areas of the one or more inner solder pads is at least five times an average of areas of the one or more inner solder pads. The plurality of outer solder ball pads are for receiving solder ball balls. The outer portion is spaced from the perimeter of the inner portion. The outer portion and the inner portion are coplanar.

Abstract: A method of forming an integrated circuit (IC) package is disclosed comprising: (a) removing oxides from side surfaces of terminals of the IC package; (b) substantially covering an underside of the terminals of the IC package; and (c) forming a solder coating on the side surfaces of terminals of the IC packages while covering the underside of the terminals of the IC package. The solder coating on the side surfaces of the terminals protects the terminals from oxidation due to aging and subsequent processes. Additionally, the solder coating on the side surfaces of the terminals substantially improves the solderability of the IC package to printed circuit boards (PCBs) or other mountings. This further facilitates the inspection of the solder attachment using less expensive and complicated methods.

Abstract: A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.

Abstract: A light emitting diode chip a support layer having a first face and a second face opposite the first face, a diode region on the first face of the support layer, and a bond pad on the second face of the support layer. The bond pad includes a gold-tin structure having a weight percentage of tin of 50% or more. The light emitting diode chip may include a plurality of active regions that are connected in electrical series on the light emitting diode chip.

Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).

Abstract: A manufacturing method of a bump structure is provided. A substrate having at least one pad and a passivation layer is provided. The passivation layer has at least one first opening exposing the pad. An insulating layer is formed on the passivation layer. The insulating layer has at least one second opening located above the first opening. A metal layer is formed on the insulating layer. The metal layer electrically connects the pad through the first and second openings. A first bump is formed in the first and second openings. A second bump is formed on the first bump and a portion of the metal layer. The metal layer not covered by the second bump is partially removed by using the second bump as a mask, so as to form at least one UBM layer. The first bump is completely covered by the UBM layer and the second bump.

Abstract: A semiconductor device of the present invention includes a supporting board, an electrode surface processing layer formed on the supporting board, a semiconductor element, and a solder material containing a first metal composed mainly of bismuth and a second metal having a higher melting point than the first metal and joining the electrode surface processing layer and the semiconductor element, the first metal containing particles of the second metal inside the first metal. The composition ratio of the second metal is higher than the first metal in a region of the solder material corresponding to the center portion of the semiconductor element, and the composition ratio of the second metal is at least 83.8 atomic percent in the region corresponding to the center portion.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die.

Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.

Abstract: The present invention provides a circuit board including a substrate, at least one lead, at least one bump, and a solder layer. The lead is disposed on the substrate, and the bump is disposed on the lead. The solder layer covers the lead and the bump.

Abstract: A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity ?1 and a thixotropy index T1 at a position on the substrate, which is on an outer side of the mounted semiconductor package component; applying, on the first adhesive, a second adhesive with viscosity ?2 and a thixotropy index T2 so that the second adhesive gets in contact with an outer periphery part of the semiconductor package component; and forming, through a subsequent reflow process, a first adhesive part of the hardened first adhesive and a second adhesive part of the hardened second adhesive, wherein the first and second adhesives satisfy 30??2??1?300 (Pa·s) and 3?T2?T1?7, and sectional area S1 of the first adhesive part and sectional area S2 of the second adhesive part with respect to a direction perpendicular to a mounting surface of the substrate satisfy a relation S1?S2.

Abstract: A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract: A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the semiconductor chip; a stress relaxation layer formed on the semiconductor chip and having an opening for exposing the internal pad; an under-bump layer formed so as to cover a face exposed in the opening on the internal pad, an inner face of the opening and a circumference of the opening on the stress relaxation layer; a solder terminal for electrical connection with outside formed on the under-bump layer; and a protective layer formed on the stress relaxation layer, encompassing a periphery of the under-bump layer and covering a side face of the under-bump layer.

Abstract: A semiconductor wafer, substrate, and bonding structure is disclosed that includes a device wafer that includes, for example, a plurality of light emitting diodes, a contact metal layer (or layers) on one side of the device wafer opposite the light emitting diodes, and a bonding metal system on the contact metal layer that predominates by weight in nickel and tin.

Abstract: A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 ?m to 200 ?m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.

Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

Abstract: A semiconductor device includes a semiconductor die. The semiconductor die includes a first bond pad having a plurality of connection points, the first bond pad arranged on a first portion of the semiconductor die, wherein the first portion corresponds to an outer periphery of the semiconductor die, and a second bond pad and a third bond pad arranged within a second portion of the semiconductor die, wherein the second portion is within the outer periphery of the semiconductor die. A lead external to the semiconductor die is configured to provide a voltage potential to the semiconductor die. A first lead wire is connected between the lead and a first connection point. A second lead wire is connected between the second bond pad and a second connection point. A third lead wire is connected between the third bond pad and a third connection point.

Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.

Abstract: In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.

Abstract: Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.