Abstract: Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over another. Conductive pathways that extend around at least one side of at least one of the semiconductor devices provide electrical communication between conductive elements of the semiconductor devices, and optionally, a substrate. The conductive pathways may include self-supporting conductive leads or conductive traces carried by a substrate. Methods for forming semiconductor device assemblies having more than one semiconductor device include bending or wrapping at least one conductive pathway around a side of at least one semiconductor device and providing electrical communication between semiconductor devices of the assembly through the conductive pathways.

Abstract: One inventive aspect is related to a method of bonding two elements and micro-electronic devices produced according to such methods. In one aspect, a micro-electronic device includes a first and a second element, bonded together by a joining structure. The joining structure has a first micropattern portion, a second micropattern portion, and a joining portion in between the first and second micropattern portions. The first and second micropattern portions are made of cobalt. The joining portion includes intermetallic compounds of cobalt and tin (Sn).

Abstract: A mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb), the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element and the wiring board and then cooling the connected semiconductor element and wiring board at a cooling rate equal to and lower than 0.5° C./s.

Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: To provide a low-cost, easy-to-use, and efficient method for manufacturing a semiconductor device, which eliminates the need for the formation or removal of barrier metals upon formation of bumps, and a high-performance semiconductor device with fine bumps arranged at a narrow pitch. The method includes: forming a plurality of electrode pads 12 on one surface of a semiconductor substrate 10; forming insulating layers (e.g., inorganic insulating layer 14 and organic insulating layer 16) to cover the perimeter of each electrode pad 12; selectively forming a mask layer 20 on the insulating layers 14 and 16; cleaning the surface of the electrode pads 12 which is not covered with the insulating layers 14 and 16; forming external terminals 46 in regions defined by the insulating layers 14 and 16 and mask layer 20 so that they are in contact with the electrode pads 12; and removing the mask layer 20.

Abstract: A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers.

Abstract: A bonding pad structure in a semiconductor device includes a contact pad connected to an interconnect, a bonding pad overlying the contact pad with an intervention of an insulating film and exposed from an opening of a passivation film, and an annular contact disposed between the contact pad and the bonding pad for electric connection therebetween. The annular contact encircles the opening as viewed normal to the substrate surface.

Abstract: A semiconductor package includes a semiconductor chip having a first region and a second region. Bonding pads are formed and through-holes are defined in the first and second regions. Insulation layers are formed on sidewalls of the through-holes, and through-electrodes formed in the through-holes and connected with corresponding bonding pads. The insulation layers formed in the first and second regions have different thicknesses or dielectric constants.

Abstract: A stack of semiconductor dies is disclosed. A first stack level includes a first semiconductor die and at least one first support that are attached to a substrate surface. A second level includes a second semiconductor die and at least one second support that are attached to the active surface of the first semiconductor die and to a coplanar surface of the first support(s). A third level includes a third semiconductor die attached to the active surface of the second semiconductor die and to a coplanar surface of the second support(s). The second and third semiconductor dies do not overlap bond pads of the first and second semiconductor dies, respectively. An adhesive film overlies the entire inactive surface of the second and third semiconductor dies, and attaches the second and third semiconductor dies to the immediately underlying active surface and support(s).

Abstract: Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.

Abstract: A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process coats the component surfaces to facilitate the bonding of the bond pads. In another aspect, the present process coats the bond pads with shelled capsules to facilitate the bonding of the bond pads.

Abstract: A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land.

Abstract: A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip 221 with contact studs 223 is attached onto the traces 203 on tape 101. The traces, which are unprotected by soldermask 110, have solder on the top surface, but not on the sidewalls. The sidewalls of the traces are at right angles to the trace top, giving the trace a rectangular cross section. Consequently, the area for attaching stud 223 is maximized. At the same time, the differential plating method of trace metal 203 and through-hole metal 206 allows different metal thicknesses and provides independent control of the trace aspect ratio for low electrical resistance and trace fatigue.

Abstract: A semiconductor device has a semiconductor die with a solder bump formed on its surface. A contact pad is formed on a substrate. A signal trace is formed on the substrate. The pitch between the contact pad and signal trace is less than 150 micrometers. An electroless surface treatment is formed over the contact pad. The electroless surface treatment can include tin, ENIG, or OSP. A film layer is formed over the contact pad with an opening over the signal trace. An oxide layer is formed over the signal trace. The film layer and surface treatment prevent formation of the oxide layer over the contact pad. The film layer is removed. The solder bump is reflowed to metallurgically and electrically bond to the contact pad. In the event that the solder bump physically contacts the oxide layer, the oxide layer maintains electrical isolation between the solder bump and signal trace.

Abstract: Provided is a semiconductor apparatus that reduces on-resistance in wiring between a first electrode terminal and a second electrode terminal. The semiconductor apparatus includes the first electrode terminal, the second electrode terminal, and at least two wires that connect the first and second electrode terminals. At least two wires are electrically connected with each other by using a conductive adhesive in an extending direction of the wires. The first electrode terminal is a terminal of an external lead electrode, for example. The second electrode terminal is a terminal of a source electrode of a MOSFET, for example.

Abstract: A semiconductor device is provided that includes a semiconductor chip, a plurality of solder bumps that electrically couple the semiconductor chip to the outside, and a metal bump being provided on the surface of each first solder bump which is at least a part of the plurality of solder bumps and being made of a metal having a melting point higher than that of the first solder bump. The wettability of the first solder bump is improved as each metal bump serves as a core when the corresponding first solder bump melts. Thus, the connection reliability of the first solder bump can be improved.

Abstract: An LGA substrate includes a core (110), having build-up dielectric material (150), at least one metal layer (125), and solder resist (155) formed thereon, an electrically conductive land grid array pad (120) electrically connected to the metal layer, a nickel layer (121) on the electrically conductive land grid array pad, a palladium layer (122) on the nickel layer, and a gold layer (123) on the palladium layer.

Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).

Abstract: A light emitting chip is disposed on a support surface. A plurality of bonding bumps are disposed in a gap between the light emitting chip and the support surface. The plurality of bonding bumps provide at least one electrical power input path to the light emitting chip. An underfill comprising underfill material is disposed in the gap between the light emitting chip and the support surface such that the underfill substantially fills the gap but does not form a fillet extending outside the gap over sidewalls of the light emitting chip. The underfill is configured to provide at least one of (i) mechanical support for the light emitting chip and (ii) a thermal conduction path from the light emitting chip to the support surface.

Abstract: A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.

Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.

Abstract: A mounting substrate for mounting a semiconductor chip in a flip chip manner, having a plurality of connection pads to which the semiconductor chip is connected, an insulating pattern formed so as to cover a part of the connection pads, and a plurality of dummy patterns for controlling a flow of an underfill infiltrated below the semiconductor chip, characterized in that the plurality of dummy patterns are arranged in staggered lattice shape.

Abstract: An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and the barrier layer may include nickel and/or copper. Moreover, portions of the under bump seed metallurgy layer may be undercut relative to portions of the barrier layer. In addition, a solder layer may be provided on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.

Abstract: An integrated circuit/substrate interconnect apparatus and method of manufacture are provided. Included is a substrate with a plurality of wells and a landing pad formed in each of the wells. The substrate further includes a seed layer deposited in each of the wells over the landing pad, and a metalized layer deposited in each of the wells over the seed layer. Before assembly, an upper surface of the metalized layer forms a well.

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Abstract: A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to the first row and consist of a second group of four die pads running in the first direction. The second row begins at a first offset in the first direction from where the first row begins. A third row of die pads are adjacent to the second row and comprise a third group of four die pads that run in the first direction. The third row begins at a second offset in the first direction from where the second row begins. This allows for relatively easy access to all of the die pads.

Abstract: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.

Abstract: An electronic device comprises a device substrate, a plurality of compliant electrically-conductive balls, and a plurality of solder joints that couple the compliant electrically-conductive balls to the device substrate by a reflow process.

Abstract: Disclosed are semiconductor die packages having overlapping dice, systems that use such packages, and methods of making such packages. An exemplary die package comprises a leadframe, a first semiconductor die, and a second semiconductor die that has a recessed portion in one of its surfaces. The first die is disposed over a first portion of the leadframe, and the second die is disposed over a second portion of the leadframe with its recess portion overlying at least a portion of the first die. Another exemplary die package comprises a leadframe with a recessed area, a first semiconductor die disposed in the recessed area, and a second semiconductor die overlying at least a portion of the first die. Preferably, electrically conductive regions of both dice are electrically coupled to a conductive region of the leadframe to provide an interconnection between dice that has very low parasitic capacitance and inductance.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a leadframe, a die, a solder layer and several connecting components. The leadframe includes a heat dissipation pad and several leads. The heat dissipation pad is disposed in a substantial center of the leadframe. The leads are surrounding the heat dissipation pad. The die having an active surface is disposed on the leadframe. The solder layer is disposed between the active surface and the heat dissipation pad. The connecting components are disposed between the active surface and the leads. The die is electrically connected to the leadframe through the solder layer and the connecting components.

Abstract: An integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate.

Abstract: A method for producing a matrix of electromagnetic radiation detectors made up of a plurality of elementary detection modules mounted on an interconnection substrate. The method includes depositing on the interconnection substrate a predefined number of quantities of solder or hybridization material, intended to constitute hybridization bumps for the elementary modules, in at least a first array for the nominal hybridization, and at least one second array, with the deposits of solder or hybridization material of the second array being lower in volume than those of the first array, depositing a liquid flux on the interconnection substrate, mounting the elementary modules to be hybridized on the interconnection substrate, and raising the temperature of a chamber in which the various elements to be hybridized are positioned until reaching at least the melting point of the solder or hybridization material to join the modules and interconnection substrate together by reflow effect.

Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.

Abstract: A chip module having a substrate and at least one chip connected to the substrate is provided, the substrate featuring a first main plane of extension and the chip featuring a second main plane of extension, and an acute angle being provided between the first main plane of extension and the second main plane of extension, and the substrate also comprising a mold housing.

Abstract: A circuit device of preferred embodiments of the present invention includes: a circuit element with electrodes formed in a peripheral part thereof; connecting portions connected to surfaces of the electrodes; and redistribution lines which are continuous to the respective connecting portions and extended in parallel to the main surface of the circuit element. In preferred embodiments of the present invention, the connecting portions and the redistribution lines are integrally formed of one piece of metal. Accordingly, there is no place where different materials are connected in a portion between the connecting portions and the redistribution lines, thus improving a joint reliability of the entire device against a thermal stress or the like.

Abstract: A method and product which provides a thin metal or ceramic plate to the top of a plastic grid array (PGA) as a stiffener to maintain its flatness over temperature during a column attach process, and the columns are used for attachment to circuit boards or other circuit devices. These may be constructed in this manner initially or may be retrofitted plastic ball grid arrays from which the solder balls are removed and, the stiffener is attached to the top, and the solder columns have been added to replace the solder balls. The stiffener is a bonded thin metal or ceramic plate attached to the top of the PGA to maintain its flatness over temperature during the column attach process. An aluminum plate bonded to the top of a PGA results in a significant reduction in warping during a temperature cycle. This allows attachment of solder columns to the PBGA. The high melt solder columns are attached to an area array pattern on the PBGA substrate. This array is typically either a solid or perimeter grid.

Abstract: A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.

Abstract: Semiconductor devices, as well as stacked structures, packages, modules, and electronic apparatus including the semiconductor device, and methods of fabricating the same. The semiconductor device includes a circuit layer on a substrate, a metal interconnection layer on the circuit layer, the metal interconnection layer having a copper interconnection and a protection layer, a first and a second through silicon via plugs vertically penetrating the circuit layer, a first via pad on the first through silicon via plug, and a second via pad on the second through silicon via plug, wherein the first via pad is electrically connected to the copper interconnection, and wherein the second via pad is electrically insulated from the copper interconnection.

Abstract: A solder preform according to the present invention has a variation in the size of high melting point metal particles which is at most 20 micrometers when the metal particle diameter is 50 micrometers, and an alloy layer of the high melting point metal particles and the main component of solder is formed around the high melting point metal particles. In addition, no voids at all are present in the solder. An electronic component according to the present invention has a semiconductor element bonded to a substrate with the above-described solder preform and has excellent resistance to heat cycles.

Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.

Abstract: A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

Abstract: A vacuum package has a chamber in which pressure is reduced to less than the atmospheric pressure, a functional component sealed in the chamber, and a material forming at least a part of the chamber. The material has at least one through hole to evacuate the chamber. In a cross section perpendicular to the material taken along the through hole, an edge portion of the material forming the through hole has an obtuse angle. The through hole is sealed with a sealing material.

Abstract: An electrically conductive pin comprising a pin stern and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head has an underside surface defining a continuous curve configured to allow gases to escape from a pin-attach solder region adjacent the underside surface.

Abstract: A board structure, a ball grid array (BGA) package and method thereof and a solder ball and method thereof. The example solder ball may include a solder portion and a grooved connection portion, formed through a partitioning process, configured to fit a corresponding protruding portion on a board. The example BGA package may include a plurality of the example solder balls. The example board structure may include the example BGA package connected to the board via the grooved connection portions and the protruding portions.

Abstract: A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.

Abstract: A monolithic substrate contains an integrated circuit comprising an amplifier having input and output, a mixer and a hybrid coupler for coupling the amplifier to the mixer. Metallic pads on the substrate are connected to each of two ports of the coupler and separate metallic pads are also connected to each of the input and output of the amplifier. The metallic pads allow the amplifier and mixer to be separately tested by a probe and the input or the output of the amplifier to be selectively connected to the mixer to enable the circuit to operate either as a receiver or transmitter. Alternatively, connections between the mixer and both input and output of the amplifier may be preformed and one of the connections subsequently severed depending on whether the circuit is to operate in receive or transmit mode.

Abstract: Consistent with the present disclosure, a package is provided in which the PLC substrate, for example, is bonded to the underyling carrier though a limited contact area. The rest of the substrate is detached from the carrier so that stresses are applied to a limited portion of the PLC substrate. The PLC itself, however, is provided over that portion of the substrate that is detached from the carrier, and thus experiences reduced stress. Accordingly, high modulus adhesives, as well as solders, may be used to bond the PLC substrate to the carrier, thereby resulting in a more robust mechanical structure.

Abstract: One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.