Abstract: The present invention relates to a semiconductor device in which electrodes formed on a semiconductor chip and electrodes formed on a wiring board are electrically connected via projecting elastic electrodes, and further relates to a mounting method of reducing a pressure applied to electrodes formed on a substrate or underlying wirings when a semiconductor chip and a wiring board are bonded.

Abstract: Provided is a semiconductor device including: a base plate; a thermally conductive resin layer formed on an upper surface of the base plate; an integrated layer which is formed on an upper surface of the thermally conductive resin layer, and includes an electrode and an insulating resin layer covering all side surfaces of the electrode; and a semiconductor element formed on an upper surface of the electrode, in which the integrated layer is thermocompression bonded to the base plate through the thermally conductive resin layer. This semiconductor device excels in insulating properties and reliability.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices are disclosed herein. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The microelectronic workpiece of this embodiment further includes a protective layer over the backside of the substrate. The protective layer is formed on the backside of the substrate from a material that is in a flowable state and is then cured to a non-flowable state.

Abstract: A package structure preventing solder overflow on substrate solder pads includes a plurality of die pins, a plurality of solders and a plurality of substrate solder pads. The die pins are located under a die. The substrate solder pads are formed on an upper surface of a substrate by copper plating or etching. Each of the substrate solder pads has at least one solder pad connection point. The solders connect the die pins with the corresponding solder pad connection points, respectively. Each of the solder pad connection points has a pair of solder pad ridges or a pair of solder pad grooves. The solder pad ridges and the solder pad grooves filled with the solder or a resin can prevent the solder overflow problem.

Abstract: A semiconductor device such as a COF or the like is provided on a semiconductor chip on a film-like shaped flexile wiring substrate on which a wiring pattern is formed. Between the semiconductor chip and the flexile wiring substrate, a sealing resin is filled for protecting the semiconductor chip. In the semiconductor device, a resin trace is 0.1 to 1.0 mm in width and 10 ?m in thickness, the resin trace being formed when applying the sealing resin along a longitudinal side of the semiconductor chip.

Abstract: A semiconductor device includes a chip. The chip includes a single circuit element formed in a semiconductor substrate, a first metal layer on a first face of the semiconductor substrate, and a second metal layer on a second face of the semiconductor substrate opposite the first face. The first metal layer and the second metal layer are configured for accessing the single circuit element. A smaller of a first width of the first face of the semiconductor substrate and a second width of the first face of the semiconductor substrate perpendicular to the first width is less than or equal to a distance between an exposed face of the first metal layer parallel to the first face of the semiconductor substrate and an exposed face of the second metal layer parallel to the second face of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor chip having a current path between a first principal surface and a second principal surface opposite from the first principal surface, a first conductive frame having an opposite region to the first principal surface, and a second conductive frame electrically connected via electrical connection member to a pad formed on the second principal surface. In a gap between the first principal surface and the first conductive frame, there are arranged multiple column-shaped lead-free solders which are arranged within a circle drawn around a center of the opposite region and having a diameter corresponding to a narrow side of the opposite region, and which electrically connects the first conductive frame with the semiconductor chip, and a filler which is filled between the multiple column-shaped lead-free solders.

Abstract: Pad structures and methods for forming such pad structures are provided. For the pad structure, the first conductive material layer has a first hardness over about 200 kg/mm2. The second conductive material layer is over the first conductive material layer and has a second hardness over about 80 kg/mm2. For the method of forming the pad structure, a plurality of first conductive material layers is formed within each of a plurality of openings of a substrate. The substrate has a plurality of openings therein. The first conductive material layers are formed within each of the openings of the substrate. The first conductive material layers substantially have a round top surface. The second conductive material layers are formed and substantially conformal over the first conductive material layers. The second conductive material layers cover a major portion of the round top surface of the first conductive material layers.

Abstract: An insulating layer 12 is formed as a surface layer of electronic circuit chip 10. A conductor interconnect 14 is formed in the insulating layer 12. The conductor interconnect 14 is exposed in the surface of the insulating layer 12. A solder wetting metallic film 16 (a metallic film) is formed on a portion of the conductor interconnect 14 to be exposed in the surface of the insulating layer 12. Typical metallic material (second metallic material) available for composing the solder wetting metallic film 16 includes a material that requires higher free energy for forming an oxide thereof, as compared with a free energy required for forming an oxide of the metallic material composing the conductor interconnect 14.

Abstract: A semiconductor apparatus includes a device, two metal-wiring layers, and an insulation film. The device includes first and second electrodes. The two metal-wiring layers include uppermost and next-uppermost metal-wiring layers. The insulation film is formed on the uppermost metal-wiring layer and includes first and second pad openings. The uppermost metal-wiring layer has a first portion exposed to air through the first pad opening and forming a first electrode pad, and the uppermost metal-wiring layer has a second portion exposed to air through the second pad opening and forming a second electrode pad. The first and second electrode pads are located over the device and are electrically connected to the first and second electrodes, respectively. The next-uppermost metal-wiring layer has a first portion located under the first electrode pad and electrically connected thereto, and a second portion located under the second electrode pad and electrically connected thereto.

Abstract: The present invention relates to methods and arrangements for forming a solder joint connection. One embodiment involves an improved solder ball. The solder ball includes a perforated, metallic shell with an internal opening. Solder material encases the shell and fills its internal opening. The solder ball may be applied to an electrical device, such as an integrated circuit die, to form a solder bump on the device. The solder bump in turn can be used to form an improved solder joint connection between the device and a suitable substrate, such as a printed circuit board. In some applications, a solder joint connection is formed without requiring the application of additional solder material to the surface of the substrate. The present invention also includes different solder bump arrangements and methods for using such arrangements to form solder joint connections between devices and substrates.

Abstract: A semiconductor interconnection comprises a semiconductor device, a substrate adjacent the semiconductor device, and a plurality of spring contacts on the semiconductor device or the substrate. A plurality of solder connections are on the opposite semiconductor device or substrate. Each spring contact comprises a contact surface and a conductive material on the contact surface. Upon assembly of the semiconductor device and the substrate, the conductive material on the plurality of spring contacts makes contact with each of the plurality of solder connections. The conductive material is in a liquid state at manufacturing or operating temperatures of the semiconductor device. Thus, the conductive material could be a solid at room temperature and transition to a liquid state at the semiconductor's manufacturing or operating temperatures.

Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.

Abstract: A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.

Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

Abstract: Integrated circuit bond pads are provided for forming wire bonds to integrated circuit package pins. Each pad uses a bond pad structure that provides room for under-pad circuitry. The under-pad circuitry can be connected to other circuitry on the integrated circuit, thereby providing efficient use of circuit real estate. The bond pad structures are formed in the dielectric stack portion of the integrated circuit using dummy bond pads and bond pad support structures. Bond pad support structures may be formed from metal in metal interconnect layers. Vias may be used to connect the bond pad support structures to each other and to the dummy bond pads. Bond pad support structures may be formed in a polysilicon layer at the bottom of the dielectric stack. A contact layer contains metal plugs that connect the polysilicon bond pad support structures to the lowermost metal-layer bond pad support structures.

Abstract: A packaged circuit element such as an LED and a method for making the same are disclosed. The packaged circuit element includes a lead frame, a molded body, and a die containing the circuit element. The lead frame has first and second leads, each lead having first and second portions. The molded body surrounds the first portion of each lead, and the die is connected electrically to the first and second leads on the first portions of the first and second leads. The second portion of each of the first and second leads is substantially parallel to opposing side surfaces of the body and include a feature that inhibits molten solder from wetting a portion of the second section of each lead between the feature and the first portion of that lead while allowing the molten solder to wet the remaining surfaces of the second portions.

Abstract: An improved apparatus for semiconductor wafer bumping utilizes the injection molded solder process and is designed for high volume manufacturing. The apparatus includes equipment for filling patterned mold cavities on a mold structure with solder, equipment for positioning and aligning a patterned surface of a semiconductor structure directly opposite to the solder filled patterned mold cavities of the mold structure, a fixture tool for holding and transferring the aligned mold and semiconductor structures together, and equipment for receiving the fixture tool and transferring the solder from the aligned patterned mold cavities to the aligned patterned semiconductor first surface. The solder transfer equipment include a wafer heater stack configured to heat the semiconductor structure and a mold heater stack configured to heat the mold structure to a process temperature slightly above the solder's melting point.

Abstract: A semiconductor package including a leadframe having first and second major surfaces and a mold lock opening extending between the first and second major surfaces. The semiconductor package includes a semiconductor die coupled to the first major surface, and an encapsulating material formed about the semiconductor chip and a portion of the first major surface of the leadframe and filling all but a portion of the mold lock opening, the unfilled portion of the mold lock opening forming a vent extending from the second major surface to the first major surface, the vent providing a pathway for air to escape from between the second major surface and a surface to which the second major surface is to be attached.

Abstract: Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.

Abstract: A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.

Abstract: A packaged semiconductor device (100) has a first (110) and a second (111) side, the second side including a plurality of metal terminals (120) extending to the first side. Each terminal includes an oblong groove (122) extending to the first side and ending in an orifice (123) at the first side. The terminals are made of a base metal and may have a solder-wettable surface except for the terminal surface (121) exposed at the first device side.

Abstract: In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.).

Abstract: A semiconductor device in accordance with the present invention includes IC chips (semiconductor elements) (2, 3, 4) having solder bumps (24) (projecting electrodes) formed on electrode pads, and a first wiring board (1) having connection terminals (7) to which the respective solder bumps (24) of the IC chips (2, 3, 4) are connected, external connection terminals (8) for connection to an external apparatus, and conductor wires (9) provided in respective groove portions formed in a board surface and connected to the respective connection terminals (7). In spite of the reduced pitch of the conductor wires (9), the presence of the groove portions enables an increase in cross section, allowing a reduction in wiring resistance.

Abstract: A method for forming a high thermal conductivity heat sink to IC package interface is disclosed. The method uses reactive getter materials added to a two phase solder system having a phase change temperature that is about the normal operating temperature range of the IC, to bind absorbed and dissolved oxygen in the two phase solder interface material at or near the air to solder surface. Over time this chemical binding action results in an oxide layer at the air to solder surface that slows the rate of oxygen absorption into the solder interface material, and thus reduces the harmful oxidation of the solder to IC package interface and the solder to heat sink interface.

Abstract: A method for mounting a semiconductor package onto PCB is disclosed. A semiconductor package is provided, which comprises a plurality of outer terminals exposed out of an encapsulant. A PCB is provided and has a surface with a plurality of contact pads. Each contact pad has a first exposed side, an opposing exposed second side and a center between the exposed sides. A plurality of first pre-solders and a plurality of second pre-solders are formed on the surface by one single printing. The first pre-solders and the second pre-solders respectively cover the first and second exposed sides of the contact pads, spaces between the opposing first and second pre-solders expose the centers of the contact pads. Then the first and second pre-solders are reflowed and the semiconductor package is mounted on the PCB.

Abstract: A bonding pad structure for an optoelectronic device. The bonding pad structure comprises a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same.

Abstract: A power semiconductor module and a method of manufacture thereof includes a lead frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract: This assembly of an object and a support is achieved by using solder bumps. At least two wettability areas are made respectively on an object and on a support. Each solder bump ensures electrical contact and mechanical fixing firstly to one of the wettability areas of object and secondly to one of the wettability areas of support. The melting temperature of solder bumps is lower than the melting temperature of each of the wettability areas. Each wettability area of the object forms an angle of 70° to 110° with respect to each wettability area of the support and the object and the support are mutually distant from one another.

Abstract: A pad for soldering a contact of a surface mounted component is provided herein. The pad includes a central portion and a plurality of separate extending portions extending from the central portion. All of the plurality of separate extending portions includes a free end and a connected end connected to the central portion. A width of the free end is larger than a width of the connected end. A circuit board and an electronic device are also provided.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including two or more semiconductor dies which are electrically connected to an underlying substrate through the use of conductive wires, some of which may be fully or partially encapsulated by an adhesive or insulating layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate are first and second semiconductor dies. The first semiconductor die and a portion of the substrate are covered by an adhesive layer. The second semiconductor die, the adhesive layer and a portion of the substrate are in turn covered by a package body of the semiconductor package.

Abstract: When a nickel (Ni) layer is formed on an electrode pad made of aluminum-silicon (Al—Si) by an electroless plating method, prior to the precipitation of zinc (Zn) which becomes a catalyst, copper (Cu) is formed in the form of discontinuous spots or islands on the surface of the electrode pad, thereby providing a copper (Cu) thin layer.

Abstract: A solder foil formed from a material comprising particles of Cu, etc. as metal particles and Sn particles as solder particles by rolling is suitable for solder bonding at a high temperature side in temperature-hierarchical bonding, and semiconductor devices and electronic devices produced by use of such solder bonding have distinguished reliability of mechanical characteristics, etc.

Abstract: An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Abstract: To prevent any uneven solder wetting in a main surface of electrodes of a semiconductor connected with a main surface of a planar lead and any displacement of the lead vis-a-vis the electrodes due to the reflow of the solder in a semiconductor module having the semiconductor element mounted on a substrate and the planar lead electrically connected therewith, the present invention provides an improved semiconductor module characterized in that the width of at least a part of the region of the main surface of the lead facing the semiconductor element is expanded wider than or equal to the width of the electrodes formed on the semiconductor element, and preferably the other part of the main surface of the lead soldered to an electrode formed on the substrate is split in the extending direction thereof.

Abstract: A semiconductor device has upper electrodes and external terminals which are protruding above the both surfaces of a substrate for semiconductor device and connected to each other by penetrating electrodes, a first insulating film covering at least a metal pattern except for the portions of the first insulating film corresponding to the upper electrodes, a second insulating film covering at least another metal pattern except for the portions of the second insulating film corresponding to the external terminals, and a semiconductor element connected to the upper electrodes and placed on the substrate for semiconductor device. The solder-connected surface of the external terminal is positioned to have a height larger than that of a surface of the second insulating film. The semiconductor element is placed on the first insulating film and covered, together with the upper electrodes, with a mold resin.

Abstract: A semiconductor device includes a semiconductor substrate, a lower wiring layer formed on the semiconductor substrate, a first interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second upper surface, the first upper surface being higher than the second upper surface relative to a surface of the semiconductor substrate, a contact plug formed in the interlayer insulating film and including a first bottom surface contacting to the lower wiring layer, a third upper surface flush with the second upper surface and a fourth upper surface flush with the first upper surface, an upper wiring layer formed on the first and third upper surfaces and including a first side surface and a second side surface opposite to the first side surface, and a second interlayer insulating film formed on the second and fourth upper surfaces.

Abstract: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed. Optionally coating on bump may be needed for certain chosen bump materials.

Abstract: A process for forming a solder bump on an under bump metal structure in the manufacture of a microelectronic device comprising exposing the under bump metal structure to an electrolytic bath comprising a source of Sn2+ ions, a source of Ag+ ions, a thiourea compound and/or a quaternary ammonium surfactant; and supplying an external source of electrons to the electrolytic bath to deposit a Sn—Ag alloy onto the under bump metal structure.

Abstract: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed.

Abstract: The present invention provides a conductive resin composition for connecting electrodes electrically, in which metal particles are dispersed in a flowing medium, wherein the flowing medium includes a first flowing medium that has relatively high wettability with the metal particles and a second flowing medium that has relatively low wettability with the metal particles, and the first flowing medium and the second flowing medium are dispersed in a state of being incompatible with each other. Thereby, a flip chip packaging method that can be applied to flip chip packaging of LSI and has high productivity and high reliability is provided.

Abstract: Provided is a power semiconductor module in which two components are bonded by a Bi based solder material. A Cu layer is provided on the surfaces thereof to be bonded by the Bi based solder material on the two-component. Two components, i.e., the components to be bonded, are a combination of a semiconductor element and an insulating part, or a combination of an insulating part and a radiator plate. The insulating part is composed of a Cu/SiNx/Cu laminated body.

Abstract: An electrical connection inside a semiconductor device is established by lead frames formed of plural conductor plates. The lead frames are disposed three-dimensionally so that the respective weld parts thereof are exposed toward a laser light source used in the laser welding. The laser welding is then performed by irradiating a laser beam. According to the above, welding can be performed readily in a reliable manner. The productivity of the semiconductor device and the manufacturing method of the semiconductor device can be thus enhanced. In addition, because the lead frames have the cooling effect, they have the capability of a heat spreader. It is thus possible to provide a semiconductor device and a manufacturing method of the semiconductor device with high productivity.

Abstract: A conductive bump structure of a circuit board and a method for forming the same are proposed. A conductive layer is formed on an insulating layer on the surface of the circuit board. A first resist layer is formed on the conductive layer and a plurality of first openings is formed in the first resist layer to expose the conductive layer. Then, a patterned trace layer is electroplated in the first openings and a second resist layer is covered on the circuit board with the patterned trace layer. Second openings are formed in the second resist layer to expose part of the trace layer to be used as electrical connecting pads. Thereafter, metal bumps are electroplated in the second openings and the surface of the circuit board is covered with a solder mask. A thinning process is applied to the solder mask to expose the top surface of the metal bumps. Afterwards, an adhesive layer is formed on the surface of the metal bumps exposing out of the solder mask.

Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each other; and an interconnect electrically connected to the electrode and extending over one of the first portions of the resin protrusion. A lower portion of a side surface of the second portion includes a portion which extends in a direction intersecting a direction in which the resin protrusion extends.

Abstract: A small and thin surface-mount type optical semiconductor device having high air tightness, which can be manufactured at a reduced cost includes: a base 2 formed of a glass substrate; a recess 5 formed on a first main surface 3 of the base; a through hole 7 extending from a bottom portion 4 of the recess to a second main surface 6 of the base; an inner wall conductive film formed on an inner wall surface of the through hole; a wiring pattern 9 made of a conductive film formed around an opening of the through hole on the bottom portion of the recess so as to be connected electrically to the inner wall conductive film; an optical semiconductor element 8 bonded to the wiring pattern via a conductive bonding material 14; a terminal portion 10 made of a conductive film formed around an opening of the through hole on the second main surface such that it is connected electrically to the inner wall conductive film; and a metal portion 13 bonded to the inner wall conductive film to clog the through hole.

Abstract: An electric power semiconductor device including first and second circuit patterns formed on main surfaces of first and second insulating substrates, respectively, first and second semiconductor chips mounted on the first and second circuit patterns, respectively, a multilayer electrode plate assembly disposed between the first and second insulating substrates, having first, second and third electrode terminals provided with a distance from each other, a first connecting conductor made by wire bonding for connecting the first and second semiconductor chips to the first and second electrode terminals, and a second connecting conductor having an extending portion extended from a part of the third electrode terminal to be connected to the second circuit pattern, and the connection between the extending portion of the third electrode terminal and the second circuit pattern is implemented by a solder.

Abstract: A contact pad is disclosed including a first electrode pattern with an open portion inside, an insulation layer formed on the first electrode pattern and having a contact via portion formed therein, and a second electrode pattern formed on the insulation layer and electrically connected to the first electrode pattern through the contact via portion. The second electrode pattern comprises single electrode patterns spaced apart from one another. A thin film transistor substrate and a liquid crystal display panel having the contact pad are also disclosed.