Abstract: An electronic device having a plurality of electronic components placed on a substrate, each component being constituted by a portion of a layer of active material joined mechanically to the substrate by an electrically conductive joining element pertinent to it, the layer of active material having at least one trench delimiting, at least in part, groups of electronic components each having at least two components and forming successive strips, two successive strips having a common boundary.

Abstract: Substrates including conductive pads for coupling the substrates to a microelectronic device and/or package are described herein. Embodiments of the present invention provide substrates comprising one or more conductive pads including a base portion and a pillar portion, the pillar portion being configured to couple with a microelectronic device. According to various embodiments of the present invention, the substrate may be a printed circuit board and/or may be a carrier substrate incorporated into an electronic package. The pillar portion may facilitate interconnection between the substrate and a microelectronic device or package by effectively raising the height of the conductive pad. Other embodiments may be described and claimed.

Abstract: A process for manufacturing a substrate with bumps is provided. First, a metallic substrate having a body and a plurality of conductive elements is provided. Next, a first dielectric layer is formed on the body, and the conductive elements are covered by the first dielectric layer. Then, a plurality of circuits and a plurality of contacts are formed on a surface of the first dielectric layer, and the contacts are electrically connected to the conductive elements. Next, a second dielectric layer is formed on the surface of the first dielectric layer, and the circuits are covered by the second dielectric layer. Finally, the body is patterned to form a plurality of bumps, and the bumps are electrically connected to the contacts by the conductive elements. The bumps are formed by etching the body, so the connection reliability between bumps and conductive elements is desirable, and the manufacturing cost is reduced.

Abstract: Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling.

Abstract: A microelectronic assembly includes a microelectronic element, such as a semiconductor wafer or semiconductor chip, having a first surface and contacts accessible at the first surface, and a compliant layer overlying the first surface of the microelectronic element, the compliant layer having openings in substantial alignment with the contacts of the microelectronic element. The assembly desirably includes conductive posts overlying the compliant layer and projecting away from the first surface of the microelectronic element, the conductive posts being electrically interconnected with the contacts of the microelectronic element by elongated, electrically conductive elements extending between the contacts and the conductive posts.

Abstract: According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections.

Abstract: A carrier (100) for bonding a semiconductor chip (114) onto is provided, wherein the carrier (100) comprises a die pad (101) and a plurality of contact pads (102), wherein each of the plurality of contact pads (102) comprises an electrically conductive multilayer stack, wherein the electrically conductive multilayer stack comprises a surface layer (109), a first buffer layer, and a first conductive layer (108). Furthermore, the first buffer layer comprises a material adapted to prevent diffusion of material of the surface layer (109) into the first conductive layer (108), and at least two of the contact pads (102) has an ultrafine pitch relative to each other.

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.

Abstract: A semiconductor device is of a PoP structure such that first electrode portions provided in a first semiconductor module and second electrode portions provided in a second semiconductor module are joined together by solder balls. The first electrode has a first conductor having the same thickness as that of a wiring layer provided in an insulating layer, a second conductor formed on the first conductor, a gold plating layer provided on the second conductor.

Abstract: An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon.

Abstract: An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

Abstract: A semiconductor packaging system includes a semiconductor die and a solder pillar on a side of the semiconductor die extending outwardly from a side of the semiconductor die. The solder pillar electrically couples to an electrical contact of a packaging substrate, even when access to the electrical contact is limited by a mask.

Abstract: A semiconductor package and a method for making the same, whereby the semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, and second and third metal layers. The substrate has a surface having at least first and second pads. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: An article including a substrate having a blind hole formed therein, wherein the blind hole is defined by a floor and a sidewall and a solder connection is provided. The solder connection may couple a first contact pad to a second contact pad. The first contact pad may cover a first field of the floor of the blind hole, and may also promote wetting of a solder material of the solder connection. Wetting may be impeded on a second field of the floor of the blind hole. The second contact pad may be arranged above a surface of a further substrate, wherein the surface of the further substrate may be oriented perpendicularly to the floor of the blind hole in the substrate.

Abstract: A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided on a substrate. The first tin-containing layer may be joined with the second tin-containing layer during a packaging process.

Abstract: A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Abstract: An optical transmitter includes a package including a cavity formed at an upper part thereof, a light transparent member disposed on the package, and a flexible substrate including a circuit pattern formed on at least one side thereof and being placed on a back surface of the light transparent member.

Abstract: An RFID tag including a base including a resin material, an antenna pattern disposed on a surface of the base, and a reinforcement pad disposed on the surface of the base. A thermosetting adhesive is applied onto the antenna pattern and the reinforcement pad, and a circuit chip is electrically coupled to the antenna pattern via the thermosetting adhesive. The reinforcement pad is formed within a region where the circuit chip is mounted, and the circuit chip includes a first protrusion contacting the antenna pattern and a second protrusion contacting the reinforcement pad.

Abstract: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires.

Abstract: A packaging substrate having an electrical connection structure and a method for fabricating the same are provided. The packaging substrate have a substrate body with a plurality of conductive pads on a surface thereof; a solder mask layer disposed on the substrate body with a plurality of openings corresponding to the conductive pads, the size of each of the openings being larger than each of the conductive pads; and electroplated solder bumps for covering the conductive pads to provide better bond strength and reliability.

Abstract: Provided are a spacer capable of avoiding a poor connection due to the suction of solder when the clearance width between a soldered semiconductor device and a printed circuit board is made constant, and a manufacturing method for the spacer. The spacer includes an electrically insulating base member, and at least one solder guiding terminal. The base member has a bottom face, a top face and at least one side face, of which the bottom face and the top face are out of contact with each other whereas the side face contacts one or both the bottom face and the top face. The solder guiding terminal covers the bottom face partially, the top face partially, and the side face partially or wholly. A solder guiding face as the surface of a portion of the solder guiding terminal covering the side face is not normal to the bottom face.

Abstract: Methods of forming microelectronic device structures are described. Those methods may include forming a passivation layer on a substrate, wherein the substrate comprises an array of conductive structures, forming a first via in the passivation layer, forming a second via in the passivation layer that exposes at least one of the conductive structures in the array, and wherein the second via is formed within the first via space to form a step via, and forming a conductive material in the step via, wherein a round dimple is formed in the conductive material.

Abstract: A column is coupled to a last metallization of a die and the column is mated to a mounting substrate with that aid of a solder. The column may have the solder attached thereto before mating to the mounting substrate and the mounting substrate may be a bare-board (no solder mask) during the mating process. The column has an aspect ratio between 0.75 and 10.

Abstract: A package of a micro-electro-mechanical systems (MEMS) device includes a cap wafer, a plurality of bonding bumps formed over the cap wafer, a plurality of array pads arrayed on an outer side of the bonding bumps, and an MEMS device wafer bonded to an upper portion of the cap wafer in a manner to expose the array pads.

Abstract: The present invention provides a semiconductor component having a joint structure including a semiconductor device, an electrode disposed opposite the semiconductor device, and a joining material which contains Bi as main component and connects the semiconductor device to the electrode. Since the joining material contains a carbon compound, joint failure due to the difference in linear expansion coefficient between the semiconductor device and the electrode can be reduced compared with conventional materials. The joining material which contains Bi as main component enables provision of a joint structure in which a semiconductor device and an electrode are joined by a joint more reliable than a conventional joint.

Abstract: The present invention provides a semiconductor device for which thermal stress at mounting is reduced and a reduction in reliability with regard to moisture absorption is prevented. The semiconductor device includes a uppermost metal layer 12, a solder bump 17, metals 15 and 16 which connect an uppermost metal layer 12 and the solder bump 17, and, a polyimide multilayer 14 having formed therein an opening 14x in which the metals 15 and 16 are provided. The polyimide multilayer 14 includes a first polyimide layer 14A and a second polyimide layer 14B formed on the first polyimide layer 14A. The second polyimide layer 14B is softer than the first polyimide layer 14A. A thermal stress at mounting is reduced by the second polyimide layer 14B. Since the first polyimide layer 14A has a higher strength than the second polyimide layer 14B, even if cracking occurs in the second polyimide layer 14B, the cracks are prevented from developing in the first polyimide layer 14A.

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, first dielectric layer, an underfill layer, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The underfill layer is formed over the top surface of the first dielectric layer and within the first opening. The second substrate is formed over and in contact with the underfill layer.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: A semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate, and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity. The electrically-conductive platform has a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion. The semiconductor device also includes a cushioning material disposed in the cavity.

Abstract: An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Abstract: To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability. A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals.

Abstract: A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the center axes of the sprocket openings in each layer being substantially alignable with one another, the diameter of the sprocket openings in an abutting layer for first receiving the sprocket being greater than the diameter of the sprocket openings in an abutted layer. This is followed by forming a plurality of reservoir openings in each of at least two of the layers and positioning the sprocket openings in the layers to correspond with one another and the reservoir openings in the layers to correspond with one another so that substantial alignment of the center axes of the corresponding sprocket openings in the layers effects substantial alignment of the center axes of the corresponding reservoir openings in the layers.

Abstract: A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation layer is also provided overlying the major surface of the substrate. The passivation layer overlies the contact pad such that it exposes at least a portion of the contact surface. A plurality of metal layers arranged in a stack overlie the contact surface and at least a portion of the passivation layer. The stack includes multiple layers, which can have different thicknesses and different metals, with the lowest layer including titanium (Ti) and nickel (Ni) in contact with the contact surface.

Abstract: A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching.

Abstract: A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

Abstract: Methods for making, and structures so made for producing integrated circuit (IC) chip packages without forming micro solder balls. In one embodiment, a method may include placing a solid grid made from an organic material between the IC chip and the substrate. The grid provides a physical barrier between each of a plurality of Controlled Collapse Chip Connections, and thereby prevents the formation of micro solder balls between them, thus improving chip performance and reliability.

Abstract: A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch.

Abstract: A substrate structure having non-solder mask design (N-SMD) ball pads. The substrate structure includes a substrate and a solder mask. The substrate has a first surface, a trace layer and at least one ball pad. The ball pad and the trace layer are disposed on the first surface. The trace layer has a plurality of traces, and at least one trace electrically connects to the ball pad. The solder mask has at least one opening corresponding to the ball pad. The size of the opening is larger than that of the ball pad. The solder mask covers the trace connecting to the ball pad. The problem of non-alignment of the solder ball can thus be solved, and the hole in the solder ball can be prevented when the substrate structure is welded with a PCB so that the reliability of solder ball welding can be improved.

Abstract: Provided is an electronic circuit device in which the bonding state of electrodes can be detected easily with high precision. The electronic circuit device has a stack structure in which a plurality of electronic circuit boards (1a, 1b, 100a, 100b, 100c) are stacked in three or more layers through ball electrodes (10a, 10b, 20a, 20b) bonded to electrode pads (30a, 30b, 40b, 50a, 60a), wherein the electrode pads are disposed such that transmission shaded images of a pair of the electrode pads provided between adjacent layers partially overlap each other and have a non-overlapping region in which the transmission shaded images of the pair of electrode pads are free from overlapping and such that the transmission shaded image of the non-overlapping region is at least partially free from overlapping with transmission shaded images of all the other electrode pads.

Abstract: It is desired to provide an electronic device which can be easily taken out of a mold after a resin sealing processing. The electronic device include: an insulating layer; a wiring formed on the insulating layer; and a solder resist layer formed to cover the insulation layer and the wiring and including particles of an elastomer. An asperity is formed on a surface of the solder resist layer.

Abstract: It is desired to provide an electronic device which can be easily taken out of a mold after resin sealing processing. The electronic device includes: an insulating layer; a wiring layer formed on a surface of the insulating layer; a first solder resist formed to cover the insulating layer and the wiring layer and including a particle of a first elastomer; and a second solder resist formed to cover a surface of the first solder resist. A surface of the second solder resist has smaller adhesive strength than the surface of the second solder resist at a glass transition point of the first elastomer.

Abstract: Electrode pads (5) and a solder resist (7) are disposed on the upper surface of a wiring board (1), and apertures (7a) are formed in the solder resist (7) so as to expose the electrode pads (5). Electrodes (4) are disposed on the lower surface of a semiconductor element (2). Electrodes (4) are connected to the electrode pads (5) by way of bumps (3). An underfill resin (6) is disposed in the area that excludes the solder resist (7) and the bumps (3) in the space between the wiring board (1) and the semiconductor element (2). Between the wiring board (1) and the semiconductor element (2), the thickness (B) of the solder resist (7) is equal to or greater than the thickness (A) of the underfill resin (6) on the solder resist (7). The volume (Vb) of the bumps (3) is less than the volume (Vs) of the apertures (7a).

Abstract: A semiconductor device is provided in which a semiconductor chip is bonded to a substrate with a sufficiently increased bonding strength and cracking is assuredly prevented which may otherwise occur due to heat shock, heat cycle and the like. The semiconductor device includes a semiconductor chip and a substrate having a bonding area to which the semiconductor chip is bonded via a metal layer. The metal layer includes an Au—Sn—Ni alloy layer and a solder layer provided on the Au—Sn—Ni alloy layer. Undulations are formed in an interface between the Au—Sn—Ni alloy layer and the solder layer.

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract: A layered structure comprises a variable wettability layer including a material that changes a critical surface tension in response to energy provided thereto, the wettability changing layer including at least a high surface energy part of large critical surface tension and a low surface energy part of low critical surface tension, a conductive layer formed on the variable wettability layer at the high surface energy tension part, and a semiconductor layer formed on the variable wettability layer at the low surface energy part.

Abstract: A method generates at least one electrical connection from at least one electronic component, which is positioned on a substrate inside an encapsulation, to outside the encapsulation. The functional capability of the electrical connection is to be provided at ambient temperatures greater than 140° C. and in the event of large power losses and extreme environmental influences. A reactive nanofilm, having targeted reaction, which can be triggered exothermically by laser, is used to produce hermetically sealed electrical connections. Using the nanofilm, an output of an electrical connection and a contact of the electrical connection to at least one further electrical contact can be provided.

Abstract: A method is provided for the removal of tin or tin alloys from substrates such as the removal of residual tin solder from the molds used in the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and uses an etchant composition comprising cupric ions and HCl. Cupric chloride and cupric sulfate are preferred. A preferred method regenerates cupric ions by bubbling air or oxygen through the etchant solution during the cleaning process.

Abstract: A layer assemblage for a semiconductor chip having a chip body for producing a soldering connection for the chip. The assemblage is provided on a side of a chip body formed from a semiconducting material, wherein the layer assemblage is formed from a plurality of sequential metal layers which follow one above another and are produced by means of a physical coating method, and wherein a solderable soldering layer is provided between a noble metal layer situated at a surface of the layer assemblage and the chip body. In order to avoid an undesired penetration of a solder through the layer assemblage the soldering layer has at least one internal interface formed by an interruption of the coating method.

Abstract: A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.

Abstract: A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier.