Abstract: The present invention relates to a semiconductor device in which electrodes formed on a semiconductor chip and electrodes formed on a wiring board are electrically connected via projecting elastic electrodes, and further relates to a mounting method of reducing a pressure applied to electrodes formed on a substrate or underlying wirings when a semiconductor chip and a wiring board are bonded.

Abstract: A semiconductor component and a method for its production in semiconductor chip size, can have a semiconductor chip, which has external contacts of the semiconductor component that are arranged in the manner of a flip-chip on its active upper side. The semiconductor chip can be encapsulated by a plastic compound at least on its rear side and its side edges. The outer contacts, which can be arranged on external contact connecting areas, can project from the active upper side.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: In a semiconductor device, a semiconductor chip is connected to a board through an interconnection layer. A plurality of first terminals, a plurality of second terminals and a plurality of third terminals are provided on the board, the interconnection layer and the semiconductor chip, respectively. The second terminals are connected to the first terminals through the board. The third terminals are connected to the second terminals. The interconnection layer is rotatable about a rotation axis perpendicular to an upper surface of the interconnection layer. A first terminal having a specific function out of the first terminals and a third terminal having the specific function out of the third terminals are connected to each other by rotating the interconnection layer.

Abstract: A semiconductor chip includes flip chip contacts that are arranged on contact surfaces of an active top side of the semiconductor chip. The contact surfaces are surrounded by a passivation layer that covers the active top side while leaving exposed the contact surfaces. The passivation layer includes thickened portions that surround the contact surfaces. The semiconductor chip formed with thickened portions around the contact surfaces is protected from delamination during packaging of the semiconductor chip to form a semiconductor device.

Abstract: Pad structures and methods for forming such pad structures are provided. For the pad structure, the first conductive material layer has a first hardness over about 200 kg/mm2. The second conductive material layer is over the first conductive material layer and has a second hardness over about 80 kg/mm2. For the method of forming the pad structure, a plurality of first conductive material layers is formed within each of a plurality of openings of a substrate. The substrate has a plurality of openings therein. The first conductive material layers are formed within each of the openings of the substrate. The first conductive material layers substantially have a round top surface. The second conductive material layers are formed and substantially conformal over the first conductive material layers. The second conductive material layers cover a major portion of the round top surface of the first conductive material layers.

Abstract: Substrates having molded dielectric layers and methods of fabricating such substrates are disclosed. The substrates may advantageously be used in microelectronic assemblies having high routing density.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.

Abstract: The present invention relates to methods and arrangements for forming a solder joint connection. One embodiment involves an improved solder ball. The solder ball includes a perforated, metallic shell with an internal opening. Solder material encases the shell and fills its internal opening. The solder ball may be applied to an electrical device, such as an integrated circuit die, to form a solder bump on the device. The solder bump in turn can be used to form an improved solder joint connection between the device and a suitable substrate, such as a printed circuit board. In some applications, a solder joint connection is formed without requiring the application of additional solder material to the surface of the substrate. The present invention also includes different solder bump arrangements and methods for using such arrangements to form solder joint connections between devices and substrates.

Abstract: A package module with an alignment structure is provided by this invention. The package module comprises a package substrate having a die region and a die disposed thereon. At least one pair of conductive alignment protrusions is disposed in the die region and is separated from each other by the die. A test pad is disposed on the package substrate opposing the die and electrically connected to the pair of conductive alignment protrusions. An electronic device with an alignment structure and an inspection method after mounting is also disclosed.

Abstract: A method of manufacturing an electronic component minimizes the occurrence of voids and degradation of characteristics in a resin-sealed portion, while reducing the costs thereof. A sealing step for sealing surface acoustic wave elements by a sealing resin member formed from a resin film is performed by mounting the surface acoustic wave elements on a collective mounting substrate and the resin film in a bag with a gas-barrier property, and causing the resin film to infiltrate between the surface acoustic wave elements mounted on the reduce-pressured-packed collective mounting substrate to be hermetically sealed by the pressure difference between the inside and the outside of the bag.

Abstract: A circuit device includes a semiconductor substrate on which a circuit element is formed, an electrode formed on a surface of the semiconductor substrate, an insulating layer formed on the electrode, a second wiring layer formed on the insulating layer, and a conductive bump which penetrates the insulating layer and electrically connects the electrode and the second wiring layer. The conductive bump is such that the size of crystal grains in a direction parallel with the surface of the semiconductor substrate is larger than the size of crystal grains in a conduction direction of the electrode and the wiring layer.

Abstract: A semiconductor die has conductors encapsulated in a dielectric material disposed on the active surface extending across the active surface from bond pads to one or more peripheral edges where the conductor ends are disposed at a side surface of the dielectric material. Stacks of such semiconductor dice, wherein one of the dice is configured with discrete conductive elements projecting from the active surface, and the exposed ends of the dice in the stack are connected with vertical interconnects. A probe card is disclosed having bond wires extending from one or more central contacts between one or more peripheral contacts to the edge of the probe card. A probe card having an upper layer bearing contacts and at least one window therethrough, a lower layer bearing conductive traces with ends exposed through the at least one window, and conductors extending from at least some of the contacts to conductive trace ends is also provided. Methods of making the foregoing structures are disclosed.

Abstract: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.

Abstract: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Abstract: The present invention provides a unique way of connecting a flip-chip die to a substrate. Initially, metallic posts are formed on the flip-chip die and solder bumps are placed on the substrate where the metallic post will ultimately connect to the substrate. The tip layer of flash gold, tin, or other wettable electroplated material is applied to the tips of the metallic posts to prevent oxidation and enhance wettability. The sides of the metallic posts are allowed to oxidize to reduce wettability. To attach the flip-chip die to the substrate, the flip-chip die is initially positioned over the substrate, such that the metallic posts align with and come into contact with the solder bumps. Once the flip-chip die is in place over the substrate, the substrate and the flip-chip are heated to cause the solder bumps to reflow and bond to the tip layers of the metallic posts.

Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

Abstract: A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.

Abstract: A pad for soldering a contact of a surface mounted component is provided herein. The pad includes a central portion and a plurality of separate extending portions extending from the central portion. All of the plurality of separate extending portions includes a free end and a connected end connected to the central portion. A width of the free end is larger than a width of the connected end. A circuit board and an electronic device are also provided.

Abstract: A semiconductor device includes: a base substrate; a semiconductor chip formed on the base substrate in such a manner that an adhesive layer is interposed between the semiconductor chip and the base substrate; a resin layer covering at least a portion of the semiconductor chip; and an external connection terminal electrically connected to the base substrate via a wiring layer. The external connection terminal is in the same plane as the surface of the resin layer, and is exposed from the resin layer. With this configuration, it is possible to provide a semiconductor device of a lower stage, and a stacked semiconductor device, each of which is high in connection reliability in a case of stacking plural semiconductor devices, no matter if a connection terminal of a semiconductor device stacked on an upper stage is low.

Abstract: A semiconductor loading lead pin that does not tilt at a time of reflow. A void is sometimes left in solder between an electrode pad and the flange of a semiconductor loading lead pin. When reflow is carried out to load an IC chip, the solder for connection is melted and at the same time, the void in the solder is expanded. The solder escapes sideway along the groove portion, and thereby a flange is not raised by the void so that the semiconductor loading lead pin is not tilted.

Abstract: An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Abstract: In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings (310) and bump pad openings (330); the metal layer (360) has atop (340) and bottom (360) layer. In the metal layer (360), bond pad connections (310) and bump pad connections (330) are defined (25, 30) by removing the top layer of metal in areas other than at bond pad openings (310) and bump pad openings (330), and leaving the bottom layer (360) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined (35, 40). A second organic dielectric layer (325) is deposited (45) on the silicon substrate (305), enveloping the circuit pattern.

Abstract: An audio power amplifier package includes a non-signal lead, a first non-signal pad, a second non-signal pad and a plurality of bonding wires. The first non-signal pad and the second non-signal pad are disposed on a substrate. The bonding wires connect the non-signal lead to the first non-signal pad and the second non-signal pad respectively.

Abstract: A package structure having a semiconductor chip embedded therein and a method of fabricating the same are disclosed. The package structure comprises: an aluminum oxide composite plate and a semiconductor chip. The aluminum oxide composite plate is formed by a stack consisting of an adhesive layer placed in between two aluminum oxide layers. The semiconductor chip having an active surface a plurality of electrode pads disposed thereon can be embedded and secured in the aluminum oxide composite plate. The present invention also comprises a method of fabricating the above-mentioned package structure. The present invention provides an excellent package structure, which can decrease the thickness of the package structure and make the package structure having characteristics of high rigidity and enduring tenacity at the same time.

Abstract: The present invention provides a semiconductor device which comprises a lead frame including a die pad having one or two or more openings, a substrate mounted over the die pad so as to expose a plurality of semiconductor chip connecting second electrode pads from the openings of the die pad, a plurality of semiconductor chips mounted over the die pad and the substrate, bonding wires that connect chip electrode pads of the semiconductor chip and their corresponding semiconductor chip connecting first and second electrode pads of the substrate, and a sealing portion which covers these and is provided so as to expose parts of leads.

Abstract: An electrical component includes a substrate, a first integrated circuit attached to the substrate, a metal portion coupled to the first integrated circuit, and a second integrated circuit attached to the first integrated circuit. The metal portion is sandwiched between the first integrated circuit and the second integrated circuit.

Abstract: A redistribution connecting structure for solder balls is disclosed. A substrate includes a plurality of bonding pads. A plurality of dielectric layers, a redistribution conductive layer between the dielectric layer, and a plurality of solder balls are formed on the substrate. The redistribution layer has a redistribution pad disposed adjacent to one of the bonding pads without electrical connection with the redistribution pad. One of the dielectric layers covering the redistribution conductive layer has an opening to partially expose the redistribution pad, in which the opening is approximately circular and has a cut-off portion so that the opening is adjacent to an opening of another of the dielectric layers exposing one of the bonding pads without overlapping. Accordingly, bonding area of the redistribution pad for a bonding pad under one of the solder balls can be expanded to reduce stress effect.

Abstract: Substrates including conductive pads for coupling the substrates to a microelectronic device and/or package are described herein. Embodiments of the present invention provide substrates comprising one or more conductive pads including a base portion and a pillar portion, the pillar portion being configured to couple with a microelectronic device. According to various embodiments of the present invention, the substrate may be a printed circuit board and/or may be a carrier substrate incorporated into an electronic package. The pillar portion may facilitate interconnection between the substrate and a microelectronic device or package by effectively raising the height of the conductive pad. Other embodiments may be described and claimed.

Abstract: Provided is a wafer level chip scale package that reduces the parasitic capacitance generated between ball pads and the solder balls, and enhances the joint reliability between the ball pads and the solder balls. The wafer level chip scale package provides a conductive pattern in each ball pad section, on which a solder ball is mounted, so as to have a spiral or mesh shape, provides a space defined by the conductive pattern such that a first dielectric layer under the conductive pattern is exposed, and provides the solder ball on a top surface of each ball pad section such that part of the solder ball is inserted into the space defined by the conductive pattern. When viewed from the top, the dielectric layer is exposed from each ball pad section by an area of about 50% or less.

Abstract: A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main surface of a second element a second solder ball, providing contact between the first solder ball and the second solder ball, bonding the first element and the second element by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a nonconductive material, such that the upper part of the first solder ball is not covered by the non-conductive material. Devices related to such methods are also disclosed.

Abstract: Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross-section and a second portion in the form of a hollow ball, extending laterally further within the wafer than the first portion. Back-grinding the wafer to the second portion of the via may create a vent. A conductive path may be formed by filling the via with a conductive material, such as solder. Flux gases may escape through the vent. The wafer surrounding the second portion of the via may be removed, exposing a conductive element in the shape of a ball, the shape of the second portion of the via. Semiconductor devices including the conductive paths of the present invention are also disclosed.

Abstract: The semiconductor integrated circuit device includes: an active element, an interlayer insulting film, first and second metal patterns made of a first metal layer formed right above the active element, first and second buses made of a second metal layer formed right above the first metal layer, and contact pads provided on the first and second buses. The contact pad has a probe testing region and a bonding region.

Abstract: The present invention provides a method for manufacturing a semiconductor device which includes at least supplying an adhesive for bonding an electronic component which has a plurality of bumps with a substrate which has a plurality of bonding pads corresponding to the bumps, to at least a portion of the substrate, between the electronic component and the substrate, flow-casting the adhesive on the substrate by a flow-casting unit, in such a manner that the expression S1/S0>1 is satisfied, where S0 is the total contact surface area with the substrate of the adhesive supplied to the substrate, and S1 is the total contact surface area with the substrate of the adhesive after the flow-casting, and curing the adhesive while making the adhesive contact with the electronic component and the substrate in a state where the bumps are abutted against the bonding pads.

Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-down configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-down flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.

Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.

Abstract: A bump structure includes a squashed ball provided on an electrode pad, and a wire provided on the squashed ball. The wire is a wire loop that is loop-shaped and is formed so as to protrude from an end part of the squashed ball. This provides high bonding reliability between a bonding pad and the bump structure.

Abstract: To provide a high-performance, highly-reliable semiconductor device in which an adhesive used to mount (e.g., flip-chip mount) a semiconductor chip on a substrate has less air bubbles, and a low-cost, efficient method for manufacturing the same. Semiconductor device 10 of the present invention includes semiconductor chip 11 having a plurality of electrode pads 12, and substrate 14 having a plurality of electrode terminals 15 at positions corresponding to electrode pads 12. A plurality of bumps 13, each composed of base part 13A and protruding part 13B having a diameter smaller than the diameter of base part 13A, is formed on at least one of electrode pads 12 in such a way that the respective base parts 13A of bumps 13 are in contact with each other, and semiconductor chip 11 is bonded to substrate 14 with adhesive 17 in a state where bumps 13 are electrically connected to electrode terminals 15.

Abstract: A stacked integrated circuit leadframe package system including forming a leadframe, packaging a top integrated circuit on a one side of the leadframe, packaging a bottom integrated circuit on an opposite side of the leadframe, and forming external electrical interconnects on the leadframe.

Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.

Abstract: A removable wafer expander for die bonding equipment for a singularized wafer supported by a flexible sticky substrate, the removable wafer expander provided with a first ring member to be coupled with a second ring member for remote expansion of the flexible sticky substrate therebetween before the mounting of the wafer expander onto the die bonding equipment.

Abstract: A semiconductor device provided with a semiconductor chip wherein an electrode pad is formed on a circuit formation surface, includes a first passivation film, which serves as an adhering layer; a second passivation film formed on the first passivation film, for protecting the semiconductor chip from external physical damage; a metal film formed so as to cover at least a first electrode-pad opening section of the first passivation film; and an external connection terminal to connect the electrode pad to an external equipment. A second electrode-pad opening section of the second passivation film is formed so as to expose the first electrode-pad opening section entirely. The second passivation film is formed so as not to be in direct contact with the electrode pad.

Abstract: A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.

Abstract: A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of an electrical connection layer. The conductive traces provide connection between an array of discrete conductive elements and bonding wires connected to bond pads of the die. The conductive layer enhances thermal conduction and structural stiffness for the assembly. In addition, the conductive layer provides a voltage reference plane that may be connected to a power source, a ground source, or an intermediate reference voltage. The conductive layer also includes at least one electrical current isolation slot, which segments the conductive layer to help isolate noise induced in one segment of the conductive layer from the other segments.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.

Abstract: An assembly includes a semiconductor die disposed between an upper substrate and a lower substrate. A circuit board that defines a through hole is spaced axially below the upper substrate to define a gap between the upper substrate and the circuit board. An upper heat sink is thermally connected to the upper substrate by an upper thermal interface material to transfer heat in a first dissipation path to the upper heat sink. A lower heat sink is thermally connected to the lower substrate by a lower thermal interface material to transfer heat in a second dissipation path to the lower heat sink. A plurality of first interconnectors are disposed in the gap to solder the upper substrate to the circuit board. The assembly is distinguished by a plurality of second interconnectors that are disposed between the upper substrate and the lower substrate to position the lower substrate in the through hole of the circuit board.

Abstract: A semiconductor device including a circuit structure and a protective layer is provided. The circuit structure has multiple contacts. The protective layer is located on the circuit structure and has multiple openings and multiple protrusions, wherein the contacts are exposed by the openings and the protrusions are located on the contacts.

Abstract: A semiconductor package module having no solder balls and a method of manufacturing the semiconductor package module are provided. The semiconductor package module includes a module board on which a plurality of semiconductor devices are able to be mounted, a semiconductor package bonded on the module board using an adhesive, being wire-bondable to the module board, and having already undergone an electrical final test, second wires electrically connecting second bond pads of the semiconductor package to bond pads of the module board; and a third sealing resin enclosing the second wires and the semiconductor package. Because the semiconductor package module does not use solder balls, degradation of solder joint reliability (SJR) can be prevented. Further, the use of a semiconductor package that has already undergone an electrical test can reduce degradation of the yield of a completed semiconductor package module.

Abstract: A collective substrate (1) is produced by firing a ceramic green sheet and forming through-holes (11) in the resulting substrate. The through-holes (11) each have an interior surface including taper surfaces (11b, 11c) which are tapered as having an opening size progressively decreasing from a main surface (21) and an external connection surface (22) toward a minimum size hole portion (11a). The taper surfaces (11b, 11c) respectively form obtuse angles ?1, ?2 with the main surface (21) and the external connection surface (22). A semiconductor element mount (BL) includes an insulative member (2) cut out of the collective substrate (1). An imaging device (PE2) includes an imaging element (PE1) mounted in a region surrounded by a frame (4) which is bonded to the main surface (21) of the insulative member (2) and closed by a cover (FL).

Abstract: A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the semiconductor pellet. The base substrate is formed of a rigid substrate, and its first electrode pads are electrically connected to the second electrode pads arranged on its reverse side. The semiconductor pellet is mounted on the pellet mounting area of the main surface of the base substrate, with its main surface downward, and its bonding pads are connected electrically with the second electrode pads of the base substrate through bonding wires passing through slits formed in the base substrate.