Abstract: An electronic device includes a main printed circuit board (PCB) assembly comprising a bottom PCB and a semiconductor package mounted on an upper surface of the bottom PCB. The semiconductor package includes a substrate and a semiconductor die mounted on a top surface of the substrate. The semiconductor die and the top surface of the substrate are encapsulated by a molding compound. A top PCB is mounted on the semiconductor package through first connecting elements.

Abstract: A printed circuit board includes a first insulating layer; a pad disposed on the insulating layer and having a protrusion; and a protective layer disposed on the insulating layer and having an opening exposing at least a portion of the pad. The protrusion protrudes from one surface of the pad and is buried in at least one of the insulating layer and the protective layer.

Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

Abstract: A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.

Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Abstract: In-Substrate Structures (ISS) and isolation regions, including, but not limited to Through Metal Vias (TMV), Dielectric Isolation Vias (DIV), and Dielectric Isolation Pockets (DIP) formed in a metal substrate to provide enhanced operations for semiconductor packages incorporating a metal substrate, and methods of making the same.

Abstract: A cell region of a semiconductor device, the cell region including: components (representing a first circuit) including alpha info conductors and dummy conductors which are substantially collinear correspondingly with reference tracks, regarding the first circuit, the alpha info conductors beipng correspondingly for one or more input and/or output signals, or one or more internal signals, and for a majority of the reference tracks, first ends correspondingly of the alpha info conductors or the dummy conductors being aligned and proximal to a first side of the cell region; a first alpha info conductor being on a first reference track and being an intra-cell conductor which does not extend beyond the first side nor a second side of the cell region; and a portion of a first beta info conductor of a second circuit (represented by components of an external cell region) being on the first reference track.

Abstract: In one embodiment a power semiconductor module includes a substrate having a first substrate side for carrying an electric circuit and having a second substrate side being located opposite to the first substrate side. The second substrate side has a flat surface and is adapted for coming in contact with a cooler. A cooling area that is surrounded by a connecting area is located at the second substrate side. A first casing component of the cooler is connected to the second substrate side at the connecting area and a second casing component is connected to the first casing component such that a cooling channel for providing the cooling area with cooling fluid is provided between the first casing component and the second casing component. A cooling structure can be welded to the cooling area at the second substrate side.

Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

Abstract: Provided is a circuit board on which an electronic component including a first terminal and a second terminal that are arranged side by side is to be mounted, the circuit board including: an insulating holding member, a conductive plate, and a signal circuit, in which the conductive plate is held by the holding member, the first terminal is joined to the conductive plate, the signal circuit is formed on a surface of the holding member using conductive nanoink containing a flux, and an end portion of the signal circuit and the second terminal are joined to each other using solder.

Abstract: Three-dimensional packaging structure for fan-out of bonding wall of device is provided. A first surface of a device is disposed with bond pads and functional area. The device, except for the first surface, is encapsulated with encapsulation material. A first surface of the encapsulation material horizontally connected to the first surface forms a fan-out surface. A wall structure is disposed on the first surface and extends to the fan-out surface. The wall structure partially covers at least one of the bond pads and comprises first opening corresponding to the at least one of the bond pads. Cover plate is bonded with the wall structure to form cavity corresponding to the functional area and comprises at least one second opening in communication with the first opening. A metal interconnection structure is disposed on surface of the cover plate and is electrically connected to the at least one of the bond pads.

Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.

Abstract: A semiconductor device includes a conductive support member, a first semiconductor element, a second semiconductor element, an insulating element, and a sealing resin. The conductive support member includes a first die pad and a second die pad, which are separated from each other in a first direction. The first die pad and the second die pad overlap each other when viewed along the first direction. When viewed along a thickness direction, a peripheral edge of the first die pad has a first near-angle portion including a first end portion in a second direction orthogonal to both the thickness direction and the first direction. The first near-angle portion is separated from the second die pad in the first direction toward the first end portion in the second direction.

Abstract: The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

Abstract: A method of forming a micro electro mechanical system (MEMS) assembly comprises providing a substrate having an electrically conductive layer disposed thereon. The method also comprises depositing, on the substrate over the electrically conductive layer, a bonding material having an elastic modulus of less than 500 MPa so as to form a bond layer. The bond layer is completely cured, and a MEMS die is attached to the completely cured bond layer.

Abstract: According to an embodiment, a substrate treatment apparatus includes a hair member including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While a tip part of the hair member is contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal, and the metal is removed with etching.

Abstract: A package structure is provided. The package structure includes a redistribution structure and a first semiconductor die over the redistribution structure. The package structure also includes a wall structure laterally surrounding the first semiconductor die and the wall structure includes a plurality of partitions separated from one another. The package structure also includes an underfill material between the wall structure and the first semiconductor die. The package structure also includes a molding compound encapsulating the wall structure and the underfill material.

Abstract: An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

Abstract: A temporary protective film for semiconductor sealing molding includes a support film and an adhesive layer provided on one surface or both surfaces of the support film and containing a resin and a silane coupling agent. The content of the silane coupling agent in the temporary protective film may be more than 5% by mass and less than or equal to 35% by mass with respect to the total mass of the resin.

Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height.

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

Abstract: An integrated circuit chip is attached to a support that includes first conductive elements. First conductive pads are located on the integrated circuit chip and are electrically coupled to the first conductive elements by conductive wires. The integrated circuit chip further includes a conductive track. A switch circuit is provided to selectively electrically connect each first conductive pad to the conductive track. To test the conductive wires, a group of first conductive pads are connected by their respective switch circuits to the conductive track and current flow between corresponding first conductive elements is measured.

Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.

Abstract: The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.

Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.

Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.

Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a first dielectric layer, a second dielectric layer and a conductive terminal. The first dielectric layer covers a bottom surface of the die and includes a first edge portion and a first center portion in contact with the bottom surface of the die. The first edge portion is thicker than the first center portion. The second dielectric layer is disposed on the first dielectric layer and laterally surrounding the die. The second dielectric layer includes a second edge portion on the first edge portion and a second center portion in contact with a sidewall of the die. The second edge portion is thinner than the second center portion. The conductive terminal is disposed over the die and the second dielectric layer and electrically connected to the die.

Abstract: An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.

Abstract: Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.

Abstract: A semiconductor device is disclosed including a multi-module interposer for enabling communication between one or more semiconductor dies within the device and a host device on which the semiconductor device is mounted. The multi-module interposer may be formed at the wafer level, and provides fan-out signal paths to and from the one or more dies in the device. Additionally, the multi-module interposer allows any of a variety of different semiconductor packaging configurations to be formed at the wafer level, including for example wire bonded packages, flip chip packages and through silicon via (TSV) packages.

Abstract: Disclosed is a temporary protective film for semiconductor sealing molding comprising: a support film; and an adhesive layer provided on one surface or both surfaces of the support film and containing a resin and a silane coupling agent, and the content of the silane coupling agent in the temporary protective film may be more than 5% by mass and less than or equal to 35% by mass with respect to the total mass of the resin.

Abstract: A method includes surrounding a die and a conductive pillar proximate the die with a molding material, where the die and the conductive pillar are disposed over a first side of a first redistribution structure, where a second side of the first redistribution structure opposing the first side is attached to a first carrier; bonding conductive pads disposed on a first surface of a pre-made second redistribution structure to the die and to the conductive pillar, where a second surface of the pre-made second redistribution structure opposing the first surface is attached to a second carrier; after bonding the conductive pads, removing the second carrier to expose conductive features of the pre-made second redistribution structure proximate the second surface; and forming conductive bumps over and electrically coupled to the conductive features of the pre-made second redistribution structure.

Abstract: A chip stack assembly uses a monolithic metallic multilevel connector to both join connections on at different heights on the top sides at the of the chips, and to provide a large, robust connection surface on top of top of the assembly.

Abstract: A display device may include a first substrate, a first conductive pad, a second conductive pad, a first pad electrode, and a second pad electrode. The first substrate may include a first face and a second face. The first conductive pad may be disposed on the first face. The second conductive pad may be disposed on the first face and may be spaced from the first conductive pad. The first pad electrode may be disposed on the second face, may be electrically connected to the first conductive pad, and may include a protrusion. The second pad electrode may be disposed on the second face, may be electrically connected to the second conductive pad, may be spaced from the first pad electrode, and may include a recess. The protrusion of the first pad electrode may be partially inside the recess the second pad electrode.

Abstract: A semiconductor device package includes an electronic component. The electronic component has an active surface, a back surface opposite to the active surface, and a lateral surface connected between the active surface and the back surface. The electronic component has an electrical contact disposed on the active surface. The semiconductor device package also includes a redistribution layer (RDL) contacting the back surface of the electronic component, a first dielectric layer surrounding the electrical contact on the active surface of the electronic component, and a second dielectric layer surrounding the lateral surface of the electronic component and the first dielectric layer. The second dielectric layer has a first sidewall in contact with the lateral surface of the electronic component and a second sidewall opposite to the first sidewall. The second sidewall of the second dielectric layer has a first portion proximal to the RDL and a second portion distal from the RDL.

Abstract: A structure and method of forming are provided. The structure includes a dielectric layer disposed on a substrate. The structure includes a cavity in the dielectric layer, and a plurality of contacts positioned in the cavity and bonded to the substrate. A component is bonded to the plurality of contacts. Underfill is disposed in the cavity between the dielectric layer and the component. A plurality of connectors is on the dielectric layer, the connectors being connected through the dielectric layer to a conductor that is at a same level of metallization as the plurality of contacts.

Abstract: A semiconductor package structure includes a conductive structure, a first semiconductor chip, a second semiconductor chip, a first encapsulant and an upper semiconductor chip. The first semiconductor chip is electrically connected to the conductive structure. The first semiconductor chip includes at least one first conductive element disposed adjacent to a second surface thereof. The second semiconductor chip is electrically connected to the conductive structure and disposed next to the first semiconductor chip. The second semiconductor chip includes at least one second conductive element disposed adjacent to a second surface thereof. The first encapsulant is disposed on the conductive structure to cover the first semiconductor chip and the second semiconductor chip. The first conductive element and the second conductive element are exposed from the first encapsulant.

Abstract: A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process.

Abstract: The present invention relates to a method of manufacturing a power device and a structure of the power device, which is used to solve the problem that conventional power device needs to be independently packaged and requires a welding process. The method includes: forming a plurality of semiconductor device layers spaced in intervals on a front of a silicon wafer; excavating a plurality of grooves on the front of the silicon wafer to separate the plurality of semiconductor device layers; filling each of the plurality of grooves with each of a plurality of first spacer materials; grinding a back of the silicon wafer until the first spacer materials being exposed; attaching a plurality of metal layers to a region of the back of the silicon wafer opposite to the plurality of semiconductor device layers; and electrically connecting each of independent plurality of lead frames to the plurality of metal layers respectively. The present invention further includes the structure of the power device.

Abstract: A method includes placing a plurality of functional dies over a carrier, placing a plurality of dummy dies over the carrier, encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant, and forming redistribution lines over and interconnecting the plurality of functional dies. The redistribution lines, the plurality of functional dies, the plurality of dummy dies, and the encapsulant in combination form a reconstructed wafer. The plurality of functional dies are in a center region of the reconstructed wafer, and the plurality of dummy dies are in a peripheral region of the reconstructed wafer, with the peripheral region encircling the center region. The reconstructed wafer is de-bonded from the carrier. The reconstructed wafer is bonded to a package component selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof.

Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Abstract: A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.

Abstract: A light-emitting module includes a common carrier; a plurality of semiconductor devices formed on the common carrier, and each of the plurality of semiconductor devices including three semiconductor dies; a carrier including a connecting surface; a third bonding pad and a fourth bonding pad formed on the connecting surface; and a connecting layer. One of the three semiconductor dies includes a stacking structure; a first bonding pad; and a second bonding pad with a shortest distance less than 150 microns between the first bonding pad. The connecting layer includes a first conductive part including a first conductive material having a first shape; and a blocking part covering the first conductive part and including a second conductive material having a second shape with a diameter in a cross-sectional view. The first shape has a height greater than the diameter.

Abstract: The present application provides a power semiconductor module, including a support which carries at least one power semiconductor device, the support together with the power semiconductor device is at least partly located in a housing, the support and the power semiconductor device are at least partly covered by a sealing material, additionally to the sealing material, a protecting material is provided in the housing, the protecting material is formed from silicon gel and the protecting material at least partly covers at least one of the support, the power semiconductor device and the sealing material.

Abstract: A method of manufacturing a 3DIC structure includes the following processes. A die is bonded to a wafer. A first dielectric layer is formed on the wafer and laterally aside the die. A second dielectric material layer is formed on the die and the first dielectric layer. A portion of the second dielectric material layer over a non-edge region of the wafer is selectively removed to form a protruding portion over an edge region of the wafer. The second dielectric material layer is planarized to form a second dielectric layer on the first dielectric layer and the die. A bonding film is formed on the second dielectric layer. A carrier is bonded to the wafer through the bonding film.

Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.