With Adhesive Means Patents (Class 257/783)
  • Patent number: 11398446
    Abstract: A die attachment material may include an ultra-violet (UV) curable resin and silver particles to attach a chip to a submount, where the silver particles are positioned within the UV curable resin. A method may include heating the die attachment material to obtain the UV curable resin on sintered silver particles, where at least a portion of the die attachment material is position between a chip and a submount. The method may further include irradiating, with UV light, the UV curable resin to obtain a polymer on the sintered silver particles. The polymer may form a layer on the sintered silver particles.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: July 26, 2022
    Assignee: Lumentum Operations LLC
    Inventors: Zhengwei Shi, Lijun Zhu, Jihua Du
  • Patent number: 11390777
    Abstract: A sheet for heat bonding, having a pre-sintering layer that becomes a sintered layer by being heated, and a component migration prevention layer.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: July 19, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Satoshi Honda, Yuki Sugo, Mayu Shimoda
  • Patent number: 11393746
    Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Po-Yao Lin, Shuo-Mao Chen, Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 11322385
    Abstract: A pressure sensitive adhesive tape for semiconductor processing includes a base having a Young's modulus of 1000 MPa or more at 23° C., and a pressure sensitive adhesive layer provided on at least one surface of the base, and the product (N)×(C) of (N) and (C) is 500 or more at 30° C., and 9000 or less at 60° C., where (N) [?m] is a thickness of the pressure sensitive adhesive layer and (C) [?m] is a creep amount.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: May 3, 2022
    Assignee: LINTEC Corporation
    Inventors: Kazuto Aizawa, Jun Maeda
  • Patent number: 11296015
    Abstract: A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Giovanni Ragasa Garbin, Chen Wen Lee, Benjamin Reichert, Peter Strobel
  • Patent number: 11223020
    Abstract: A display may have an array of organic light-emitting diodes that form an active area on a flexible substrate. Metal traces may extend between the active area and an inactive area of the flexible substrate. Display driver circuitry such as a display driver integrated circuit may be coupled to the inactive area. The metal traces may extend across a bend region in the flexible substrate. The flexible substrate may be bent in the bend region. The flexible substrate may be made of a thin flexible material to reduce metal trace bending stress. A coating layer in the bend region may be provided with an enhanced elasticity to allow its thickness to be reduced. The flexible substrate may be bent on itself and secured within an electronic device without using a mandrel.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: January 11, 2022
    Assignee: Apple Inc.
    Inventors: Zhen Zhang, Yi Tao, Paul S. Drzaic, Joshua G. Wurzel
  • Patent number: 11196011
    Abstract: A display may have an array of organic light-emitting diodes that form an active area on a flexible substrate. Metal traces may extend between the active area and an inactive area of the flexible substrate. Display driver circuitry such as a display driver integrated circuit may be coupled to the inactive area. The metal traces may extend across a bend region in the flexible substrate. The flexible substrate may be bent in the bend region. The flexible substrate may be made of a thin flexible material to reduce metal trace bending stress. A coating layer in the bend region may be provided with an enhanced elasticity to allow its thickness to be reduced. The flexible substrate may be bent on itself and secured within an electronic device without using a mandrel.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 7, 2021
    Assignee: Apple Inc.
    Inventors: Zhen Zhang, Yi Tao, Paul S. Drzaic, Joshua G. Wurzel
  • Patent number: 11152147
    Abstract: A coil component includes: a body having a first surface and a second surface opposing each other in a thickness direction of the body and a wall surface connecting the first and second surfaces; a coil part including coil patterns and including at least one turn centered on the thickness direction; external electrodes disposed on the first surface of the body and electrically connected to the coil part; a shielding layer including a cap portion disposed on the second surface of the body and side wall portions disposed on the wall surface of the body and each having a first end connected to the cap portion; an insulating layer disposed between the body and the shielding layer; and a gap portion bounded by a second end of the shielding layer opposing the first end and the first surface of the body to expose portions of the wall surface.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tai Yon Cho, Chang Hak Choi, Byeong Cheol Moon, Sang Jong Lee, Hee Soo Yoon, Tae Jun Choi, Seung Hee Oh, Su Bong Jang
  • Patent number: 11130671
    Abstract: A Micro-Electro-Mechanical System (MEMS) device includes a substrate, a packaging component provided on the substrate and a MEMS component provided inside the packaging component and on the substrate. The device further includes a sealing component. The sealing component is provided on the substrate and/or the packaging component, for preventing an external small molecule from contacting with the MEMS component.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: September 28, 2021
    Assignee: WUHAN YANXI MICRO COMPONENTS CO., LTD.
    Inventors: Wei Dong, Re-ching Lin, Pei-chun Liao
  • Patent number: 11107755
    Abstract: Packaging methods and structures for lateral high voltage gallium nitride (GaN) devices achieve electrical isolation while also maintaining thermal dissipation. The electrical isolation reduces or eliminates vertical leakage current, improving high voltage performance. The packages may use or be compatible standards such as JEDEC, which reduces packaging cost and facilitates implementation of the packaged devices in conventional circuit design approaches.
    Type: Grant
    Filed: May 10, 2020
    Date of Patent: August 31, 2021
    Inventors: Zhanming Li, Yue Fu, Yan-Fei Liu
  • Patent number: 11011420
    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hongqi Li, Anurag Jindal, Jin Lu, Shyam Ramalingam
  • Patent number: 11004823
    Abstract: A chip assembly includes a carrier and a metal grid array having an opening. The metal grid array is attached to the carrier by an attachment material. The metal grid array and the carrier define a cavity which is formed by the opening and the carrier. The chip assembly further includes an electronic chip mounted in the cavity.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies AG
    Inventors: Alexander Heinrich, Frank Daeche
  • Patent number: 10985349
    Abstract: The present disclosure provides a hot-pressing buffer, a display device, a hot-pressing process, and a method for reducing the X-line bright lines. The hot-pressing buffer includes: a thermally conductive material layer including a non-particulate thermally conductive material made of a non-particulate thermally conductive material; and a buffer material layer wrapped around an outer surface of the non-particulate thermally conductive material layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 20, 2021
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiehong Zhou, Hengfei Shi, Ke Cao
  • Patent number: 10950672
    Abstract: The present disclosure provides a flexible display device, a display apparatus, and a method for manufacturing the flexible display device. The flexible display device comprises a flexible display panel, a hardened layer, and an integrated circuit layer with bumps. A front surface of the flexible display panel is provided with a circuit bonding region. The flexible display panel comprises a first flexible substrate. The hardened layer is on the first flexible substrate. The hardened layer is at a position corresponding to the circuit bonding region. The integrated circuit layer is bonded to the circuit bonding region by the bumps.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunyan Xie, Jianwei Li, Liqiang Chen, Song Zhang
  • Patent number: 10943842
    Abstract: A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Mark E. Tuttle
  • Patent number: 10940676
    Abstract: The present disclosure relates to an anisotropic conductive film, a display device and a reworking method thereof. The anisotropic conductive film comprises: a first resin layer having positively photosensitive characteristics and conductive particles distributed in the first resin layer. Since the first resin layer has positively photosensitive characteristics, it can be decomposed after the exposure process. In this case, when failures occur in the binding of the display panel with the external circuit by the anisotropic conductive film, the first resin layer in the anisotropic conductive film can be decomposed by performing an exposure process on the anisotropic conductive film, so as to separate the external circuit from the display panel for reworking of the display panel. In this way, no heating process is needed, which not only simplifies the reworking procedure, but also is suitable for the reworking of a flexible display panel.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: March 9, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hong Li
  • Patent number: 10930601
    Abstract: A fan-out wafer level package includes: (1) a flexible substrate; (2) a semiconductor component embedded in the flexible substrate, the semiconductor component including an active surface that is exposed from the flexible substrate, the semiconductor component including a bonding pad adjacent to the active surface; (3) a stress buffer layer disposed over the flexible substrate and the semiconductor component, the stress buffer layer defining an opening exposing the bonding pad of the semiconductor component; and (4) an interconnect disposed over the stress buffer layer and including a portion extending into the opening of the stress buffer layer to electrically connect to the bonding pad of the semiconductor component.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 23, 2021
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Subramanian S. Iyer, Takafumi Fukushima, Adeel A. Bajwa
  • Patent number: 10923438
    Abstract: A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
  • Patent number: 10879205
    Abstract: A method of manufacturing a semiconductor device includes: applying a bonding resin composition on a semiconductor chip supporting member, the bonding resin composition containing a thermosetting resin and silver microparticles having an average particle size of 10 to 200 nm, the silver microparticles having a protective layer made of an organic compound on surfaces thereof; a semi-sintering step of heating the applied bonding resin composition at a temperature that is lower than a reaction starting temperature of the thermosetting resin and is equal to or more than 50° C. to bring the silver microparticles into a semi-sintered state; and a bonding step including: placing a semiconductor chip on the bonding resin composition containing the silver microparticles in a semi-sintered state, heating at a temperature higher than the reaction starting temperature of the thermosetting resin in a pressure-free state, and bonding the semiconductor chip to the semiconductor chip supporting member.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 29, 2020
    Assignee: KYOCERA CORPORATION
    Inventor: Masakazu Fujiwara
  • Patent number: 10861792
    Abstract: Methods and apparatus for an integrated circuit having with a frontside metal layer on the frontside of the substrate and a backside metal layer on the backside of the substrate. The backside metal layer is deposited onto the backside of the substrate and into the via such that a portion of the backside metal layer is connected to a portion of the frontside metal layer. A diffusion barrier layer is deposited on the backside metal layer located in the via.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: December 8, 2020
    Assignee: Raytheon Company
    Inventor: Paul J. Duval
  • Patent number: 10840206
    Abstract: A method of manufacturing a semiconductor device includes: applying a bonding resin composition on a semiconductor chip supporting member, the bonding resin composition containing a thermosetting resin and silver microparticles having an average particle size of 10 to 200 nm, the silver microparticles having a protective layer made of an organic compound on surfaces thereof; a semi-sintering step of heating the applied bonding resin composition at a temperature that is lower than a reaction starting temperature of the thermosetting resin and is equal to or more than 50° C. to bring the silver microparticles into a semi-sintered state; and a bonding step including: placing a semiconductor chip on the bonding resin composition containing the silver microparticles in a semi-sintered state, heating at a temperature higher than the reaction starting temperature of the thermosetting resin in a pressure-free state, and bonding the semiconductor chip to the semiconductor chip supporting member.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: November 17, 2020
    Assignee: KYOCERA CORPORATION
    Inventor: Masakazu Fujiwara
  • Patent number: 10784188
    Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rongwei Zhang, Vikas Gupta
  • Patent number: 10665524
    Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kamal K. Sikka, Krishna R. Tunga
  • Patent number: 10622275
    Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kamal K. Sikka, Krishna R. Tunga
  • Patent number: 10615140
    Abstract: A semiconductor device according to the present invention includes a resist provided so as to have an opening on a metal pattern, the resist having a protrusion part protruding into the opening, and the semiconductor device further includes a semiconductor element having an outside dimension smaller than an outside dimension of the opening excluding the protrusion, and solder provided inside the opening to join the metal pattern and the semiconductor element, wherein the protrusion part of the resist includes a plurality of protrusions that overlap with the semiconductor element in a plan view and regulate a thickness direction of the semiconductor element.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takami Otsuki
  • Patent number: 10580710
    Abstract: A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Mark E. Tuttle
  • Patent number: 10529869
    Abstract: A connecting member includes a first part arranged between a first region of an electronic device and a board and a second part arranged between a second region of the electronic device and the board, a distance from an edge to the first part is longer than a distance from a center to the first part, and a distance from the edge to the second part is shorter than a distance from the center to the second part, a space is provided between the electronic device and the board and between the first part and the second part, and, in the board, a through hole communicating with the space is provided not to overlap with the center of the electronic device.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 7, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Taiki Shitamichi, Takashi Miyake
  • Patent number: 10510578
    Abstract: A protective film forming film 1 is provided in which the product of the breaking stress (MPa) measured at a measurement temperature of 0° C. and the breaking strain (unit: %) measured at a measurement temperature of 0° C. in at least one of the protective film forming film 1 and a protective film formed from the protective film forming film 1 is in a range of 1 MPa·% to 250 MPa·%. According to such a protective film forming film 1, the protective film forming film 1 or the protective film formed from the protective film forming film 1 can be suitably divided in an expanding process performed on a workpiece when the workpiece is divided to obtain a work product.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: December 17, 2019
    Assignee: Lintec Corporation
    Inventors: Naoya Saiki, Daisuke Yamamoto, Hiroyuki Yoneyama, Youichi Inao
  • Patent number: 10461111
    Abstract: There is provided a solid state imaging apparatus, including: an optical film layer on which a solid state image sensor is mounted; a multifunctional chip laminated at a periphery of the solid state image sensor in the optical film layer being electrically contacted with the optical film layer via a metal body; a sealing resin layer for sealing the periphery where the multifunctional chip is laminated on the optical film layer; and a concave structure for blocking a flow of the sealing resin in a liquid state when the sealing resin layer is formed at the periphery of the sealing resin layer. Also, a method of producing the solid state imaging apparatus is also provided.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 29, 2019
    Assignee: Sony Corporation
    Inventor: Masataka Maehara
  • Patent number: 10431534
    Abstract: Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: October 1, 2019
    Assignee: NXP USA, Inc.
    Inventors: Nishant Lakhera, Gilles Montoriol, Trung Duong, Akhilesh Kumar Singh, Navas Khan Oratti Kalandar
  • Patent number: 10428257
    Abstract: A thermal interface material includes at least one polymer, at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of: nitrogen containing complexing agents, phosphorus containing complexing agents, and hydroxyl carboxylic acid based complexing agents.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: October 1, 2019
    Assignee: Honeywell International Inc.
    Inventors: Ya Qun Liu, Liang Zeng, Hui Wang, Bright Zhang, Hong Min Huang
  • Patent number: 10388742
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region in the nitride semiconductor layer and the insulating layer, has a higher electric resistivity than the first region, and includes carbon (C).
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 20, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10366944
    Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rongwei Zhang, Vikas Gupta
  • Patent number: 10347589
    Abstract: An assembly (101) comprising a semiconductor device (110) with solderable bumps (112); a substrate (120) with a layer (130) of a first insulating compound and an underlying metal layer (140) patterned in contact pads (141) and connecting traces (142), the insulating layer having openings (132) to expose the surface (142a) and sidewalls (142b) of underlying traces; the device bumps soldered onto the contact pads, establishing a gap (150) between device and top insulating layer; and a second insulating compound (160) cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaimal M. Williamson, Nima Shahidi, Jose Carlos Arroyo
  • Patent number: 10314177
    Abstract: A component mounting apparatus is configured to mount a component on a substrate. The substrate includes a lower side substrate member, an upper side substrate member provided on an upper surface of the lower side substrate member, a lower side mark provided on the lower side substrate member, and an upper side mark provided on an upper surface of the upper side substrate member. The apparatus includes an upward facing camera configured to image the lower side mark from below the lower side substrate member, a data storage configured to store relative positional relationship data indicating a predetermined relative positional relationship between the lower side mark and the upper side mark, and a component mounting unit configured to mount the component on the upper surface of the upper side substrate member based on the data and information obtained through imaging the lower side mark imaged by the upward facing camera.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: June 4, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shingo Yamada, Takafumi Tsujisawa
  • Patent number: 10192769
    Abstract: A thermosetting adhesive sheet and a method for manufacturing a semiconductor device capable of reducing warping of a semiconductor wafer are provided. The thermosetting adhesive sheet is to be applied to a grinding-side surface of a semiconductor wafer and cured before dicing and includes a polymer containing an elastomer, a (meth) acrylate containing more than 95% wt of a polyfunctional (meth) acrylate with respect to total (meth)acrylate content, an organic peroxide having a one-minute half-life temperature of 130° C. or lower, and a transparent filler. Thereby, the thermosetting adhesive sheet significantly shrinks and generates a stress opposing a warp direction of the semiconductor wafer, enabling the semiconductor wafer to be maintained in a flat state.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 29, 2019
    Assignee: DEXERIALS CORPORATION
    Inventor: Daichi Mori
  • Patent number: 10155894
    Abstract: A thermal interface material includes at least one polymer, at least one thermally conductive filler; and at least one ion scavenger. In some embodiments, the ion scavenger is a complexing agent selected from the group consisting of: nitrogen containing complexing agents, phosphorus containing complexing agents, and hydroxyl carboxylic acid based complexing agents.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: December 18, 2018
    Assignee: Honeywell International Inc.
    Inventors: Ya Qun Liu, Liang Zeng, Hui Wang, Bright Zhang, Hong Min Huang
  • Patent number: 9946158
    Abstract: Disclosed herein is a composition for forming a resist underlayer film used as an underlayer of a resist for nanoimprint in nanoimprint lithography of a pattern forming process by heat-baking, light-irradiation, or a combination thereof to form the resist underlayer film. The composition includes a silicon atom-containing polymerizable compound (A), a polymerization initiator (B), and a solvent (C). The polymerizable compound (A) may contain silicon atoms in a content of 5 to 45% by mass. The polymerizable compound (A) may be a polymerizable compound having at least one cation polymerizable reactive group, a polymerizable compound having at least one radical polymerizable reactive group, or a combination thereof, and the polymerization initiator (B) may be a photopolymerization initiator.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: April 17, 2018
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Satoshi Takei, Tomoya Ohashi
  • Patent number: 9859247
    Abstract: A method is provided for assembly of a micro-electronic component, in which a conductive die bonding material is used. This material includes a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer A laser beam is impinged on the dynamic release layer, adjacent to the die bonding material layer, in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated, to cover a selected part of the pad structure with a transferred conductive die bonding material. The laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly, adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: January 2, 2018
    Assignees: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO, IMEC vzw
    Inventors: Edsger Constant Pieter Smits, Sandeep Menon Perinchery, Jeroen Van den Brand, Rajesh Mandamparambil, Harmannus Franciscus Maria Schoo
  • Patent number: 9728458
    Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 8, 2017
    Assignee: Soitec
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 9666513
    Abstract: An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 30, 2017
    Assignee: Invensas Corporation
    Inventors: Ashok S. Prabhu, Rajesh Katkar, Sean Moran
  • Patent number: 9659917
    Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: May 23, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Michel Koopmans
  • Patent number: 9634059
    Abstract: A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 25, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jui Yi Chiu
  • Patent number: 9614168
    Abstract: A display may have an array of organic light-emitting diodes that form an active area on a flexible substrate. Metal traces may extend between the active area and an inactive area of the flexible substrate. Display driver circuitry such as a display driver integrated circuit may be coupled to the inactive area. The metal traces may extend across a bend region in the flexible substrate. The flexible substrate may be bent in the bend region. The flexible substrate may be made of a thin flexible material to reduce metal trace bending stress. A coating layer in the bend region may be provided with an enhanced elasticity to allow its thickness to be reduced. The flexible substrate may be bent on itself and secured within an electronic device without using a mandrel.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: April 4, 2017
    Assignee: Apple Inc.
    Inventors: Zhen Zhang, Yi Tao, Paul S. Drzaic, Joshua G. Wurzel
  • Patent number: 9601365
    Abstract: A peeling device separates a superposed substrate, in which a target substrate and a support substrate are joined to each other with an adhesive, into the target substrate and the support substrate. The peeling device includes a holding unit configured to hold the superposed substrate, and a plurality of position adjustment units movable forward and backward with respect to a side surface of the superposed substrate held in the holding unit, and the position adjustment unit configured to perform a position adjustment of the superposed substrate by contacting the side surface of the superposed substrate.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 21, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masaru Honda, Ryoichi Sakamoto
  • Patent number: 9587075
    Abstract: The invention provides an addition-curable silicone composition which provides a cured product having good performance at a low temperature and excellent resistance to a temperature change, and to provide a semiconductor device having a high reliability, whose semiconductor element is encapsulated with the cured product. The invention provides an addition-curable silicone composition comprising (A) a branched organopolysiloxane having at least two alkenyl groups and represented by the formula (1) with a short branch consisting of 1 to 4 siloxane units, (B) an organohydrogenpolysiloxane having at least two hydrosilyl groups, in an amount such that a ratio of the number of the hydrosilyl groups in component (B) to the number of the alkenyl groups in component (A) is 0.4 to 4, and (C) a hydrosilylation catalyst in a catalytic amount. The invention also provides a semiconductor device provided with a cured product obtained by curing the condensation-curable silicone composition.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: March 7, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Takayuki Kusunoki, Yuusuke Takamizawa, Tsutomu Kashiwagi
  • Patent number: 9589882
    Abstract: The semiconductor device includes a wiring substrate having a plurality of ball lands formed on a lower surface of a core layer, a solder resist film covering the lower surface of the core layer, a via conductor layer penetrating the core layer and connected to the ball lands, and an upper surface wiring formed on the upper surface of the core layer, the upper surface wiring having one end formed as a bonding land and the other end connected to the via conductor layer. The semiconductor device further includes a semiconductor chip arranged on the wiring substrate, a solder ball connected to the ball lands. The solder resist film has an eliminating portion that exposes the lower surface of the core layer, and the upper surface wiring has a thin-wire portion and a thick-wire portion, and when seen in a plan view, the thick-wire portion overlaps the eliminating portion.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Hiromitsu Takeda
  • Patent number: 9583453
    Abstract: Sintering die-attach materials provide a lead-free solution for semiconductor packages with superior electrical, thermal and mechanical performance to prior art alternatives. Wafer-applied sintering materials form a metallurgical bond to both semiconductor die and adherends as well as throughout the die-attach joint and do not remelt at the original process temperature. Application to either one or both sides of the wafer, as well as paste a film application are disclosed.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: February 28, 2017
    Assignee: Ormet Circuits, Inc.
    Inventors: Catherine Shearer, Michael C Matthews, Peter A Matturi, Eunsook Barber, Richard Weaver
  • Patent number: 9508622
    Abstract: A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: November 29, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Leo M. Higgins, III
  • Patent number: 9502271
    Abstract: Flexible structures and method of providing a flexible structure are disclosed. In some embodiments, a method of providing a flexible structure includes: providing a flex substrate having a device bonded to a first side of the flex substrate; and attaching a rigid layer to a second side of the flex substrate opposite the first side using an adhesive layer.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shih Ting Lin, Jing-Cheng Lin, Shang-Yun Hou, Szu Wei Lu