Wire Contact, Lead, Or Bond Patents (Class 257/784)
  • Patent number: 11444058
    Abstract: A package structure includes a first chip and a second chip. The first chip is connected to a pair of first signal lines and a plurality of first power lines. The second chip is connected to a pair of second signal lines and a plurality of second power lines. The first chip and the second chip belong to a common wafer. A separated street is between the first chip and the second chip.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: September 13, 2022
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chien-Chen Ko, Teng-Jui Yu, Wei-Kang Tsai
  • Patent number: 11444006
    Abstract: An electronic component includes: a first lead frame; a second lead frame that is provided on the first lead frame; a first electronic component that is provided between the first lead frame and the second lead frame; a connection member that is provided between the first lead frame and the second lead frame; and an insulating resin that is filled between the first lead frame and the second lead frame so as to cover the first electronic component and the connection member. A first oxide film is provided on a surface of the first lead frame. A second oxide film is provided on a surface of the second lead frame. The first lead frame and the second lead frame are electrically connected to each other by the connection member.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: September 13, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yukinori Hatori, Yasushi Araki, Akinobu Inoue, Tsukasa Nakanishi
  • Patent number: 11439847
    Abstract: Systems and methods for treating a lung of a patient. One embodiment of a method comprises positioning a leadless marker in the lung of the patient relative to the target, and collecting position data of the marker. This method further comprises determining the location of the marker in an external reference frame outside of the patient based on the collected position data, and providing an objective output in the external reference frame that is responsive to movement of the marker. The objective output is provided at a frequency (i.e., periodicity) that results in a clinically acceptable tracking error. In addition, the objective output can also be provided at least substantially contemporaneously with collecting the position data used to determine the location of the marker.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 13, 2022
    Assignee: VARIAN MEDICAL SYSTEMS, INC.
    Inventors: Edward J. Vertatschitsch, Steven C. Dimmer, Timothy P. Mate, Eric Meier, Keith Seiler, J. Nelson Wright
  • Patent number: 11443776
    Abstract: An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system on chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to a parallel memory interface through parallel signal traces arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing is between the parallel signal traces for a majority portion of the parallel signal traces.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 13, 2022
    Assignee: QUALCOMM Incorporated
    Inventor: Sunil Gupta
  • Patent number: 11437192
    Abstract: A multilayered capacitor includes a capacitor body including a plurality of dielectric layers and a plurality of internal electrodes; and external electrodes disposed on both end portions of the capacitor body and connected to exposed portions of the internal electrodes, respectively. Each of the external electrodes includes a conductive layer formed on the capacitor body and connected to the internal electrodes; an inner plated layer including nickel (Ni) and phosphorus (P), and covering the conductive layer; and an outer plated layer including palladium (Pd) and phosphorus (P), and covering the inner plated layer.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Mi Geum Kim, Byeong Cheol Moon, Kun Hoi Koo, Jung Min Kim
  • Patent number: 11437342
    Abstract: A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 6, 2022
    Assignee: SK hynix Inc.
    Inventor: Chan Sun Lee
  • Patent number: 11437295
    Abstract: A semiconductor package includes a substrate including an antenna; a heating element disposed on a first surface of the substrate and connected to the antenna; a heat radiating part coupled to the heating element; and a signal transfer part disposed on the first surface of the substrate and configured to electrically connect the substrate to a main substrate. The heat radiating part may include a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 6, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Jung Hyun Lim, Seung Goo Jang, Eun Kyoung Kim, Se Min Jin
  • Patent number: 11430758
    Abstract: A semiconductor device includes a solder supporting material above a substrate. The semiconductor device also includes a solder on the solder supporting material. The semiconductor device further includes selective laser annealed or laser ablated portions of the solder and underlying solder supporting material to form a semiconductor device having 3D features.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 30, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Simon Joshua Jacobs
  • Patent number: 11417631
    Abstract: A semiconductor package includes: a first semiconductor package including: a first frame having a first through portion, a first semiconductor chip in the first through portion and having a first surface on which a first connection pad is disposed and a second surface on which a second connection pad is disposed, and a through via connected to the second connection pad, a first connection structure on the first surface and including a first redistribution layer, and a backside redistribution layer on the second surface; and a second semiconductor package on the first semiconductor package and including: a second connection structure including a second redistribution layer, a second frame on the second connection structure and having a second through portion, and a second semiconductor chip in a second through portion and having a third surface on which a third connection pad is disposed.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: August 16, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yun Tae Lee, Hyung Joon Kim, Han Kim
  • Patent number: 11404356
    Abstract: An electronic device includes an electronic component provided with a first electrode pad, a die pad including an obverse surface facing in a first direction with the electronic component mounted on the obverse surface, a first lead, a second lead, and a first connection member electrically connecting the first electrode pad and the first lead to each other. The first lead and the second lead are disposed, as viewed in the first direction, on a same side of the die pad in a second direction perpendicular to the first direction. The first lead includes a first pad portion and a first extended portion. The first connection member is bonded to the first pad portion. The first extended portion extends from the first pad portion up to a position located between the die pad and the second lead as viewed in the first direction.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 2, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Katsutoki Shirai, Yoshio Higashida
  • Patent number: 11404357
    Abstract: A dielectric film is disposed on a semiconductor substrate, and a conductor including a bent section is arranged between the semiconductor substrate and the dielectric film. A pad is disposed on the dielectric film. The pad is covered with a protective film. The protective film has an opening through which an upper surface of the pad is exposed. The bent section in the conductor and the pad overlap each other as seen in plan view, and an inside corner and an outside corner in the bent section are chamfered.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: August 2, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Hiroaki Tokuya, Kazuya Kobayashi, Yuichi Sano
  • Patent number: 11398455
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewall and the device stack, and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 26, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee
  • Patent number: 11393795
    Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: July 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongjin Park, Sunghawn Bae, Won Choi
  • Patent number: 11380601
    Abstract: A semiconductor chip is mounted on a substrate in a face-down manner. A metal film is arranged on a back surface of the semiconductor chip facing an opposite side from the substrate away from an edge of the back surface. A sealing resin layer seals the semiconductor chip with a part of the metal film being exposed from the sealing resin layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Yuichi Sano, Toshihiro Tada
  • Patent number: 11342309
    Abstract: In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hang Tung, Kuo-Chung Yee
  • Patent number: 11334703
    Abstract: Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes initializing a layout for fabricating an integrated circuit. A plurality of fill cells is inserted into the layout. The plurality of fill cells includes a plurality of fill line shapes that correspond to conductive lines of the integrated circuit. Thereafter, a design is inserted into the layout that includes a plurality of functional shapes. A conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflict with the plurality functional shapes are removed. The layout that includes the plurality of fill cells and the design is provided for fabricating the integrated circuit.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Cheng Yeh, Yen-Sen Wang, Ming-Yi Lin
  • Patent number: 11302658
    Abstract: The present disclosure provides a fan-out antenna packaging structure for a semiconductor chip and its fabricating method. The structure is a stacked-up two sets of metal connecting columns and antenna metal patterns arranged in two sequential layers of packaging materials sealing the chip. The two sets of metal interconnecting structures in the two layers of packaging materials may have different thicknesses. In some applications there can be more than two sets of the stacked-up antenna structures, fabricated around the chip at one side of a rewiring layer. The chip is interconnected to external metal bumps on the other side of the rewiring layer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: April 12, 2022
    Assignee: SJ SEMICONDUCTOR(JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu
  • Patent number: 11239132
    Abstract: A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 1, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Salamone, Cristiano Gianluca Stella
  • Patent number: 11231606
    Abstract: Embodiments of the present invention provide a conductive substrate, a manufacturing method thereof and a display device. The conductive substrate includes a base substrate and a first conductive layer and a second conductive layer disposed on the base substrate, wherein the first conductive layer and the second conductive layer contact with each other, the first conductive layer is configured to be electrically connected with separated parts after the second conductive layer is fractured, and the first conductive layer includes a composite material layer or a nanowire conductive network layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 25, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongfei Cheng, Yuxin Zhang
  • Patent number: 11227855
    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang-woo Lee, Un-byoung Kang, Ji-hwang Kim, Jong-bo Shim, Young-kun Jee
  • Patent number: 11195783
    Abstract: A semiconductor device includes a semiconductor element made up of a semiconductor substrate, an element electrode formed on the substrate, and a wiring layer electrically connected to the element electrode. The semiconductor device further includes a lead frame supporting the semiconductor element, a first conductive member electrically connecting the semiconductor element and the lead frame, a second conductive member overlapping with the semiconductor element as seen in plan view, and a sealing resin covering the semiconductor element, a part of the lead frame, and the first and second conductive member. The wiring layer includes a first pad portion and a second pad portion. The second conductive member has a first connecting portion bonded to the first pad portion and a second connecting portion bonded to the second pad portion.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: December 7, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Yoshio Higashida, Katsutoki Shirai
  • Patent number: 11171126
    Abstract: Systems and devices for enabling the use of SIP subsystems to make a configurable system having a unique interconnecting scheme creates appropriate connections between the SIP components and/or subsystems such that desired characteristics and features for the configurable system are provided.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: November 9, 2021
    Assignee: OCTAVO SYSTEMS LLC
    Inventors: Masood Murtuza, Gene Alan Frantz, Neeraj Kumar Reddy Dantu
  • Patent number: 11158616
    Abstract: A semiconductor package includes a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer. A frame is disposed on the connection structure and has one or more through-holes, a semiconductor chip and a passive component are disposed on the connection structure in the one or more through-holes of the frame, a first encapsulant covers at least a portion of the passive component, and a second encapsulant covers at least a portion of the semiconductor chip. An upper surface of the second encapsulant is positioned at a level equal to or lower than an upper surface of the first encapsulant.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: October 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Minsek Jang
  • Patent number: 11152327
    Abstract: A semiconductor device includes a semiconductor element, a terminal electrode, and internal wiring. The semiconductor element is housed in a case. The terminal electrode is provided electrically connectable to an outside of the case. The internal wiring is provided in the case and electrically connects the semiconductor element and the terminal electrode. The internal wiring includes a fuse portion provided at a part of the internal wiring and configured to be melted by an overcurrent. The fuse portion includes a plurality of metal wires which are a group of parallel wires. Of the plurality of metal wires, a first metal wire is higher in resistance value than a second metal wire laid on an outer side relative to the first metal wire.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: October 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshitaka Otsubo, Shun Tonooka, Tetsuya Matsuda
  • Patent number: 11152344
    Abstract: An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Mirng-Ji Lii, Chien-Hsun Lee, Jiun Yi Wu
  • Patent number: 11139153
    Abstract: The MCP assembly of this embodiment is formed at least of a conductive upper support member, an MCP unit, an output electrode, a flexible sheet electrode, and a conductive lower support member as a structure for improving handleability of a flexible sheet electrode having a mesh area. The flexible sheet electrode includes the mesh area provided with plural openings. The flexible sheet electrode and the lower support member are physically and electrically connected to each other, and the flexible sheet electrode is sandwiched between the upper support member and the lower support member. As a result, even if the flexible sheet electrode becomes thin as an opening ratio of the mesh area increases, potential is set while the flexible sheet electrode is firmly held in the MCP assembly.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 5, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventor: Masahiro Hayashi
  • Patent number: 11129277
    Abstract: An elongate, three dimensional, conductive, micro lattice truss structure has parallel layers of resilient strands so that the truss structure maintains structural integrity during end-to-end compression which shortens its uncompressed length. The resiliency of the micro lattice truss structure enables the truss structure to return to substantially its uncompressed length when the compression is removed. The truss structure is adapted to provide a resilient electrical connection between two opposing conductive areas when the distal ends of the truss structure engage and are compressed between the two areas.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 21, 2021
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Matthew J. Pirih, Steven J. Mass, Andrew Yurko
  • Patent number: 11114599
    Abstract: Electronic devices including a layer of polymeric material and solid semiconductor dies partially embedded in the layer are provided. The dies have first ends projecting away from the first major surface of the layer. The electronic devices can be formed by sinking the first ends of the dies into a major surface of a liner. A flowable polymeric material is filled into the space between the dies and solidified to form the layer of polymeric material. The first ends of the dies are exposed by delaminating the liner from the first ends of the dies. Electrical conductors are provided on the layer to connect the first ends of the dies.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: September 7, 2021
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Ankit Mahajan, Mikhail L. Pekurovsky, Matthew S. Stay, Shawn C. Dodds, Thomas J. Metzler, Matthew R. D. Smith, Saagar A. Shah, Jae Yong Lee, James F. Poch, Roger W. Barton
  • Patent number: 11094652
    Abstract: A radio frequency integrated circuit includes a transmitter integrated on a die, the transmitter circuit being controlled by a first logical signal and configured to receive a to-be-transmitted signal and output a first voltage at a first internal node; a receiver integrated on the die. The receiver circuit is controlled by the first logical signal and a second logical signal and configured to output a receive signal. A first pad, a second pad, and a first inductor integrated on the die, the first pad being connected to the first internal node, the second pad being connected to the second internal node, and the first inductor being placed across the first internal node and the second internal node.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: August 17, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Poh Boon Leong, Chia-Liang (Leon) Lin
  • Patent number: 11056432
    Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuek Jae Lee, Ji Hoon Kim, Tae Hun Kim, Ji Seok Hong, Ji Hwan Hwang
  • Patent number: 11038093
    Abstract: A configuration of wirebonds for reducing cross-talk in a quantum computing chip includes a first wirebond coupling a first conductor of a quantum computing circuit with a first conductor of an external circuit. The embodiment further includes in the configuration a second wirebond coupling a second conductor of the quantum computing circuit with a second conductor of the external circuit, wherein the first wirebond and the second wirebond are separated by a first vertical distance in a direction of a length of the first conductor.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dongbing Shao, Markus Brink
  • Patent number: 11004778
    Abstract: A ball grid array (BGA) package for an integrated circuit device includes an integrated circuit device having a plurality of terminals, and two largest dimensions that define a major plane. A package substrate material encloses the integrated circuit device, and is formed, in a plane parallel to the major plane, into a polygon having at least five sides. An array of contacts on an exterior surface of the package substrate material is electrically coupled to the plurality of terminals. Contacts in the array of contacts are distributed in a pattern of contact positions, and the center of each contact position may be separated from the center of each nearest other position by a separation distance that is identical throughout the pattern. Each position may be occupied by a contact, or positions in a sub-pattern may lack a contact and may be available for insertion of at least one via.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Dan Azeroual, William Bruce Weiser
  • Patent number: 10978591
    Abstract: A nanowire semiconductor device having a high-quality epitaxial layer. The semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 13, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 10978419
    Abstract: A semiconductor package includes a substrate and a semiconductor chip, a lower conductive layer and an upper conductive layer sequentially stacked on the substrate. The substrate includes first and second connection pads formed thereon. The semiconductor chip includes third and fourth connection pads formed thereon. The upper conductive layer is connected to the first and the third connection pads via a first and a second wiring, and the lower conductive layer is connected to the second and the fourth connection pads via a third and a fourth wiring.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: April 13, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 10916522
    Abstract: A method for manufacturing a semiconductor device includes: a first bonding process including bonding, at a first bonding point, a tip of a wire held by a capillary; a first lifting process including moving the capillary upward; a first reverse process including moving the capillary in a direction that includes a component in a first direction that is from a second bonding point toward the first bonding point; a second lifting process including moving the capillary upward; a second reverse process including moving the capillary in the first direction; a third lifting process including moving the capillary upward; a forward process including moving the capillary toward the second bonding point; and a second bonding process including bonding the wire at the second bonding point. A movement distance of the capillary in the first lifting process is not less than a movement distance of the capillary in the second lifting process.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: February 9, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Daisuke Fukamachi
  • Patent number: 10895736
    Abstract: Methods and apparatus for modulating light thorough a transparent laminate structure. The transparent laminate structure includes at least one soft dielectric layer and at least one stiff dielectric layer having a stiffness greater than the stiffness of the at least one soft dielectric layer. The transparent laminate structure further comprises a plurality of stiff conductive elements formed on a surface of the at least one soft dielectric layer that, in the presence of an electric field, compress the at least one soft dielectric layer to alter a morphology of the surface of the at least one soft dielectric layer on which the plurality of stiff conductive elements are formed. Light incident on the surface of the at least one soft dielectric layer is scattered by the undulating morphology of the surface, thereby reducing the transmission of light through the transparent laminate structure.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: January 19, 2021
    Assignee: President and Fellows of Harvard College
    Inventors: Samuel Shian, David Clarke
  • Patent number: 10854575
    Abstract: The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that a size of electronic package structure can be reduced. The three-dimensional package structure comprises a first electronic component, a plurality of second electronic components and a plurality of conductive patterns. The first electronic component has a top surface and a bottom surface. The plurality of second electronic components are disposed over the top surface of the first electronic component. The plurality of conductive patterns are disposed over the plurality of second electronic components to electrically connect the plurality of second electronic components and the first electronic component.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: December 1, 2020
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Ming-Chia Wu, Shao Wei Lu
  • Patent number: 10825753
    Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device including first and second semiconductor dies arranged on respective and first and second carriers, the first and second semiconductor dies each comprising a first contact and a second contact arranged on a top major surface of the respective semiconductor dies and a third contact arranged on a bottom major surface the respective semiconductor dies; first and second die connection portions, arranged on the respective first and second carriers, connected to the third contacts of the respective first and second semiconductor dies; and a first contact connection member, extending from the first contact of the first semiconductor die to the die connection portion of second carrier, electrical connection of the first contact of the first semiconductor die to the third contact of the second semiconductor die.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: November 3, 2020
    Assignee: Nexperia B.V.
    Inventors: Adam R. Brown, Ricardo L. Yandoc
  • Patent number: 10804186
    Abstract: Provided are a semiconductor module capable of further increasing an effect of canceling out a parasitic inductance by a current and a power converter including the semiconductor module. The semiconductor module includes a first leadframe, a second leadframe, a third leadframe, an insulating material, a first semiconductor element, and a second semiconductor element. The first leadframe is a plate-shaped wiring path to which a first potential is applied. The second leadframe is a plate-shaped wiring path including an output terminal. The third leadframe is a plate-shaped wiring path to which a second potential is applied. The first semiconductor element is directly joined to the first leadframe with a joint material therebetween, and the second semiconductor element is directly joined to the second leadframe with a joint material therebetween. The first leadframe and the second leadframe face each other with the insulating material therebetween.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 13, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shinya Yano, Yasushi Nakayama
  • Patent number: 10770400
    Abstract: A semiconductor module includes a substrate, two bare chips (semiconductor elements) mounted on the substrate, and a case fixed to the substrate. A conductor pattern and five signal patterns are provided for each bare chip on an upper surface of an insulating substrate. Signal electrodes and the signal patterns of the bare chips are connected to by conductive plates. An insulating member is provided on connecting portions of the conductive plates.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 8, 2020
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Naoki Kato, Shogo Mori, Harumitsu Sato, Hiroki Watanabe, Hiroshi Yuguchi, Yuri Otobe
  • Patent number: 10756165
    Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 25, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Kouki Yamamoto, Masatoshi Kamitani, Shingo Matsuda, Hiroshi Sugiyama, Kaname Motoyoshi, Masao Nakayama
  • Patent number: 10748877
    Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Philip G. Emma, Hillery C. Hunter, John U. Knickerbocker
  • Patent number: 10733351
    Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. In particular, the present embodiments allow for the automatic creation of WSPs by examining heights and placement orientations of instances, along with the width, spacing, and colors of instance pins and blockages. In these and other embodiments, techniques are provided for filling gaps between generated tracks, as well as for generating tracks to account for the possibility of flipped or mirrored instances.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: August 4, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gary Matsunami, Karun Sharma, Sandipan Ghosh, Yinnie Lee
  • Patent number: 10736250
    Abstract: A method of manufacturing a transparent flexible silver nanowire-based conducting film and a transparent flexible silver nanowire-based conducting film are provided. The method includes coating conductive nanowires, which shield and absorb electromagnetic interference, on a flexible substrate, sintering the conductive nanowires using a wet sintering process, and coating a polymer layer in which graphene flakes are dispersed on the flexible substrate with the conductive nanowires formed thereon.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: August 4, 2020
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sang Woo Kim, Jong Han Choi
  • Patent number: 10727208
    Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Zhicheng Ding, Bin Liu, Yong She, Aiping Tan, Li Deng
  • Patent number: 10685929
    Abstract: A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer disposed on the first insulating layer, first vias penetrating through the first insulating layer and electrically connecting the connection pads and the first redistribution layer to each other, and a first insulating film covering the first insulating layer and the first redistribution layer. The first insulating film includes a silicon based compound.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chang Hwa Park, Ga Young Yoo, Sang Ah Kim, Yu Rim Choi
  • Patent number: 10658325
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and his a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: May 19, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Patent number: 10658311
    Abstract: Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a plurality of conductive layers designed so as to be formed in a first region within a semiconductor chip, the density in which the plurality of conductive layers are disposed in the first region being at least a first threshold value and not more than a second threshold value, the first and second threshold values being less than a minimum density according to the design rules for ensuring that all of the plurality of conductive layers are formed in the first region; and a reader which provides an identification key by identifying if, among the plurality of conductive layers, a previously designated first conductive layer has been formed.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: May 19, 2020
    Assignee: ICTK Holdings Co., Ltd.
    Inventors: Byong Deok Choi, Dong Kyue Kim
  • Patent number: 10643970
    Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 5, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: David Auchere, Asma Hajji, Fabien Quercia, Jerome Lopez
  • Patent number: 10643931
    Abstract: A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base substrate and having an opening exposing a portion of the conductive pad; and a bump on the exposed portion of the conductive pad and on the insulating layer around the opening. The bump includes a plurality of concave portions corresponding to the opening and is arranged in a longitudinal direction of the bump.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 5, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung Hwa Ha, Jung Yun Jo, Byoung Yong Kim, Jeong Do Yang, Jeong Ho Hwang