Wire Contact, Lead, Or Bond Patents (Class 257/784)
  • Patent number: 10347577
    Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yuki Miura, Mieko Kojima
  • Patent number: 10332671
    Abstract: An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mario Francisco Velez, Niranjan Sunil Mudakatte, Changhan Hobie Yun, Daeik Daniel Kim, David Francis Berdy, Jonghae Kim, Yunfei Ma, Chengjie Zuo
  • Patent number: 10271421
    Abstract: Electrically-conductive wires are used to construct an EMI shield between inductors of an RF module that prevents, or at least reduces, EMI crosstalk between the inductors while maintaining high Q factors for the inductors. The EMI shield comprises at least a first set of electrically-conductive wires that at least partially surrounds and extends over at least a first inductor of a pair of inductors. Adjacent wires of the first set are spaced apart from one another by a predetermined distance selected to ensure that the EMI shield attenuates a frequency or frequency range of interest. First and second ends of each of the wires are connected to an electrical ground structure. A length of each wire in between the first and second ends of the respective wire extends above the first inductor and is spaced apart from the first inductor so as not to be in contact with the first inductor.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 23, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Bernhard Gebauer, Oliver Wiedenmann, Sarah Haney, Lueder Elbrecht, Deog-Soon Choi, Aaron Lee
  • Patent number: 10249764
    Abstract: A method for manufacturing a transistor with stable electric characteristics and little signal delay due to wiring resistance, used in a semiconductor device including an oxide semiconductor film. A semiconductor device including the transistor is provided. A high-performance display device including the transistor is provided.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10242965
    Abstract: A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication between the second semiconductor package and a host device occurs through the first semiconductor package.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: March 26, 2019
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Chin-Tien Chiu, Hem Takiar
  • Patent number: 10237974
    Abstract: A conductive nanowire film having a high aspect-ratio metal is described. The nanowire film is produced by inducing metal reduction in a concentrated surfactant solution containing metal precursor ions, a surfactant and a reducing agent. The metal nanostructures demonstrate utility in a great variety of applications.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: March 19, 2019
    Assignee: RAMOT AT TEL-AVIV UNIVERSITY LTD. ISRAELI COMPANY OF
    Inventors: Gil Markovich, Daniel Azulai, Olga Krichevski
  • Patent number: 10217832
    Abstract: A semiconductor device is provided that includes a semiconductor substrate; an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen; a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and an upper electrode provided above the insulating film. The barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yanzheng Zhang
  • Patent number: 10217859
    Abstract: A semiconductor device is provided that includes a semiconductor substrate; an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen; a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and an upper electrode provided above the insulating film. The barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yanzheng Zhang
  • Patent number: 10192796
    Abstract: A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 29, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen
  • Patent number: 10115699
    Abstract: A manufacturing method for a wire bonding structure of the present invention includes a step of preparing a wire made of Cu and a step of joining the wire to a first joining target formed on an electronic device. Before the joining step, the wire has an outer circumferential surface and a withdrawn surface. The withdrawn surface is withdrawn toward a central axis of the wire from the outer circumferential surface. In the joining step, ultrasonic vibration is applied to the wire in a state in which the withdrawn surface is pressed against the first joining target.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 30, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Kazuya Ikoma
  • Patent number: 10109574
    Abstract: A method and structure for improving high voltage breakdown reliability of a microelectronic device, e.g., a galvanic digital isolator, involves providing an abatement structure around metal plate corners of a high voltage isolation capacitor to ameliorate the effects of an electric field formed thereat during operation of the device due to dielectric discontinuity.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: October 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. West, Byron Lovell Williams, David Leonard Larkin, Weidong Tian
  • Patent number: 10103120
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 16, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Patent number: 10083890
    Abstract: Aligned high quality boron nitride nanotubes (BNNTs) can be incorporated into groups and bundles and placed in electronic and electrical components (ECs) to enhance the heat removal and diminish the heat production. High quality BNNTs are excellent conductors of heat at the nano scale. High quality BNNTs are electrically insulating and can reduce dielectric heating. The BNNTs composite well with a broad range of ceramics, metals, polymers, epoxies and thermal greases thereby providing great flexibility in the design of ECs with improved thermal management. Controlling the alignment of the BNNTs both with respect to each other and the surfaces and layers of the ECs provides the preferred embodiments for ECs.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: September 25, 2018
    Assignee: BNNT, LLC
    Inventors: R. Roy Whitney, Kevin C. Jordan, Michael W. Smith, Jonathan C. Stevens
  • Patent number: 10076023
    Abstract: A compartment EMI shield for use inside of a system module package is provided that comprises at least a first set of electrically-conductive wires that surrounds and extends over circuitry of the module package. Adjacent wires of the first set are spaced apart from one another by a predetermined distance selected to ensure that the compartment EMI shield attenuates a frequency or frequency range of interest. First and second ends of each of the wires are connected to an electrical ground structure. A length of each wire that is located in between the first and second ends of the respective wire extends above the circuitry and is spaced apart from the components of the circuitry so as not to be in contact with the components of the circuitry.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 11, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Deog-Soon Choi, Chang-Yul Cheon, Sang-Hwa Jung, Sung-Phyo Lim, Aaron Lee
  • Patent number: 10074616
    Abstract: In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, the semiconductor die having a first surface and a thickness t1. A second dielectric layer is arranged on a first surface of the first dielectric layer, the second dielectric layer including a photodefinable polymer composition, and a conductive layer is arranged on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The conductive layer has a thickness t2, wherein t2?t1/3.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 11, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Martin Standing
  • Patent number: 10031549
    Abstract: Transitioning between a high-resolution input mode, such as a mouse-based interface, and a low-resolution input mode, such as a touch-based interface, is described. A change of orientation of a touch screen between a first orientation and a second orientation is detected. Transitioning between the two input modes and corresponding user interfaces (UIs) is based on the detected change of orientation. A change of orientation can be detected with one or more sensors, such as an accelerometer, position sensors, etc. Transitioning from one mode to another can include modifying an item displayed in the UI of the one mode into a corresponding item displayed in the UI of the other mode. The modifying can include enlarging/reducing, obscuring/unobscuring, moving, etc. For example, an item can be obscured by the visual effect of sliding it off of the screen.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: July 24, 2018
    Assignee: Apple Inc.
    Inventor: Paul Costa
  • Patent number: 10011478
    Abstract: A method for bonding two substrates is described, comprising providing a first and a second silicon substrate, providing a raised feature on at least one of the first and the second silicon substrate, forming a layer of gold on the first and the second silicon substrates, and pressing the first substrate against the second substrate, to form a thermocompression bond around the raised feature. The high initial pressure caused by the raised feature on the opposing surface provides for a hermetic bond without fracture of the raised feature, while the complete embedding of the raised feature into the opposing surface allows for the two bonding planes to come into contact. This large contact area provides for high strength.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 3, 2018
    Assignee: Innovative Micro Technology
    Inventors: Christopher S. Gudeman, Paul J. Rubel
  • Patent number: 9991227
    Abstract: A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 5, 2018
    Assignee: MediaTek Inc.
    Inventors: Hsing-Chih Liu, Chia-Hao Yang, Ying-Chih Chen
  • Patent number: 9978654
    Abstract: A semiconductor device has a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of wire studs or stud bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the wire studs. A first encapsulant is deposited around the semiconductor die. A first interconnect structure is formed over the semiconductor die and first encapsulant. A second encapsulant is deposited over the substrate, semiconductor die, and first interconnect structure. The second encapsulant can be formed over a portion of the semiconductor die and side surface of the substrate. A portion of the second encapsulant is removed to expose the substrate and first interconnect structure. A second interconnect structure is formed over the second encapsulant and first interconnect structure and electrically coupled to the wire studs. A discrete semiconductor device can be formed on the interconnect structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 22, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen
  • Patent number: 9960097
    Abstract: A semiconductor device manufacturing method includes a step of preparing a semiconductor unit, having a first main surface including a heat releasing portion and a second main surface opposite to the first main surface, in which is mounted a semiconductor chip, a step of preparing a cooler having a flat surface, a step of applying a paste including metal nanoparticles to the first main surface of the semiconductor unit or the flat surface of the cooler, a step of bringing the first main surface of the semiconductor unit and the flat surface of the cooler into contact through the paste, and a step of applying a pressurizing force uniform in-plane to the second main surface of the semiconductor unit at the same time as raising the temperature of the paste, thereby sintering the paste and forming a junction layer.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: May 1, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yo Sakamoto
  • Patent number: 9961773
    Abstract: A printed circuit board assembly includes: a first signal terminal row including a plurality of first signal terminals connected to a plurality of signal wirings of a flexible printed circuit board (FPCB), respectively; a first ground terminal row spaced from the first signal terminal row and including a plurality of first ground terminals connected to a plurality of ground wirings of the FPCB, respectively; a second signal terminal row including a plurality of second signal terminals connected to a plurality of signal wirings of a printed circuit board (PCB), respectively; and a second ground terminal row spaced from the second signal terminal row and including a plurality of second ground terminals connected to a plurality of ground wirings of the PCB, respectively. The first ground terminal row is closer to an end portion of the FPCB than the first signal terminal row.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 1, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dongwan Choi
  • Patent number: 9923560
    Abstract: Aspects of the disclosure provide a system having a power circuit. The power circuit includes a first switch circuit having at least a first transistor and a second switch circuit having at least a second transistor. Further, the power circuit includes first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit, and second interconnection configured to couple the second switch circuit in parallel to the first switch circuit to the driving nodes, the source node and the drain node of the power circuit. A polarity of unbalance in the first interconnections and the second interconnections dominates a polarity of current unbalance in the first switch circuit and the second switch circuit.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: March 20, 2018
    Assignees: Toyota Motor Engineering & Manufacturing North America, Inc., VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
    Inventors: Chi-Ming Wang, Yincan Mao, Zichen Miao, Khai Ngo
  • Patent number: 9893000
    Abstract: A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: February 13, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Si Hyeon Go, Jun Young Heo, Moon Taek Sung, Dong Seong Oh
  • Patent number: 9887174
    Abstract: A semiconductor device manufacturing method includes: raising and moving a bonding tool, while paying out a wire, in a direction from a second toward a first bonding point to form in the wire a cut portion bent in a vicinity of the second bonding point; lowering and moving a tip of the bonding tool to the cut portion; lowering the bonding tool vertically to thin the cut portion; raising the bonding tool while paying out the wire; and moving the bonding tool in a direction away from the first and second bonding points and along a wire direction connecting the first and second bonding points and then cutting the wire at the cut portion to form a wire tail. This allows the length of the wire tail to be adjusted easily and efficiently to be constant.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: February 6, 2018
    Assignee: SHINKAWA LTD.
    Inventor: Naoki Sekine
  • Patent number: 9842831
    Abstract: A semiconductor package includes a semiconductor die having an active surface and a bottom surface opposite to the active surface; a plurality of bond pads distributed on the active surface of the semiconductor die; an encapsulant covering the active surface of the semiconductor die, wherein the encapsulant comprises a bottom surface that is flush with the bottom surface of the semiconductor; and a plurality of printed interconnect features embedded in the encapsulant for electrically connecting the plurality of bond pads. Each of the printed interconnect features comprises a conductive wire and a conductive pad being integral with the conductive wire.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: December 12, 2017
    Assignee: MEDIATEK INC.
    Inventor: Shiann-Tsong Tsai
  • Patent number: 9842821
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: December 12, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Patent number: 9824980
    Abstract: Various aspects are directed to apparatuses, systems and related methods involving the mitigation of issues relating to thermal expansion and contraction of lead fingers of an integrated circuit package. Consistent with one or more embodiments, lead fingers on a leadframe substrate each have a locking structure that secures the lead finger in place relative to the substrate. The lead fingers provide a location to attach a bond wire to an integrated circuit, and connect the bond wire to terminals at a perimeter of the leadframe. The locking structure and arrangement of the lead fingers mitigate issues such as cracking or breaking of a solder connection of the bond wire to the leadframe, which can occur due to thermal expansion and contraction.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 21, 2017
    Assignee: NXP B.V.
    Inventors: Chayathorn Saklang, Wiwat Tanwongwan
  • Patent number: 9812423
    Abstract: A semiconductor device includes: a connection terminal; a semiconductor chip having an electrode pad on one surface; a wire that connects the connection terminal and the electrode pad of the semiconductor chip; and transparent resin that covers the one surface of the semiconductor chip, and that seals the connection terminal and the wire, wherein: the wire includes a first bonded portion that is joined to the electrode pad, a second bonded portion that is joined to the connection terminal, and a loop portion that is formed so as to be continuous with the first bonded portion and has a turned back portion on a side opposite to the second bonded portion; and predetermined clearances are provided between the loop portion and the first bonded portion, and between the loop portion and other portions of the wire.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: November 7, 2017
    Assignee: AOI Electronics Co., Ltd.
    Inventor: Naoki Fukue
  • Patent number: 9799620
    Abstract: A method of forming a die package includes forming a conductive column over a first side of a carrier, attaching a semiconductor die to the first side of the carrier, and forming a molding compound over the first side of the carrier. The semiconductor die and the conductive column are embedded in the molding compound. A second side of the carrier opposite the first side is under a compressive stress. The method also includes forming a first compressive dielectric layer over the semiconductor die, the conductive column, and the molding compound, forming a first redistribution layer (RDL) over the first compressive dielectric layer, and forming a first passivation layer over the first RDL.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 9786589
    Abstract: A method for manufacturing a package structure carries out in following way. A flexible circuit board is provided. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer, a first conductive pattern and a bearing layer located at opposite sides. The bearing layer corresponds to the laminated area. A second dielectric layer and a second conductive pattern are formed on the first conductive pattern. A third dielectric layer and a third conductive pattern are formed on the bearing layer. All of the second and third dielectric layers, and the second and third conductive pattern corresponds to the laminated area. A first solder resist layer is formed on the second conductive layer. The first solder resist layer defines a plurality of openings, a portion of the second conductive pattern is exposed from the openings defining a plurality of first pads.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: October 10, 2017
    Assignees: Qi Ding Technology Qinghuangdao Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventor: Wei-Shuo Su
  • Patent number: 9640729
    Abstract: Semiconductor LED layers are epitaxially gown on a patterned surface of a sapphire substrate (10). The patterned surface improves light extraction. The LED layers include a p-type layer and an n-type layer. The LED layers are etched to expose the n-type layer. One or more first metal layers are patterned to electrically contact the p-type layer and the n-type layer to form a p-metal contact (32) and an n-metal contact (33). A dielectric polymer stress-buffer layer (36) is spin-coated over the first metal layers to form a substantially planar surface over the first metal layers. The stress-buffer layer has openings exposing the p-metal contact and the n-metal contact. Metal solder pads (44, 45) are formed over the stress-buffer layer and electrically contact the p-metal contact and the n-metal contact through the openings in the stress-buffer layer. The stress-buffer layer acts as a buffer to accommodate differences in CTEs of the solder pads and underlying layers.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 2, 2017
    Assignee: Koninklijke Philips N.V.
    Inventors: Salman Akram, Quanbo Zou
  • Patent number: 9627585
    Abstract: In a wiring conversion part which connects a lower conductive film to a first conductive film each functioning as a wiring, a first transparent conductive film is formed into a pattern in which it covers an end surface of the first conductive film, and an angle formed at a corner part in a portion of the first transparent conductive film making contact with a lower first insulating film (outside a width of the first conductive film) is larger than 90 degrees and smaller than 270 degrees or the corner part has an arc shape. A second transparent conductive film is connected to the lower conductive film and the first transparent conductive film, and the first transparent conductive film is connected to the first conductive film, so that the lower conductive film and the first conductive film are electrically connected to each other.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 18, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazunori Okumoto
  • Patent number: 9620697
    Abstract: The present invention provides a thermoelectric conversion material of which the structure is controlled to have nano-order microscopic pores and which has a low thermal conductivity and has an improved thermoelectric performance index. In the thermoelectric conversion material having a thermoelectric semiconductor layer formed on a block copolymer substrate that comprises a block copolymer having microscopic pores, wherein the block copolymer comprises a polymer unit (A) formed of a monomer capable of forming a homopolymer having a glass transition temperature of 50° C. or higher, and a polymer unit (B) formed of a conjugated dienic polymer.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: April 11, 2017
    Assignees: KYUSHU INSTITUTE OF TECHNOLOGY, LINTEC CORPORATION
    Inventors: Tsuyoshi Mutou, Koji Miyazaki, Yoshika Hatasako, Kunihisa Kato
  • Patent number: 9536837
    Abstract: A TSV via structure comprising an upper part made on the side of the front face of a substrate in which electronic components are located and a lower part with height and cross-section smaller than the height and cross-section the upper part, the arrangement of the connection element in the substrate being such that it releases stresses generated by the different materials of said structure.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 3, 2017
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Yann Lamy
  • Patent number: 9515043
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 6, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Patent number: 9472514
    Abstract: To reduce radio frequency (RF) losses during operation of a radio frequency integrated circuit (RFIC) module, the RFIC module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the RF current to flow around the high-resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: October 18, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Weimin Sun, Peter J. Zampardi, Jr., Hongxiao Shao
  • Patent number: 9434027
    Abstract: It is an object of the present invention to provide a bonding wire capable of maintaining a structure and a configuration thereof at the time of performing wire bonding; and a manufacturing method thereof. Provided is a bonding wire having a core member mainly composed of copper; and a palladium coating layer. Particularly, formed in a center of the core member is a fibrous structure with copper crystals extending in an axial direction.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: September 6, 2016
    Assignee: NIPPON MICROMETAL CORPORATION
    Inventor: Ryo Togashi
  • Patent number: 9433117
    Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 30, 2016
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jong Ok Chun, Nozad Karim, Richard Chen, Giuseppe Selli, Michael Kelly
  • Patent number: 9401717
    Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: July 26, 2016
    Assignee: Baysand Inc.
    Inventors: Jonathan C Parks, Yin Hao Liew, Kok Seong Lee, Salah M Werfelli
  • Patent number: 9391032
    Abstract: An embodiment includes an integrated circuit, comprising: a substrate; a first circuit formed on the substrate and coupled to a plurality of first pads on the substrate; and a second circuit formed on the substrate and coupled to a plurality of second pads on the substrate. The first pads are formed on a perimeter of the substrate; and the second pads extend from the perimeter of the substrate towards an interior of the substrate.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: July 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Koog, Jiankang Wang, Harpreet Gill, Sunghwan Min
  • Patent number: 9357604
    Abstract: An LED array switching apparatus comprises, on a single PCB substrate: a plurality of LED arrays D1 to Dn connected in series, each LED array having a forward voltage; an AC voltage supply coupled to the plurality of LED arrays; and a plurality of constant current sources G1 to Gn, coupled to outputs of LED arrays D1 to Dn, respectively, each of the constant current sources being switchable between a current regulating state and an open state such that as the voltage of the AC voltage supply increases, LED arrays are switched on and lit to form a higher forward voltage LED string, and as the voltage of the AC voltage supply decreases, LED arrays are switched off and removed from the LED string starting with the most recently lit LED array.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: May 31, 2016
    Assignee: Huizhou Light Engine Ltd.
    Inventors: Kam Wah Siu, Wa Hing Leung
  • Patent number: 9331039
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 3, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Patent number: 9325257
    Abstract: The purpose of the present invention is to reduce variance of a voltage to be applied between the terminals of each of the power semiconductor elements, and to improve lifetime of the power semiconductor elements and reliability of the power semiconductor device. In order to achieve the purpose, in this power semiconductor device, which is provided with three or more power semiconductor elements that are aligned and mounted on a metal wire, and another metal wire different from the metal wire, one terminal of each of the power semiconductor elements being connected to the wire and another one terminal thereof being connected to the other wire, the resistance value of the metal wire in a region where the power semiconductor elements are mounted is higher in the downstream side than that in the upstream side in the electric current flowing direction.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: April 26, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yoshio Okayama
  • Patent number: 9324675
    Abstract: A semiconductor structure includes a bond pad and a wire bond coupled to the bond pad. The wire bond includes a bond in contact with the bond pad. The wire bond includes a coating on a surface of the wire bond, and a first exposed portion of the wire bond in a selected location. The wire bond is devoid of the coating over the selected location of the wire bond, and an area of the first exposed portion is at least one square micron.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 26, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Burton J. Carpenter, Chu-Chung Lee, Tu-Anh N. Tran
  • Patent number: 9281339
    Abstract: A method for mounting a chip on a printed circuit board (PCB) is disclosed. The method includes the steps of: providing a chip having a plurality of bonding pads and a PCB having a recess portion and a plurality of connectors; gluing the recess portion; placing the chip into the recess portion; and forming circuit patterns linking associated bonding pad and connector. A bottom of the recess portion is substantially flat and a shape of the recess portion is similar to that of the chip but large enough so that the chip can be fixed in the recess portion after being glued.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: March 8, 2016
    Assignee: Sunasic Technologies, Inc.
    Inventors: Chi-Chou Lin, Zheng-Ping He
  • Patent number: 9280737
    Abstract: A system in package (SIP) structure, an electroplating module thereof and a memory storage device are provided. The SIP structure includes a first layout layer, a second layout layer and a rewritable non-volatile memory module. The first layout layer includes a first pad and a wire. The first pad is close to a first side of the first layout layer, and the first pad is configured to couple to a ground voltage. One terminal of the wire is coupled to the first pad, and another terminal of the wire is coupled to an opening of the SIP structure, wherein the opening is located at a second side of the first layout layer opposite to the first side, and the opening is configured to couple to an external voltage.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: March 8, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chun-Feng Lee, Chien-Liang Chang, Hsuan-Teng Cheng
  • Patent number: 9277614
    Abstract: An LED array switching apparatus comprises, on a single PCB substrate: a plurality of LED arrays D1 to Dn connected in series, each LED array having a forward voltage; an AC voltage supply coupled to the plurality of LED arrays; and a plurality of constant current sources G1 to Gn, coupled to outputs of LED arrays D1 to Dn, respectively, each of the constant current sources being switchable between a current regulating state and an open state such that as the voltage of the AC voltage supply increases, LED arrays are switched on and lit to form a higher forward voltage LED string, and as the voltage of the AC voltage supply decreases, LED arrays are switched off and removed from the LED string starting with the most recently lit LED array.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 1, 2016
    Assignee: Huizhou Light Engine Ltd.
    Inventors: Kam Wah Siu, Wa Hing Leung
  • Patent number: 9269677
    Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 23, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chia-Yin Chen, Yu-Ching Liu, Yueh-Chiung Chang, Yu-Po Wang
  • Patent number: 9263373
    Abstract: A high density film adapted for nanochip package comprises three redistribution layers. A bottom redistribution circuit has a plurality of first bottom pads adapted for a nanochip to mount; and has a plurality of first top pads. The density of the first bottom pads is higher than the density of the first top pads. A middle redistribution circuit has a plurality of second bottom pads electrically coupled to the first top pads; and has a plurality of second top pads. The density of the second bottom pads is higher than the density of the second top pads. A top redistribution circuit has a plurality of third bottom pads electrically coupled to the second top pads; and has a plurality of third top pads. The density of the third bottom pads is higher than the density of the third top pads.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: February 16, 2016
    Inventor: Dyi-Chung Hu
  • Patent number: 9252086
    Abstract: A connector for electrically connecting a chip electrode of a semiconductor element to a lead constituting an external leading terminal of the chip electrode, includes a first connecting part having an interface joined to the chip electrode; a second connecting part having an interface joined to a base end part of the lead; and a plate-shape coupling part for connecting the first connecting part and the second connecting part to each other, and having a step formed on the interface of the first connecting part in a direction away from the chip electrode by a half blanking process.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: February 2, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Atsushi Maruyama