Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

Abstract: A configuration of wirebonds for reducing cross-talk in a quantum computing chip includes a first wirebond coupling a first conductor of a quantum computing circuit with a first conductor of an external circuit. The embodiment further includes in the configuration a second wirebond coupling a second conductor of the quantum computing circuit with a second conductor of the external circuit, wherein the first wirebond and the second wirebond are separated by a first vertical distance in a direction of a length of the first conductor.

Abstract: A ball grid array (BGA) package for an integrated circuit device includes an integrated circuit device having a plurality of terminals, and two largest dimensions that define a major plane. A package substrate material encloses the integrated circuit device, and is formed, in a plane parallel to the major plane, into a polygon having at least five sides. An array of contacts on an exterior surface of the package substrate material is electrically coupled to the plurality of terminals. Contacts in the array of contacts are distributed in a pattern of contact positions, and the center of each contact position may be separated from the center of each nearest other position by a separation distance that is identical throughout the pattern. Each position may be occupied by a contact, or positions in a sub-pattern may lack a contact and may be available for insertion of at least one via.

Abstract: A semiconductor package includes a substrate and a semiconductor chip, a lower conductive layer and an upper conductive layer sequentially stacked on the substrate. The substrate includes first and second connection pads formed thereon. The semiconductor chip includes third and fourth connection pads formed thereon. The upper conductive layer is connected to the first and the third connection pads via a first and a second wiring, and the lower conductive layer is connected to the second and the fourth connection pads via a third and a fourth wiring.

Abstract: A nanowire semiconductor device having a high-quality epitaxial layer. The semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.

Abstract: A method for manufacturing a semiconductor device includes: a first bonding process including bonding, at a first bonding point, a tip of a wire held by a capillary; a first lifting process including moving the capillary upward; a first reverse process including moving the capillary in a direction that includes a component in a first direction that is from a second bonding point toward the first bonding point; a second lifting process including moving the capillary upward; a second reverse process including moving the capillary in the first direction; a third lifting process including moving the capillary upward; a forward process including moving the capillary toward the second bonding point; and a second bonding process including bonding the wire at the second bonding point. A movement distance of the capillary in the first lifting process is not less than a movement distance of the capillary in the second lifting process.

Abstract: Methods and apparatus for modulating light thorough a transparent laminate structure. The transparent laminate structure includes at least one soft dielectric layer and at least one stiff dielectric layer having a stiffness greater than the stiffness of the at least one soft dielectric layer. The transparent laminate structure further comprises a plurality of stiff conductive elements formed on a surface of the at least one soft dielectric layer that, in the presence of an electric field, compress the at least one soft dielectric layer to alter a morphology of the surface of the at least one soft dielectric layer on which the plurality of stiff conductive elements are formed. Light incident on the surface of the at least one soft dielectric layer is scattered by the undulating morphology of the surface, thereby reducing the transmission of light through the transparent laminate structure.

Abstract: The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that a size of electronic package structure can be reduced. The three-dimensional package structure comprises a first electronic component, a plurality of second electronic components and a plurality of conductive patterns. The first electronic component has a top surface and a bottom surface. The plurality of second electronic components are disposed over the top surface of the first electronic component. The plurality of conductive patterns are disposed over the plurality of second electronic components to electrically connect the plurality of second electronic components and the first electronic component.

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device including first and second semiconductor dies arranged on respective and first and second carriers, the first and second semiconductor dies each comprising a first contact and a second contact arranged on a top major surface of the respective semiconductor dies and a third contact arranged on a bottom major surface the respective semiconductor dies; first and second die connection portions, arranged on the respective first and second carriers, connected to the third contacts of the respective first and second semiconductor dies; and a first contact connection member, extending from the first contact of the first semiconductor die to the die connection portion of second carrier, electrical connection of the first contact of the first semiconductor die to the third contact of the second semiconductor die.

Abstract: Provided are a semiconductor module capable of further increasing an effect of canceling out a parasitic inductance by a current and a power converter including the semiconductor module. The semiconductor module includes a first leadframe, a second leadframe, a third leadframe, an insulating material, a first semiconductor element, and a second semiconductor element. The first leadframe is a plate-shaped wiring path to which a first potential is applied. The second leadframe is a plate-shaped wiring path including an output terminal. The third leadframe is a plate-shaped wiring path to which a second potential is applied. The first semiconductor element is directly joined to the first leadframe with a joint material therebetween, and the second semiconductor element is directly joined to the second leadframe with a joint material therebetween. The first leadframe and the second leadframe face each other with the insulating material therebetween.

Abstract: A semiconductor module includes a substrate, two bare chips (semiconductor elements) mounted on the substrate, and a case fixed to the substrate. A conductor pattern and five signal patterns are provided for each bare chip on an upper surface of an insulating substrate. Signal electrodes and the signal patterns of the bare chips are connected to by conductive plates. An insulating member is provided on connecting portions of the conductive plates.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

Abstract: A method of manufacturing a transparent flexible silver nanowire-based conducting film and a transparent flexible silver nanowire-based conducting film are provided. The method includes coating conductive nanowires, which shield and absorb electromagnetic interference, on a flexible substrate, sintering the conductive nanowires using a wet sintering process, and coating a polymer layer in which graphene flakes are dispersed on the flexible substrate with the conductive nanowires formed thereon.

Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. In particular, the present embodiments allow for the automatic creation of WSPs by examining heights and placement orientations of instances, along with the width, spacing, and colors of instance pins and blockages. In these and other embodiments, techniques are provided for filling gaps between generated tracks, as well as for generating tracks to account for the possibility of flipped or mirrored instances.

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Abstract: A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer disposed on the first insulating layer, first vias penetrating through the first insulating layer and electrically connecting the connection pads and the first redistribution layer to each other, and a first insulating film covering the first insulating layer and the first redistribution layer. The first insulating film includes a silicon based compound.

Abstract: Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a plurality of conductive layers designed so as to be formed in a first region within a semiconductor chip, the density in which the plurality of conductive layers are disposed in the first region being at least a first threshold value and not more than a second threshold value, the first and second threshold values being less than a minimum density according to the design rules for ensuring that all of the plurality of conductive layers are formed in the first region; and a reader which provides an identification key by identifying if, among the plurality of conductive layers, a previously designated first conductive layer has been formed.

Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and his a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.

Abstract: A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base substrate and having an opening exposing a portion of the conductive pad; and a bump on the exposed portion of the conductive pad and on the insulating layer around the opening. The bump includes a plurality of concave portions corresponding to the opening and is arranged in a longitudinal direction of the bump.

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Abstract: A semiconductor device includes an electronic component that includes an oscillator and has terminals on one face. A semiconductor chip is electrically connected to the electronic component and also includes terminals on one face thereof. The electronic component and the semiconductor chip are mounted to a mounting base such that the terminals of the electronic component and the terminals of the semiconductor chip face in the same direction. First bonding wires are connected to the terminals of the semiconductor chip, and second bonding wires having an apex height smaller than that of the first bonding wires connect the terminals of the electronic component to the terminals of the semiconductor chip. A sealing member completely seals within at least the electronic component.

Abstract: Aspects of the present disclosure relate to a packaged module with a radio frequency isolation structure that includes a racetrack, a conductive layer, and a conductive feature in an electrical path between the racetrack and the conductive layer. The racetrack can be disposed in a substrate and configured at a ground potential. The racetrack can include a break.

Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.

Abstract: The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.

Abstract: A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Abstract: The invention relates to a method for integrating at least one interconnection for the manufacture of an integrated circuit, including a step of depositing at least one insulating body onto a substrate including a horizontal surface, said insulating body comprising a first wall extending from the horizontal surface of the substrate to a high point of said insulating body and a step of depositing a one-piece electrical structure which is made of an electrically conductive material and extends on the horizontal surface of the substrate and the first wall of the insulating body, the first wall being vertically angled by more than 10 ?m and having a rising slope extending from the horizontal surface of the substrate to the high point of said insulating body.

Abstract: Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.

Abstract: An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.

Abstract: Electrically-conductive wires are used to construct an EMI shield between inductors of an RF module that prevents, or at least reduces, EMI crosstalk between the inductors while maintaining high Q factors for the inductors. The EMI shield comprises at least a first set of electrically-conductive wires that at least partially surrounds and extends over at least a first inductor of a pair of inductors. Adjacent wires of the first set are spaced apart from one another by a predetermined distance selected to ensure that the EMI shield attenuates a frequency or frequency range of interest. First and second ends of each of the wires are connected to an electrical ground structure. A length of each wire in between the first and second ends of the respective wire extends above the first inductor and is spaced apart from the first inductor so as not to be in contact with the first inductor.

Abstract: A method for manufacturing a transistor with stable electric characteristics and little signal delay due to wiring resistance, used in a semiconductor device including an oxide semiconductor film. A semiconductor device including the transistor is provided. A high-performance display device including the transistor is provided.

Abstract: A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication between the second semiconductor package and a host device occurs through the first semiconductor package.

Abstract: A conductive nanowire film having a high aspect-ratio metal is described. The nanowire film is produced by inducing metal reduction in a concentrated surfactant solution containing metal precursor ions, a surfactant and a reducing agent. The metal nanostructures demonstrate utility in a great variety of applications.

Abstract: A semiconductor device is provided that includes a semiconductor substrate; an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen; a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and an upper electrode provided above the insulating film. The barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.

Abstract: A semiconductor device is provided that includes a semiconductor substrate; an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen; a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and an upper electrode provided above the insulating film. The barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.

Abstract: A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate.

Abstract: A manufacturing method for a wire bonding structure of the present invention includes a step of preparing a wire made of Cu and a step of joining the wire to a first joining target formed on an electronic device. Before the joining step, the wire has an outer circumferential surface and a withdrawn surface. The withdrawn surface is withdrawn toward a central axis of the wire from the outer circumferential surface. In the joining step, ultrasonic vibration is applied to the wire in a state in which the withdrawn surface is pressed against the first joining target.

Abstract: A method and structure for improving high voltage breakdown reliability of a microelectronic device, e.g., a galvanic digital isolator, involves providing an abatement structure around metal plate corners of a high voltage isolation capacitor to ameliorate the effects of an electric field formed thereat during operation of the device due to dielectric discontinuity.

Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.

Abstract: Aligned high quality boron nitride nanotubes (BNNTs) can be incorporated into groups and bundles and placed in electronic and electrical components (ECs) to enhance the heat removal and diminish the heat production. High quality BNNTs are excellent conductors of heat at the nano scale. High quality BNNTs are electrically insulating and can reduce dielectric heating. The BNNTs composite well with a broad range of ceramics, metals, polymers, epoxies and thermal greases thereby providing great flexibility in the design of ECs with improved thermal management. Controlling the alignment of the BNNTs both with respect to each other and the surfaces and layers of the ECs provides the preferred embodiments for ECs.

Abstract: A compartment EMI shield for use inside of a system module package is provided that comprises at least a first set of electrically-conductive wires that surrounds and extends over circuitry of the module package. Adjacent wires of the first set are spaced apart from one another by a predetermined distance selected to ensure that the compartment EMI shield attenuates a frequency or frequency range of interest. First and second ends of each of the wires are connected to an electrical ground structure. A length of each wire that is located in between the first and second ends of the respective wire extends above the circuitry and is spaced apart from the components of the circuitry so as not to be in contact with the components of the circuitry.

Abstract: In an embodiment, a chip protection envelope includes a first dielectric layer including at least one organic component having a decomposition temperature of at least 180° C., a semiconductor die embedded in the first dielectric layer, the semiconductor die having a first surface and a thickness t1. A second dielectric layer is arranged on a first surface of the first dielectric layer, the second dielectric layer including a photodefinable polymer composition, and a conductive layer is arranged on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The conductive layer has a thickness t2, wherein t2?t1/3.

Abstract: Transitioning between a high-resolution input mode, such as a mouse-based interface, and a low-resolution input mode, such as a touch-based interface, is described. A change of orientation of a touch screen between a first orientation and a second orientation is detected. Transitioning between the two input modes and corresponding user interfaces (UIs) is based on the detected change of orientation. A change of orientation can be detected with one or more sensors, such as an accelerometer, position sensors, etc. Transitioning from one mode to another can include modifying an item displayed in the UI of the one mode into a corresponding item displayed in the UI of the other mode. The modifying can include enlarging/reducing, obscuring/unobscuring, moving, etc. For example, an item can be obscured by the visual effect of sliding it off of the screen.

Abstract: A method for bonding two substrates is described, comprising providing a first and a second silicon substrate, providing a raised feature on at least one of the first and the second silicon substrate, forming a layer of gold on the first and the second silicon substrates, and pressing the first substrate against the second substrate, to form a thermocompression bond around the raised feature. The high initial pressure caused by the raised feature on the opposing surface provides for a hermetic bond without fracture of the raised feature, while the complete embedding of the raised feature into the opposing surface allows for the two bonding planes to come into contact. This large contact area provides for high strength.

Abstract: A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.

Abstract: A semiconductor device has a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of wire studs or stud bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the wire studs. A first encapsulant is deposited around the semiconductor die. A first interconnect structure is formed over the semiconductor die and first encapsulant. A second encapsulant is deposited over the substrate, semiconductor die, and first interconnect structure. The second encapsulant can be formed over a portion of the semiconductor die and side surface of the substrate. A portion of the second encapsulant is removed to expose the substrate and first interconnect structure. A second interconnect structure is formed over the second encapsulant and first interconnect structure and electrically coupled to the wire studs. A discrete semiconductor device can be formed on the interconnect structure.

Abstract: A semiconductor device manufacturing method includes a step of preparing a semiconductor unit, having a first main surface including a heat releasing portion and a second main surface opposite to the first main surface, in which is mounted a semiconductor chip, a step of preparing a cooler having a flat surface, a step of applying a paste including metal nanoparticles to the first main surface of the semiconductor unit or the flat surface of the cooler, a step of bringing the first main surface of the semiconductor unit and the flat surface of the cooler into contact through the paste, and a step of applying a pressurizing force uniform in-plane to the second main surface of the semiconductor unit at the same time as raising the temperature of the paste, thereby sintering the paste and forming a junction layer.

Abstract: A printed circuit board assembly includes: a first signal terminal row including a plurality of first signal terminals connected to a plurality of signal wirings of a flexible printed circuit board (FPCB), respectively; a first ground terminal row spaced from the first signal terminal row and including a plurality of first ground terminals connected to a plurality of ground wirings of the FPCB, respectively; a second signal terminal row including a plurality of second signal terminals connected to a plurality of signal wirings of a printed circuit board (PCB), respectively; and a second ground terminal row spaced from the second signal terminal row and including a plurality of second ground terminals connected to a plurality of ground wirings of the PCB, respectively. The first ground terminal row is closer to an end portion of the FPCB than the first signal terminal row.

Abstract: Aspects of the disclosure provide a system having a power circuit. The power circuit includes a first switch circuit having at least a first transistor and a second switch circuit having at least a second transistor. Further, the power circuit includes first interconnections configured to couple the first switch circuit to driving nodes, a source node and a drain node of the power circuit, and second interconnection configured to couple the second switch circuit in parallel to the first switch circuit to the driving nodes, the source node and the drain node of the power circuit. A polarity of unbalance in the first interconnections and the second interconnections dominates a polarity of current unbalance in the first switch circuit and the second switch circuit.

Abstract: A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.