Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Abstract: A power semiconductor device includes first and second disc-shaped electrodes and a wafer sandwiched between the electrodes. An outer insulating ring is attached to the first and second electrodes and surrounds the wafer. An inner insulating ring is located inside of the outer insulating ring and surrounds the wafer and a ring-shaped first flange portion laterally surrounds a main portion of the first electrode. An O-ring radially surrounds the main portion of the first electrode and is sandwiched in a vertical direction between the inner insulating ring and the first flange portion. In a relaxed state the O-ring has a cross-section that is elongated in the vertical direction such that, in the relaxed state, a height of the O-ring in the vertical direction is greater than a width of the O-ring in a radial direction that is parallel to the first contact face.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Abstract: A vehicular accessory module includes a circuit board and a metal enclosure. An electrically conductive grounding contact affixed at a first side of the circuit board and electrically connected to circuitry at the circuit board. The grounding contact is disposed between and contacts both the first side of the circuit board and the metal enclosure to provide an electrical connection between the circuit board and the metal enclosure. The grounding contact includes an abrasive surface that is in contact with the metal enclosure. Movement of the grounding contact relative to the metal enclosure causes the abrasive surface to scrape the metal enclosure to enhance grounding of the grounding contact with the metal enclosure.

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Abstract: A functional contactor is provided. The functional contactor contains a conductive elastic portion having elasticity and electrically contacting one of a circuit board of an electronic device, a bracket coupled to the circuit board, and a conductor which can come into contact with the human body; a substrate containing a plurality of dielectric layers; and a functional element embedded in the substrate so as to be electrically connected in series to the conductive elastic portion.

Abstract: According to an embodiment, an electronic apparatus includes a printed circuit board including a plurality of devices that include a nonvolatile memory package and a controller package configured to control the nonvolatile memory package, and a housing accommodating the printed circuit board. The housing includes an opening on a surface constituting the housing. An encryption device among the plurality of devices is present in a first region. The first region is a region on the printed circuit board that is not irradiated with light emitted from a light source placed at the opening. The encryption device is a device used for an encryption process of data to be stored into the nonvolatile memory package.

Abstract: A stack boat tool includes a boat including a stack hole configured to accommodate first and second semiconductor packages; and a weight bar configured to be placed on the second semiconductor package during a reflow process for combining the first and second semiconductor packages, wherein the weight bar includes: a base configured to contact an upper surface of the second semiconductor package; a sidewall on the base; and a balance weight arranged on the base configured to lower a weight center of the weight bar.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: The reliability of a copper wire is improved without inhibiting the wiring resistance of the copper wire. For example, another metallic element segregates in the boundary region between a copper film CUF1 and a copper film CUF2, and at the upper side face part of a wiring gutter leading to the boundary region. In a sectional view, a metallic element having a reducing power higher than copper segregates at the inner part of the copper wire apart from both the surface of the copper wire and the bottom face of the wiring gutter and at the side face part of the copper wire. In a sectional view, a metallic element different from copper segregates in the vicinity of the center part of the copper wire and at the side face part of the copper wire.

Abstract: The present invention provides a method for manufacturing silicon carbide semiconductor apparatus including a testing step of testing a PN diode for the presence or absence of stacking faults in a relatively short time and an energization test apparatus. The present invention sets the temperature of a bipolar semiconductor element at 150° C. or higher and 230° C. or lower, causes a forward current having a current density of 120 [A/cm2] or more and 400 [A/cm2] or less to continuously flow through the bipolar semiconductor element, calculates, in a case where a forward resistance of the bipolar semiconductor element through which the forward current flows reaches a saturation state, the degree of change in the forward resistance, and determines whether the calculated degree of change is smaller than a threshold value.

Abstract: A Schottky diode and a method for making one. The method includes the following steps: providing a semiconductor base body, preferably in the form of a wafer, having a high dopant concentration and having a first main surface, which forms the first electrical contact surface of the Schottky diode; epitaxially depositing a semiconductor layer having the same conductivity and a lower dopant concentration on that surface of the semiconductor base body which lies opposite the first main surface; arranging a first metal layer on the semiconductor layer with the formation of a Schottky contact between the first metal layer and the semiconductor layer; connecting a planar contact body to the first metal layer by means of a connecting means; forming at least one individual Schottky diode; and arranging a passivation layer in the edge region of the at least one Schottky diode.

Abstract: The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer.

Abstract: In an embodiment, an apparatus for reducing the mechanical load on the electrical terminals of a capacitor includes a plate having a planar body and one or more deflectable tabs connected to the planar body, one or more capacitors respectively mounted to the plate via the one or more deflectable tabs, and a busbar electrically connected to the one or more capacitors such that the one or more capacitors are arranged intermediate the plate and the busbar. The deflectable tabs are configured to support the capacitors, and to move towards and away from the planar body for accommodating size variances in the capacitors relative to a fixed spacing between the busbar and an enclosure.

Abstract: A semiconductor device includes a first insulator film having a first opening, a first wiring layer extending from the first opening onto the first insulator film, a first semiconductor chip mounted on the first insulator film so as to be electrically coupled with the first wiring layer, and a resin portion applied on the first insulation film to cover the first semiconductor chip.

Abstract: A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.

Abstract: A method for manufacturing a printed wiring board, including providing a support board having a metal foil secured to the support board, forming a resin insulation layer on the metal foil, forming openings in the resin insulation layer, forming a conductive circuit on the resin insulation layer, forming in the openings via conductors to electrically connect the conductive circuit and the metal foil, separating the support board and the metal foil, and forming from the metal foil external terminals to electrically connect to another substrate or electronic component.

Abstract: A semiconductor device includes a plate-shaped semiconductor element and an electrically insulating resin member. The semiconductor element has a front-surface electrode on its front surface and a back-surface electrode on its back surface. The resin member encapsulates the semiconductor element. The front-surface electrode is exposed to a front side of an outer surface of the resin member. The back-surface electrode is exposed to a back side of the outer surface of the resin member. The resin member has an extension portion that covers the entire side surface of the semiconductor element and extends from the side surface of the semiconductor element in a direction parallel to the front surface of the semiconductor element.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.

Abstract: A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthanide oxide. A ruthenium-based gate on a lanthanide oxide provides a gate structure that can effectively prevent a reaction between the gate and the lanthanide oxide.

Abstract: A semiconductor module includes a semiconductor having a semiconductor substrate, a first electrode formed on one surface of the semiconductor substrate, and a second electrode formed on an opposite surface of the semiconductor substrate. A first conductive member is in contact with the first electrode. A second conductive member is in contact with the second electrode. A third conductive member is in contact with the second conductive member and extends along the first conductive member. An insulating member provides insulation between the first conductive member and the third conductive member. The third conductive member is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member. The semiconductor device is fixed to the first conductive member and the second conductive member by being sandwiched between the first conductive member and the second conductive member.

Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.

Abstract: A semiconductor module system includes a substrate, at least one semiconductor chip, and a number of at least two electrically conductive first connecting elements. The substrate has a bottom side and a top side spaced apart from the bottom side in a vertical direction. The at least one semiconductor chip is arranged on the top side. Each one of the first connecting elements has a first end which protrudes away from an insulation carrier of the substrate in a direction perpendicular to the vertical direction. The semiconductor system further includes a connecting system with a number of N?1 connectors. A first one of the connectors includes at least two electrically conductive second connecting elements. Each one of the second connecting elements has a first end. The first end of each one of the first connecting elements is electrically conductively connectable to the first end of one of the second connecting elements.

Abstract: The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

Abstract: In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.

Abstract: A semiconductor device includes a semiconductor substrate; and a through electrode that penetrates the semiconductor substrate. The semiconductor substrate has a groove structure that is positioned between a peripheral edge of the semiconductor substrate and the through electrode.

Abstract: A semiconductor module includes a semiconductor device, a first conductive member, a second conductive member, a cylinder, and a cover. The first conductive member is in contact with a first electrode of the semiconductor device. The second conductive member is in contact with a second electrode of the semiconductor device. The cylinder encompasses the semiconductor device and is fixed to the first conductive member, and a first thread groove is formed on the cylinder. A second thread groove is formed on the cover. The cover is fixed to the cylinder by an engagement of the second thread groove with the first thread groove. The semiconductor device and the second conductive member are fixed by being sandwiched between the first conductive member and the cover. The second conductive member includes a portion extending from inside to outside the cylinder by penetrating an outer peripheral wall of the cylinder.

Abstract: At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device wafer and on the at least one metal adhesion layer. The first and second device wafers are then bonded together. The bonding includes heating the devices wafers to a temperature of less than 400° C., with or without, application of an external applied pressure. During the heating, the two Cu surfaces are bonded together and the at least one metal adhesion layer gets oxygen atoms from the two Cu surfaces and forms at least one metal oxide bonding layer between the Cu surfaces.

Abstract: Systems and methods for utilizing power overlay (POL) technology and semiconductor press-pack technology to produce semiconductor packages with higher reliability and power density are provided. A POL structure may interconnect semiconductor devices within a semiconductor package, and certain embodiments may be implemented to reduce the probability of damaging the semiconductor devices during the pressing of the conductive plates. In one embodiment, springs and/or spacers may be used to reduce or control the force applied by an emitter plate onto the semiconductor devices in the package. In another embodiment, the emitter plate may be recessed to exert force on the POL structure, rather than directly against the semiconductor devices. Further, in some embodiments, the conductive layer of the POL structure may be grown to function as an emitter plate, and regions of the conductive layer may be made porous to provide compliance.

Abstract: A processing technique facilitating the fabrication of the integrated circuit with microsprings at different vertical positions relative to a surface of a substrate is described. During the fabrication technique, microsprings are lithographically defined on surfaces of a first substrate and a second substrate. Then, a hole is created through a first substrate. Moreover, the integrated circuit may be created by rigidly mechanically coupling the two substrates to each other such that the microsprings on the surface of the second substrate are within a region defined at least in part by an edge around the hole. Subsequently, photoresist that constrains the microsprings on the surfaces of the two substrates may be removed. In this way, microsprings at the different vertical positions can be fabricated.

Abstract: A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film.

Abstract: A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.

Abstract: A semiconductor device includes a support plate having a hole formed therein and a conductor formed on a wall surface of the hole, a semiconductor element; and a conductive post formed by a conductor having a first end portion at one end, and a second end portion at an other end. The second end portion of the conductive post is connected to the semiconductor element, and a side surface of the conductive post is fixed to the conductor on the wall surface of the hole deformed by pressing force of the conductive post on a side closer to the first end portion than the second end portion.

Abstract: Some embodiments provide force input control devices for sensing vector forces comprising: a sensor die comprising: a rigid island, an elastic element coupled to the rigid island, die frame coupled to a periphery of the elastic element, one or more stress sensitive components on the elastic element, and signal processing IC, where the sensor die is sensitive to a magnitude and a direction of a force applied to the rigid island within the sensor die, where the sensor die is coupled electrically and mechanically to a substrate, a spring element coupling an external button, where the force is applied, to the rigid island element, wherein the spring element has a flat geometry and located in a plane parallel to a plane of the substrate, where the spring element is configured to translate a deflection of the button into an allowable force applied to the rigid island.

Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

Abstract: A piezoresistive pressure sensor is provided, which can prevent the occurrence of ESD breakdown due to the nearness of interconnection layers of a resistive element according to miniaturization thereof. The piezoresistive pressure sensor is so configured that respective semiconductor resistive layers on both sides of an arrangement are formed to be relatively longer than an adjacent semiconductor resistive layer, and thus a corner portion of a semiconductor connection layer that extends from the respective semiconductor resistive layers on both sides of the arrangement and a corner portion of the semiconductor interconnection layer that is nearest to the corner portion of the semiconductor connection layer, between which the ESD breakdown occurs easily, can be separated from each other.

Abstract: A light-emitting diode packaging structure comprises a light-emitting diode and first and second metal plates on which the light-emitting diode is mounted. The light-emitting diodes includes first and second electrode leads, the second electrode lead having first and second contact surfaces on an outer edge of the second electrode lead. The first metal plate includes at least one clamping portion that clamps and fixes the first electrode lead on the first metal plate. The second metal plate includes at least first and second clamping portions. The first contact surface of the second electrode lead contacts the first clamping portion, and the second contact surface of the second electrode lead contacts the second clamping portion, such that the light-emitting diode is fixed on the second metal plate in at least two dimensions parallel to a primary surface of the second metal plate on which the light-emitting diodes is mounted.

Abstract: The semiconductor device comprises a support plate; a semiconductor element; and conductor posts consisting of a conductor having a first end at one end and a second end at the other end, the second end being connected to the semiconductor element and the conductor posts being connected to the support plate at a position on the side of the second end that is closer to the first end, wherein the conductor posts have a heat conductivity of approximately 200 W/m·K or higher and a Vickers hardness of approximately 70 or lower.

Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

Abstract: A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.

Abstract: Embodiments of the invention provide a first component with a compliant interconnect bonded to a second component with a land pad by a metal to metal bond. In some embodiments, the first component may be a microprocessor die and the second component a package substrate.

Abstract: An interconnect structure of an integrated circuit and manufacturing method therefore are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.

Abstract: A light-emitting diode packaging structure, a packaging module and the assembling method thereof are disclosed. The assembling method comprises the steps of: providing a light-emitting diode, wherein the light-emitting diode has two electrode leads; providing two metal plates, wherein each of the metal plates has at least a clamping portion; holding the electrode leads against the metal plates respectively; and bending the clamping portion of each of the metal plates to fix the electrode leads on the metal plates. Further, a plurality of light-emitting diodes are allowed to be mounted on the metal plates to form the light-emitting diode packaging module.

Abstract: A power semiconductor module includes a housing, terminal elements leading to the outside of the housing, an electrically insulated substrate arranged inside the housing, with the substrate being comprised of an insulating body and having on the first main face facing away from the base plate a plurality of connecting tracks electrically insulated from each other. The terminal and connecting elements are arranged on a connecting track in with contact faces contacting connecting tracks or power semiconductor components, with the individual contact faces having a plurality of partial contact faces. In one optional embodiment, each partial contact face has a maximum area of 20 mm2. In another embodiment, partial contact faces each are arranged at a distance of approximately 5 mm with regard to each other and the connection of the partial faces to the connecting tracks or the power semiconductor components is flush.

Abstract: An insulative substrate includes a plurality of flexible retaining clips and a plurality of alignment and retaining pins. A metal leadframe includes a plurality of leads. Each lead terminates in a spring contact beam portion. The leadframe is attached to the substrate (for example, by fitting a hole in each lead over a corresponding alignment and retaining pin and then thermally deforming the pin to hold the lead in place). An integrated circuit is press-fit down through the retaining clips such that pads on the face side of the integrated circuit contact and compress the spring contact beams of the leads. After the press-fit step, the retaining clips hold the integrated circuit in place. The resulting assembly is encapsulated. In a cutting and bending step, the leads are singulated and formed to have a desired shape. The resulting low-cost package involves no wire-bonding and no flip-chip bond bump forming steps.

Abstract: A processing technique facilitating the fabrication of the integrated circuit with microsprings at different vertical positions relative to a surface of a substrate is described. During the fabrication technique, microsprings are lithographically defined on surfaces of a first substrate and a second substrate. Then, a hole is created through a first substrate. Moreover, the integrated circuit may be created by rigidly mechanically coupling the two substrates to each other such that the microsprings on the surface of the second substrate are within a region defined at least in part by an edge around the hole. Subsequently, photoresist that constrains the microsprings on the surfaces of the two substrates may be removed. In this way, microsprings at the different vertical positions can be fabricated.