Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Abstract: A portable object connectable package for an electronic device comprises: semiconductor die package, having a top surface and an opposite bottom surface, and a connector body mechanically supported by the semiconductor die package. The bottom surface includes a plurality of connection elements for connecting to a printed circuit board. The connector body includes a plurality of resilient electrical connecting elements extending over the top surface for contacting with a portable object PO having a contacting area. The portable object connectable package is arranged to be coupled to a portable object positioner for removably positioning the contacting area of the portable object in contact with the plurality of resilient electrical connecting elements when the portable object is present in the portable object positioner.

Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.

Abstract: The semiconductor integrated circuit device includes: an active element, an interlayer insulting film, first and second metal patterns made of a first metal layer formed right above the active element, first and second buses made of a second metal layer formed right above the first metal layer, and contact pads provided on the first and second buses. The contact pad has a probe testing region and a bonding region.

Abstract: An insulative substrate includes a plurality of flexible retaining clips and a plurality of alignment and retaining pins. A metal leadframe includes a plurality of leads. Each lead terminates in a spring contact beam portion. The leadframe is attached to the substrate (for example, by fitting a hole in each lead over a corresponding alignment and retaining pin and then thermally deforming the pin to hold the lead in place). An integrated circuit is press-fit down through the retaining clips such that pads on the face side of the integrated circuit contact and compress the spring contact beams of the leads. After the press-fit step, the retaining clips hold the integrated circuit in place. The resulting assembly is encapsulated. In a cutting and bending step, the leads are singulated and formed to have a desired shape. The resulting low-cost package involves no wire-bonding and no flip-chip bond bump forming steps.

Abstract: An integrated circuit package system includes providing a plurality of substrates; inserting a receptor in one of the substrates, the receptor held in and not extending through the one of the substrates; inserting a conductive post in another of the substrates; mounting the one of the substrates and the another of the substrates over one another with the conductive post engaging the receptor to thermally interlock without a separate bonding material; and mounting an integrated circuit mounted on the one of the substrates or the another of the substrates.

Abstract: A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate and is electrically coupled to the bond pad. The bond pad structure further includes a first passivation layer over the first dielectric layer wherein the first passivation layer has at least a portion under a middle portion of the bond pad. At least part of an active circuit is located under the bond pad.

Abstract: An arrangement with an associated production method, of a power semiconductor module in a pressure contact embodiment and a cooling component. The module includes load terminals embodied as metal molded bodies with a flat portion and a contact device originating at the flat portion, disposed within a housing. Each flat portion is disposed parallel to, and spaced from, the surface of the substrate. Contact feet extend from the flat portions to conductor tracks on the substrate. A pressure plate exerts pressure on the load terminals to hold them in place and establish electrical contact between the contact feet and the conductor tracks, while also establishing thermal contact between the load terminals and the cooling component. The cooling component, the housing, and the pressure plate form a first unit, which is mechanically decoupled from a second unit comprising the substrate and the load terminals.

Abstract: A power semiconductor module in a pressure contact embodiment, for disposition on a cooling component, in which load terminals are formed as metal molded bodies, each with at least one flat portion and having a plurality of contact feet extending from the flat portion. Each flat portion of the load terminal is disposed parallel to, and spaced from, the substrate. The contact feet also extend from the flat portion to the substrate, where they form the contacts of the terminal elements. A molded insulation body is disposed between the flat portions of the load terminals and the substrate, and this molded insulation body has recesses for permitting the passage therethrough of the contact feet.

Abstract: A nanowire device includes a nanowire formed between two surfaces, and a gap formed at a predetermined location in the nanowire.

Abstract: A stacked electronics module comprises a first layer including a first substrate having a front side and a backside, a first electrical interconnect layer disposed on the first substrate and a first electronic device disposed on the front side of the first substrate. In addition, the stacked electronics module comprises a second layer including a second substrate having a front side and a backside, a second electrical interconnect layer disposed on the second substrate and a second electronic device disposed on the front side of the second substrate.

Abstract: Resilient spring contacts for use in wafer test probing are provided that can be manufactured with a very fine pitch spacing and precisely located on a support substrate. The resilient contact structures are adapted for wire bonding to an electrical circuit on a space transformer substrate. The support substrates with attached spring contacts can be manufactured together in large numbers and diced up and tested before attachment to a space transformer substrate to improve yield. The resilient spring contacts are manufactured using photolithographic techniques to form the contacts on a release layer, before the spring contacts are epoxied to the support substrate and the release layer removed. The support substrate can be transparent to allow alignment of the contacts and testing of optical components beneath. The support substrate can include a ground plane provided beneath the spring contacts for improved impedance matching.

Abstract: A method of fabricating a semiconductor component includes providing a prefabricated frame that includes metal traces and lead-through contacts. A semiconductor chip is mounted into the prefabricated frame such that the semiconductor chip is embedded within a rim of the prefabricated frame. Contact regions on a surface of the semiconductor chip are electrically connected with the metal traces of the prefabricated frame such that the contact regions are electrically coupled to the lead-through contacts via the metal traces.

Abstract: A microelectronic package includes a microelectronic element having faces, contacts and an outer perimeter, and a flexible substrate overlying and spaced from a first face of the microelectronic element, an outer region of the flexible substrate extending beyond the outer perimeter of the microelectronic element. The package includes a plurality of etched conductive posts exposed at a surface of the flexible substrate and being electrically interconnected with the microelectronic element, wherein at least one of the conductive posts is disposed in the outer region of the flexible substrate, and a compliant layer disposed between the first face of the microelectronic element and the flexible substrate, wherein the compliant layer overlies the at least one of the conductive posts that is disposed in the outer region of the flexible substrate.

Abstract: An electronic device includes: a semiconductor chip that includes an integrated circuit, a plurality of electrodes electrically connected to the integrated circuit, and a passivation film formed in a manner that at least a portion of each of the plurality of electrodes is exposed; a resin layer that is formed on the passivation film; a plurality of wirings, each of the plurality of wirings extending from a top surface of each of the plurality of electrodes to a top surface of the resin layer and electrically connected to each of the plurality of electrodes, respectively; a wiring substrate that has a wiring pattern opposing to and electrically connected to portions of the plurality of wirings above the resin layer; and a hardened adhesive resin that is placed between the semiconductor chip and the wiring substrate, wherein the adhesive resin internally has a residual stress that is generated by contraction at the time of hardening the adhesive resin, and a portion of the adhesive resin is disposed between a p

Abstract: Wire bonds connect current-carrying edges of high-frequency planar conductors to other electrical devices. In one embodiment, planar transmission lines are interconnected using two wire bonds. One bond wire extends from an edge of a first center conductor to a corresponding edge of a second center conductor, and a second bond wire extends from the other edge of the first center conductor to the other edge of the second center conductor. Embodiments include center conductors at different heights and having different widths, and different electrical devices, such as semiconductor integrated circuits. In a particular embodiment, ball bonding is used. In some embodiments, a tack bond is included after a ball bond to allow closer attachment of the bond wire to the edge of the conductor.

Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.

Abstract: A compliant interconnect with two or more layers of metal of two or more compositions with internal stresses is described herein.

Abstract: A method of mounting a semiconductor chip in which an IC chip is mounted by filling a gap between the chip and a substrate with adhesive which functions as an underfill. The fillet of the underfill is made to have a preferable shape. To accomplish this, a head IC chip provided with bumps is placed on a suspension that is covered with the underfill adhesive and is provided with pads. A bonding tool presses the head IC chip and applies ultrasonic oscillation to the head IC chip, so that the bumps are properly bonded to the pads. When the head IC chip is pressed and subjected to ultrasonic oscillation, the ultraviolet rays 108 are emitted so as to harden the peripheral portion 151a of the adhesive 151 spread out between the head IC chip 11 and the suspension 12.

Abstract: Aspects of the current invention are directed to a method of mounting a flexible printed circuit and a manufacturing method of an electric optical device. Each of the methods form semiconductor elements and first terminal portions for electrically connecting the semiconductor elements and the outside of the board. These terminal portions have are completely or partially covered with an organic film 37 and are pressed into second terminal portion on the flexible printed circuit from the direction above the organic film thereby creating an electrical connection. Optionally, an anisotropic conductive paste or anisotropic conductive film may be provided between the second terminal portion and the organic film.

Abstract: An article of manufacture and system, as well as fabrication methods therefore, may include a plurality of lands disposed on a surface of a substrate wherein the lands are oriented at an angle to the surface of the substrate and further wherein the substrate is formed of conductive layers that are formed such that a non-conductive layer does not interpose between the conductive layers and their coupling.

Abstract: An apparatus and method for incorporating discrete passive components into an integrated circuit package. A metal layer is formed over a surface of a substrate. A layer of photosensitive material is then formed over the metal layer. Using standard photolithographic processing, a pattern is formed with the photosensitive material to expose at least one region of the metal layer. The remaining photosensitive material protects the underlying metal during metal etching. The substrate is then subjected to a metal etching process to remove the metal that is not protected by the photosensitive material. The remaining photosensitive material is then removed from each remaining area of the metal layer. The discrete passive components can then be attached to the formed metal lands.

Abstract: A integrated circuit housing includes a first clamping hardware, a second clamping hardware operatively connected to the first clamping hardware, and an integrated circuit stack comprising a top portion and a bottom portion, wherein the first clamping hardware contacts the top portion and the second clamping hardware contacts the bottom portion, and wherein a first shim is interposed between the bottom portion and the second clamping hardware.

Abstract: A microelectronic device and method for manufacture. In one embodiment, two microelectronic substrates are directly bonded to each other without an intermediate adhesive material. For example, each microelectronic substrate can include a first surface, a second surface opposite the first surface, and a functional microelectronic feature coupled to a connection terminal of the microelectronic substrate. The connection terminals can be coupled to a support member, such as a leadframe or a printed circuit board, with the bond plane between the microelectronic substrates either aligned with or transverse to the support member. The microelectronic substrates can be enclosed in a protective packaging material that can include a transparent window to allow selected radiation to strike one or the other of the microelectronic substrates.

Abstract: A device comprises a first substrate, a second substrate and a compliant element. The compliant element is composed of a first, compliant material between the first substrate and the second substrate and has a side surface coated at least in part with a layer of a second material. The compliant element exhibits deformation consistent with the first substrate and a second side having been pressed together. In some embodiments, the second material is electrically conductive such that the compliant element provides a reliable electrical connection between the substrates. In other embodiments, the second material increases the hermeticity of the compliant element such that the compliant element provides a better hermetic seal between the substrates.

Abstract: A mounting method includes the steps of, after positioning objects being bonded relative to each other, moving a movable wall positioned there around until coming into contact with one object holding means to form a local chamber having a local enclosed space, enclosing both objects in the chamber, reducing the pressure in the chamber, moving the object holding means in a direction for reducing the volume of the chamber and moving the movable wall following the movement of the object holding means, and bonding both objects to each other by pressing. Since the bonding part and the vicinity of the bonding part can be locally and efficiently enclosed from the surroundings, and the local chamber can vary the shape of the enclosed space with the bonding operation while maintaining the enclosed state even at the time of bonding.

Abstract: A bonding structure of device packaging includes a first substrate and a second substrate. The surfaces of the first substrate have metal pads and a first bonding layer connected to the second substrate whose surfaces have a second bonding layer and electrodes. The first bonding layer is combined with the second bonding layer, and the metal pads are in electrical communications with the electrodes. The second substrate may be a flexible substrate to decrease the strain between the first substrate and the second substrate.

Abstract: A sensor device includes a sensor chip and a bonding wire being fixed on a substrate. The sensor device is manufactured by using a binding material made of an adhesive containing a foaming agent that evaporates upon exposure to heat. The binding material reduces its elasticity after a wire bonding process because voids being functional as a cushion are formed by evaporation of the foaming agent.

Abstract: A gate electrode (1a) is formed on the outer peripheral step portion (1?) of a semiconductor substrate (1) so as to face a pressure-contact supporting block (6), and a convex contacting portion (1g) is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (1d). The convex contacting portion (1g) is formed of a convex portion integral with the gate electrode or formed of another gate electrode (1a?).

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a pillar and a routing line, and a ground plane. The pillar is press-fit into an opening in the ground plane, and the ground plane is electrically connected to the pad.

Abstract: A tape circuit substrate comprises a base film made of an insulating material, and a wiring pattern layer which is formed on the base film and has first leads that are connected to electrode pads arranged near a periphery of a semiconductor chip and second leads that are connected to electrode pads arranged near the center of the semiconductor chip. The semiconductor chip package comprises a semiconductor chip electrically bonded to the tape circuit substrate through chip bumps. In such a case, each of the leads is configured such that a tip end thereof to be bonded to the electrode pad has a width larger than that of a body portion thereof. According to the present invention, since the interval between the lead and the electrode pad can be made even narrower, a fine pitch semiconductor device can be realized.

Abstract: A wiring terminal is formed on a wiring substrate, and an electrode is formed on a semiconductor device. The width of the wiring terminal is smaller than the width of the electrode. When the semiconductor device is mounted on the wiring substrate, the wiring terminal becomes embedded in the electrode due to applied pressure.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a pillar and a routing line, and a ground plane. The pillar is press-fit into an opening in the ground plane, and the ground plane is electrically connected to the pad.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, then electrically connecting a conductive trace that includes a pillar and a routing line to the pad, and then press-fitting the pillar into an opening in a ground plane, thereby electrically connecting the ground plane and the pad.

Abstract: An adhesive film for manufacturing a semiconductor device comprising a thermosetting adhesive layer and a heat-resistant backing layer, wherein the adhesive film is applied to a method for manufacturing a semiconductor device, comprising the steps of (a) embedding at least a part of a conductor in the adhesive film to form a conductor adhered thereto; (b) mounting a semiconductor chip on the conductor; (c) connecting the semiconductor chip to the conductor; (d) encapsulating the semiconductor chip with an encapsulation resin; and (e) removing the adhesive film therefrom. The adhesive film can be suitably used for manufacturing a semiconductor device having a so-called standoff wherein a part of a conductor is projecting from an encapsulation resin.

Abstract: A surface protection film which comprises a substrate layer and an adhesive layer, and of which the electrostatic charge by peeling from an adherend is from +0.01 to ?0.01 nC/mm2.

Abstract: A method of wire bonding, a semiconductor chip, and a semiconductor package provides stitch-stitch bonds of a wire on a bond pad of a chip as well as on a bond position of a substrate. A ball-stitch bump is formed on an end of the wire extending from a capillary or provided on the bond pad of the chip. A ball-stitch bump is formed on the bond pad of the chip by pressing down the ball of the wire on the bond pad. A ball-stitch stitch bond of the wire is formed on the ball-stitch bump by pressing down the wire on the ball-stitch bump. The capillary is moved from the bond pad to the bond position, while loosening the wire. A stitch bond of the wire is formed on the bond position by pressing down the wire on the bond position, and then separated from the wire within the capillary. The method of wire bonding, a semiconductor chip, and a semiconductor package can reduce or minimize a moving path of the capillary and provide more effective wire bonding.

Abstract: The stackable power semiconductor module comprises electrically conductive base plates, an electrically conductive cover plate and a plurality of semiconductor chips. The semiconductor chips are arranged in groups of several on separate base plates in preassembled submodules. The base plates are moveable towards the cover plate. The submodules are paralleled inside the module housing. The submodules are fully testable according to their current ratings. Altering the number of submodules paralleled inside the housing can vary the overall current rating of a module.

Abstract: A gate electrode (1a) is formed on the outer peripheral step portion (1?) of a semiconductor substrate (1) so as to face a pressure-contact supporting block (6), and a convex contacting portion (1g) is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (1d). The convex contacting portion (1g) is formed of a convex portion integral with the gate electrode or formed of another gate electrode (1a?).

Abstract: The invention relates to an electronic chip component and a method for fabricating the chip component with a semiconductor chip having an integrated circuit therein. Contact surfaces are on the active surface of the semiconductor chip. The contact surfaces of the integrated circuit have a contact layer consisting of pressure contact material, which protrudes beyond the level of the top non-conductive layer. The active surface of the semiconductor chip includes a meltable glue layer that is adapted to the height of the contact layer.

Abstract: A voltage-driven power semiconductor device includes a voltage-driven IEGT chip, a collector electrode plate, an emitter electrode plate, and an inductance material. The collector electrode plate is connected to the collector of the IEGT chip, and press-contacts the IEGT chip from its collector side. The emitter electrode plate press-contacts the IEGT chip from its emitter side. The inductance material has an inductance component and connects the emitter of the IEGT chip and the emitter electrode plate. In the voltage-driven power semiconductor device having this arrangement, an induced electromotive force is generated in the inductance material arranged between the emitter of the IEGT chip and the emitter electrode plate. This induced electromotive force can suppress a steep current change (di/dt) upon an OFF operation, and can further suppress a steep voltage change (dv/dt) caused by the current change (di/dt).

Abstract: A mounting structure for a semiconductor die that reduces die attach strain within the die attach material without sacrificing the electrical and thermal characteristics of the package. In one embodiment, the mounting structure comprises a die attach metallization layer, a solder mask, and a layer of die attach material. The solder mask forms a solder pattern over the top surface of the die attach metallization layer. The solder pattern covers a portion of the die attach metallization layer to create multiple exposed areas of the die attach metallization layer. Each exposed area is separated by the solder mask and is located under the semiconductor die when the semiconductor die is secured to the mounting structure. A layer of die attach material covers the solder pattern and fills in each one of the exposed areas to form a semiconductor die mounting surface. In another embodiment, the die attach metallization layer is divided into multiple, spaced-apart die attach pads that are electrically coupled together.

Abstract: An electronic device and a method for producing the electronic device which has at least one microscopically small contact area for an electronic circuit having interconnects that are on a surface of a substrate. A three-dimensionally extending microscopically small contact element is integrally one-piece connected to the contact area.

Abstract: An assembly having a surface mounted electronic device mounted onto a printed circuit board and a thermoplastic adhesive applied to the surface mounted electronic device facing the printed circuit board and providing for a gap between the thermoplastic adhesive and the printed circuit board. The assembly is heated at solder reflow temperatures to at least soften the thermoplastic adhesive sufficiently to flow across the gap and provide a thermoplastic adhesive joint between the surface mounted electronic device and the printed circuit board.

Abstract: Electronic packages with uninsulated portions of copper circuits protected with coating layers having thicknesses that are suitable for soldering without fluxing and are sufficiently frangible when being joined to another metal surface to obtain metal-to-metal contact between the surfaces.

Abstract: An apparatus to retain an assembled component on one side of a double-sided printed circuit board during reflow of other components subsequently positioned on an opposite side of the double-sided printed circuit board and methods for manufacturing and using the same. The retainer includes a heat-expandable member and a retainer member. Being formed from a heat-expandable material, the heat-expandable member is coupled with the retainer member and is disposed about a periphery thereof. The retainer member is configured to be coupled with a component and, when the component is assembled onto a double-sided printed circuit board, to be received by an opening formed in the double-sided printed circuit board. The heat-expandable member is configured to expand during assembly of the component, engaging an inner surface that defines the opening. Thereby, the component is retained and supported when the double-sided printed circuit board is subsequently inverted, populated, and reflowed.

Abstract: A method is provided for forming a wafer stack. This may include providing a first wafer having a first plurality of metalized trenches on a surface of the first wafer. A second wafer may be provided having a second plurality of metalized trenches on a surface of the second wafer facing the first wafer. The first plurality of metalized trenches may be solder bonded to the second plurality of metalized trenches.

Abstract: An electronic component including an element main body section for performing an electrical function and a terminal section for electrically connecting the element main body section to a conductive member of an external device, the electronic component comprises a pair of sections arranged above the terminal section and opposite to each other in a stacking direction of the electronic component and a distance between the sections corresponding to a maximum thickness of the electronic component.

Abstract: A TAB tape for a semiconductor package is provided. The TAB tape provides number of test pad configuration for reducing the area of the test pad area on a TAB tape to increases the number of packages that may be prepared from a length of TAB tape. The TAB tape comprises a base film having a chip mounting area for mounting at least one semiconductor device and a wiring pattern formed on the base film with test pads formed at the ends of the output terminal patterns. A predetermined number of the test pads are arranged in rows form a group wherein the number of rows is less than the number of test pads in the group. Groups of the test pads are consecutively arranged across the TAB tape to provide the number of test pads necessary for testing the semiconductor device(s).

Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In an application requiring very fine pitch between bond pads, the probe regions (14) and active regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.