Active Material Comprising Refractory, Transition, Or Noble Metal Or Metal Compound, E.g., Alloy, Silicide, Oxide, Nitride (epo) Patents (Class 257/E21.006)
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Patent number: 8629467Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.Type: GrantFiled: June 26, 2012Date of Patent: January 14, 2014Assignee: Renesas Electronics CorporationInventors: Takamitsu Kanazawa, Toshiyuki Hata
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Patent number: 8624313Abstract: A semiconductor device includes a semiconductor substrate, a non-volatile semiconductor memory element formed over the semiconductor substrate, including a variable resistance element including a laminate comprising a first electrode, a variable resistance layer, and a second electrode, and a volatile semiconductor memory element formed over the semiconductor substrate, including a capacitance element including a laminate comprising a third electrode, a dielectric layer including a same material as the variable resistance layer, and a fourth electrode.Type: GrantFiled: September 6, 2011Date of Patent: January 7, 2014Inventor: Kazuhiko Kajigaya
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Patent number: 8618668Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.Type: GrantFiled: October 22, 2012Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shi Liu, Chen-Hua Yu
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Patent number: 8604530Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: GrantFiled: September 14, 2012Date of Patent: December 10, 2013Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Patent number: 8604527Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: GrantFiled: September 14, 2012Date of Patent: December 10, 2013Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Patent number: 8598643Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.Type: GrantFiled: September 18, 2011Date of Patent: December 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kaori Kawasaki, Yoshiaki Fukuzumi, Masaru Kito, Tomoko Fujiwara, Takeshi Imamura, Ryouhei Kirisawa, Hideaki Aochi
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Patent number: 8597978Abstract: A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.Type: GrantFiled: May 17, 2012Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Kurt Wachtler, Margaret Rose Simmons-Matthews
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Patent number: 8580670Abstract: A method of producing a thin film using plasma enhanced chemical vapor deposition, including the steps of supplying a cation species to a substrate region when there is at most a relatively low flux of a plasma based anion species in the substrate region, and supplying the plasma based anion species to the substrate region when there is at most a relatively low flux of the cation species in the substrate region. This enables delivery of gaseous reactants to be separated in time in PECVD and/or RPECVD based film growth systems, which provides a significant reduction in the formation of dust particles for these plasma based film growth techniques.Type: GrantFiled: February 10, 2010Date of Patent: November 12, 2013Inventor: Kenneth Scott Alexander Butcher
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Patent number: 8581421Abstract: According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.Type: GrantFiled: December 16, 2011Date of Patent: November 12, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Noriyoshi Shimizu, Akio Rokugawa, Hirokazu Yoshino
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Patent number: 8574985Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.Type: GrantFiled: March 3, 2011Date of Patent: November 5, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Xiangxin Rui, Sunil Shanker, Sandra Malhotra, Imran Hashim, Edward Haywood
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Patent number: 8574926Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.Type: GrantFiled: September 18, 2011Date of Patent: November 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Noma, Hiroshi Watanabe, Shinya Kobayashi
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Patent number: 8569105Abstract: A method and apparatus is provided for forming a resistive memory device having good adhesion among the components thereof. A first conductive layer is formed on a substrate, and the surface of the first conductive layer is treated to add adhesion promoting materials to the surface. The adhesion promoting materials may form a layer on the surface, or they may incorporate into the surface or merely passivate the surface of the first conductive layer. A variable resistance layer is formed on the treated surface, and a second conductive layer is formed on the variable resistance layer. Adhesion promoting materials may also be included at the interface between the variable resistance layer and the second conductive layer.Type: GrantFiled: April 25, 2012Date of Patent: October 29, 2013Assignee: Applied Materials, Inc.Inventors: Siu F. Cheng, Deenesh Padhi
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Patent number: 8563336Abstract: Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.Type: GrantFiled: December 23, 2008Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee, John C. Malinowski, Anthony K. Stamper
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Patent number: 8551836Abstract: A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.Type: GrantFiled: May 16, 2011Date of Patent: October 8, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Wensheng Wang
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Patent number: 8541824Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: GrantFiled: July 19, 2012Date of Patent: September 24, 2013Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Patent number: 8541828Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer includes at least a portion of rutile titanium oxide.Type: GrantFiled: November 5, 2012Date of Patent: September 24, 2013Assignee: Intermolecular, Inc.Inventors: Imran Hashim, Edward L. Haywood, Sandra G. Malhotra, Xiangxin Rui, Sunil Shanker
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Patent number: 8535953Abstract: Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.Type: GrantFiled: January 13, 2012Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: David W. Abraham, Solomon Assefa, Eugene J. O'Sullivan
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Patent number: 8536031Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.Type: GrantFiled: February 19, 2010Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Kuang-Jung Chen, Matthew E. Colburn, Dario L. Goldfarb, Stefan Harrer, Steven J. Holmes, Pushkara Varanasi
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Patent number: 8530360Abstract: A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors have an aspect ratio of height to diameter of 2 to 1 or greater, and a fine pitch center-to-center. The connector end (110a) remote from the terminal is covered by a film (130) of a sintered paste including a metallic matrix embedded in a first polymeric compound. Further a second body (103) having metallic pads (140) facing the respective terminals (102). Each connector film (130) is in contact with the respective pad (140), whereby the first body (101) is spaced from the second body (103) with the connector columns (110) as standoff. A second polymeric compound (150) is filling the space of the standoff.Type: GrantFiled: January 25, 2011Date of Patent: September 10, 2013Assignee: Texas Instruments IncorporatedInventor: Abram M. Castro
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Patent number: 8530320Abstract: A thin film metal resistor is provided that includes an in-situ formed metal nitride layer that is formed in a lower region of a deposited metal nitride layer. The in-situ formed metal nitride layer, together with the overlying deposited metal nitride layer, from a thin film metal resistor which has a nitrogen content that is greater than 60 atomic % nitrogen. The in-situ formed metal nitride layer is present on a nitrogen enriched dielectric surface layer. In accordance with the present disclosure, the in-situ formed metal nitride layer is formed during and/or after formation of the deposited metal nitride layer by reacting metal atoms from the deposited metal nitride layer with nitrogen atoms present in the nitrogen enriched dielectric surface layer. The presence of the in-situ formed metal nitride layer in the lower region of the metal nitride layer provides a two-component metal resistor having greater than 60 atomic % nitrogen therein.Type: GrantFiled: June 8, 2011Date of Patent: September 10, 2013Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Daniel C. Edelstein
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Patent number: 8525304Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.Type: GrantFiled: May 18, 2011Date of Patent: September 3, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
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Patent number: 8525353Abstract: In a system for providing temporary or permanent connection of an integrated circuit die to a base substrate using electrical microsprings, a thermal element is provided that assists with cooling of the pad structure during use. The thermal element may be formed of the same material and my similar processes as the microsprings. The thermal element may be one or more block structures or one or more thermal microsprings. The thermal element may be provided with channels to contain and/or direct the flow of a thermal transfer fluid. Cooling of components associated with the pad structure (e.g., ICs) may be provided.Type: GrantFiled: December 19, 2011Date of Patent: September 3, 2013Assignee: Palo Alto Research Center IncorporatedInventors: Eugene M. Chow, Eric J. Shrader, John S. Paschkewitz
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Patent number: 8524602Abstract: The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.Type: GrantFiled: September 7, 2010Date of Patent: September 3, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Meng-Jen Wang
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Patent number: 8525289Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.Type: GrantFiled: April 12, 2012Date of Patent: September 3, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Richard Carter, Martin Trentzsch, Sven Beyer, Rohit Pal
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Patent number: 8513057Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a routable layer having a column; mounting an integrated circuit structure in direct contact with the column; and forming a gamma connector to electrically connect the column to the integrated circuit structure.Type: GrantFiled: September 16, 2011Date of Patent: August 20, 2013Assignee: Stats Chippac Ltd.Inventors: Oh Han Kim, Ki Youn Jang, DaeSik Choi, DongSoo Moon
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Patent number: 8513680Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.Type: GrantFiled: September 16, 2011Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Daniel Kim, Jae-sung You, Jong-kil Park
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Patent number: 8513717Abstract: A first driver transistor includes a first gate insulating film that surrounds a periphery of a first island-shaped semiconductor, a first gate electrode having a first surface that is in contact with the first gate insulating film, and first and second first-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first island-shaped semiconductor, respectively. A first load transistor includes a second gate insulating film having a first surface that is in contact with a second surface of the first gate electrode, a first arcuate semiconductor formed so as to be in contact with a portion of a second surface of the second gate insulating film, and first and second second-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first arcuate semiconductor, respectively. A first gate line extends from the first gate electrode and is made of the same material as the first gate electrode.Type: GrantFiled: December 16, 2011Date of Patent: August 20, 2013Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 8502291Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.Type: GrantFiled: April 20, 2011Date of Patent: August 6, 2013Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 8501623Abstract: A semiconductor device includes an electrode having a metal silicide layer and a metal alloy layer, and a data storage element formed on the electrode. The metal silicide layer has a concave surface to correspond to a convex surface of the metal alloy layer such that the concave surface of the metal silicide layer and the convex surface of the metal alloy layer form a curved boundary.Type: GrantFiled: July 22, 2010Date of Patent: August 6, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Gyuhwan Oh, Young-Lim Park, Soonoh Park, Dongho Ahn, Jinil Lee
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Patent number: 8497208Abstract: A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.Type: GrantFiled: September 16, 2010Date of Patent: July 30, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Michie Sunayama, Yoshiyuki Nakao, Noriyoshi Shimizu
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Patent number: 8492862Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.Type: GrantFiled: November 12, 2010Date of Patent: July 23, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Keiji Sato
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Patent number: 8492264Abstract: A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.Type: GrantFiled: August 1, 2011Date of Patent: July 23, 2013Assignee: STMicroelectronics (Crolles 2) SASInventor: Patrick Vannier
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Patent number: 8486839Abstract: A method for tiling selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and adding tiling features on a metal layer above the selected isolated vias and within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.Type: GrantFiled: May 24, 2011Date of Patent: July 16, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Douglas M. Reber, Lawrence N. Herr
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Patent number: 8481381Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.Type: GrantFiled: September 14, 2011Date of Patent: July 9, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
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Patent number: 8476764Abstract: A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; and a plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.Type: GrantFiled: September 18, 2011Date of Patent: July 2, 2013Assignee: Nanya Technology Corp.Inventors: Tse-Yao Huang, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8476646Abstract: Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air.Type: GrantFiled: November 12, 2010Date of Patent: July 2, 2013Assignee: LG Innotek Co., Ltd.Inventor: Hyo Kun Son
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Patent number: 8476719Abstract: Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.Type: GrantFiled: May 18, 2011Date of Patent: July 2, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
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Patent number: 8471234Abstract: A multilayer memristive device includes a first electrode; a second electrode; a first memristive region and a second memristive region which created by directional ion implantation of dopant ions and are interposed between the first electrode and the second electrode; and mobile dopants which move within the first memristive region and the second memristive region in response to an applied electrical field.Type: GrantFiled: January 20, 2009Date of Patent: June 25, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: William M. Tong, Nathaniel J. Quitoriano, Duncan Stewart, Philip J. Kuekes
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Patent number: 8466064Abstract: A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.Type: GrantFiled: November 12, 2010Date of Patent: June 18, 2013Assignee: Macronix International Co., Ltd.Inventors: Yu-Fong Huang, Tzung-Ting Han, Wen-Pin Lu
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Patent number: 8466006Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.Type: GrantFiled: February 1, 2012Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Bipin Rajendran, Alejandro G. Schrott, Yu Zhu
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Patent number: 8466069Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can form a plurality of grooves extending in a first direction on a semiconductor substrate. The method can form an insulating layer on the inner face of the groove and on the top face of the semiconductor substrate. The method can deposit a first conductive layer on the insulating layer so as to fill in the groove. The method can deposit a second conductive layer on the first conductive layer. The method can form a hard mask in a region including part of a region immediately above the groove on the second conductive layer. The method can form a columnar body including the hard mask and the second conductive layer by etching the second conductive layer using the hard mask as a mask.Type: GrantFiled: September 14, 2011Date of Patent: June 18, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Toshiyuki Sasaki
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Patent number: 8461565Abstract: An electrically actuated device comprises an active region disposed between a first electrode and a second electrode, a fixed dopant distributed within the active region, and at least one type of mobile dopant situated near an interface between the active region and the second electrode.Type: GrantFiled: January 29, 2009Date of Patent: June 11, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Sagi Varghese Mathai, Michael Renne Ty Tan, Wei Wu, Shih-Yuan (SY) Wang
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Patent number: 8461012Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.Type: GrantFiled: February 26, 2010Date of Patent: June 11, 2013Assignee: Freescale Semiconductor, Inc.Inventor: Vishal P. Trivedi
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Patent number: 8455981Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.Type: GrantFiled: May 7, 2010Date of Patent: June 4, 2013Assignee: The Invention Science Fund I, LLCInventors: Jeffrey A. Bowers, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Clarence T. Tegreene, Tatsushi Toyokuni, Richard N. Zare
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Patent number: 8455365Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.Type: GrantFiled: May 19, 2011Date of Patent: June 4, 2013Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
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Patent number: 8445919Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof, and the package structure includes: a die including a first side and a second side opposite to the first side; a first insulating layer on the first side of the die; at least two wires which are arranged on the insulating layer and electrically isolated from each other; bumps which are arranged on the wires and adapted to be electrically connected correspondingly with electrodes of a bare chip of the light emitting diode; at least two discrete lead areas on the second side of the die; and leads in the lead areas, electrically isolated from each other and electrically connected correspondingly with the wires.Type: GrantFiled: February 19, 2010Date of Patent: May 21, 2013Assignee: China Wafer Level CSP LtdInventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang
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Patent number: 8441027Abstract: Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a substrate including a plurality of patterns, each pattern including three protrusion parts, a plurality of spaces formed between the patterns, and a light emitting device structure over the patterns and the spaces. Each space includes a medium having a refractive index different from a refractive index of the light emitting device structure.Type: GrantFiled: November 12, 2010Date of Patent: May 14, 2013Assignee: LG Innotek Co., Ltd.Inventor: Chang Bae Lee
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Patent number: 8436426Abstract: The present disclosure is directed to a thin film resistor having a first resistor layer having a first temperature coefficient of resistance and a second resistor layer on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 50 and 150 angstroms and the second resistor layer may have a thickness in the range of 20 and 50 angstroms.Type: GrantFiled: August 24, 2010Date of Patent: May 7, 2013Assignee: STMicroelectronics PTE Ltd.Inventors: Olivier Le Neel, Calvin Leung
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Patent number: 8426255Abstract: A method for manufacturing a semiconductor package structure is disclosed. In one embodiment, the method includes the steps of forming a plurality of conductive pastes on a matrix lead frame with a groove located within a predetermined distance from each conductive paste on the lead; partially curing the conductive pastes so that the conductive pastes are in a semi-cured state; preparing at least one chip with a plurality of bumps thereon; electrically connecting the chip and the lead by implanting the bumps into the semi-cured conductive pastes, wherein the groove on the lead of the matrix lead frame is configured to receive overflowed semi-cured conductive pastes; curing the semi-cured conductive pastes to completely secure the bumped chip; and forming an encapsulating material covering the lead frame and the chip. The method can also be applied in pre-molded lead frame package.Type: GrantFiled: September 14, 2011Date of Patent: April 23, 2013Assignee: Chipmos Technologies, Inc.Inventor: Geng-Shin Shen
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Patent number: 8426925Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.Type: GrantFiled: November 12, 2010Date of Patent: April 23, 2013Assignee: Nanya Technology Corp.Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai