Active Material Comprising Organic Conducting Material, E.g., Conducting Polymer (epo) Patents (Class 257/E21.007)
  • Patent number: 10269838
    Abstract: A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including forming a germanium-silicon layer for the second group of photodiodes on a first semiconductor donor wafer; defining a first interconnect layer on the germanium-silicon layer; defining integrated circuitry for controlling pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer; bonding the first interconnect layer with the second interconnect layer; defining the pixels of an image sensor array on a second semiconductor donor wafer; defining a third interconnect layer on the image sensor array; and bonding the third interconnect layer with the germanium-silicon layer.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: April 23, 2019
    Assignee: Artilux Corporation
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
  • Patent number: 10186477
    Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 22, 2019
    Assignee: General Electric Company
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
  • Patent number: 10056415
    Abstract: A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including forming a germanium-silicon layer for the second group of photodiodes on a first semiconductor donor wafer; defining a first interconnect layer on the germanium-silicon layer; defining integrated circuitry for controlling pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer; bonding the first interconnect layer with the second interconnect layer; defining the pixels of an image sensor array on a second semiconductor donor wafer; defining a third interconnect layer on the image sensor array; and bonding the third interconnect layer with the germanium-silicon layer.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: August 21, 2018
    Assignee: Artilux Corporation
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
  • Patent number: 9991113
    Abstract: A buffer layer is employed to fabricate diamond membranes and allow reuse of diamond substrates. In this approach, diamond membranes are fabricated on the buffer layer, which in turn is disposed on a diamond substrate that is lattice-matched to the diamond membrane. The weak bonding between the buffer layer and the diamond substrate allows ready release of the fabricated diamond membrane. The released diamond membrane is transferred to another substrate to fabricate diamond devices, while the diamond substrate is reused for another fabrication.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: June 5, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Jeehwan Kim, Dirk Robert Englund, Mark A. Hollis, Travis Wade, Michael Geis, Richard Molnar
  • Patent number: 9954016
    Abstract: An image sensor array including a carrier substrate; a first group of photodiodes coupled to the carrier substrate, where the first group of photodiodes include a first photodiode, and where the first photodiode includes a semiconductor layer configured to absorb photons at visible wavelengths and to generate photo-carriers from the absorbed photons; and a second group of photodiodes coupled to the carrier substrate, where the second group of photodiodes include a second photodiode, and where the second photodiode includes a germanium-silicon region fabricated on the semiconductor layer, the germanium-silicon region configured to absorb photons at infrared or near-infrared wavelengths and to generate photo-carriers from the absorbed photons.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: April 24, 2018
    Assignee: Artilux Corporation
    Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
  • Patent number: 9865570
    Abstract: Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally adjacent to a stack of dies positioned on the first die. The stack of dies electrically couples the first die to an uppermost die, and a thermally conductive pillar extends through the molding compound from the first die to an upper surface of the molding compound. The thermally conductive pillar is electrically isolated from the stack of dies and the uppermost die. The thermally conductive pillar laterally abuts and contacts the molding compound.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke G. England, Kathryn C. Rivera
  • Patent number: 9842825
    Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
  • Patent number: 9666559
    Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F; “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: May 30, 2017
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Hong Shen
  • Patent number: 9570384
    Abstract: A semiconductor device can include a substrate and a trace layer positioned in proximity to the substrate and including a trace for supplying an electrical connection to the semiconductor device. Conductive layers can be positioned in proximity to the trace layer and form a bond pad. A non-conductive thin film layer can be positioned between the trace layer and the conductive layers. The thin film layer can include a via to enable the electrical connection from the trace to the bond pad. A portion of the trace between the substrate and the plurality of conductive layers can have a beveled edge.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: February 14, 2017
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Lawrence H. White, Robert Vina, Terry Mcmahon, James R. Przybyla
  • Patent number: 9508565
    Abstract: The semiconductor package according to an exemplary embodiment includes: a substrate having a plurality of circuit layers and connection pads which are provided between a plurality of insulating layers; a plated tail part of which one end is electrically connected to the connection pad; a dicing part provided in contact with the other end of the plated tail part; a molded part provided on the substrate; and molded part vias provided on the connection pads and penetrating through the molded part.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: November 29, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hyun Lim, Do Jae Yoo, Eun Jung Jo
  • Patent number: 9343677
    Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, III, Gurtej S. Sandhu
  • Patent number: 9029228
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 12, 2015
    Assignees: SunEdision Semiconductor Limited (UEN201334164H), Kansas State University Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry, Phong Tuan Nguyen
  • Patent number: 8999862
    Abstract: Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Myoung Soo Kim, Jung Hyung Lee, Hyun Kyung Shim, Chang Il Oh
  • Patent number: 8999811
    Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
  • Patent number: 8994177
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8987922
    Abstract: A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Wen-Hsiung Lu, Hung-Jen Lin
  • Patent number: 8980689
    Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Soo Kwak, Cha-Jea Jo, Tae-Je Cho, Sang-Uk Han
  • Patent number: 8975734
    Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yueh-Ying Tsai, Fu-Di Tang, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8969134
    Abstract: A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Xavier F. Brun, Takashi Kumamoto, Sufi Ahmed
  • Patent number: 8969143
    Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daniel Kim, Jae-sung You, Jong-kil Park
  • Patent number: 8937020
    Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Keiji Sato
  • Patent number: 8932956
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8921139
    Abstract: A manufacturing method of an organic light emitting diode (OLED) display includes manufacturing a mother substrate including a plurality of panels formed with a plurality of anodes for each pixel and a test pad connected to each anode of the panel. The method further includes loading the mother substrate into a plasma chamber and applying a plasma voltage to the test pad of the mother substrate to perform a plasma surface treatment process. The test pad is applied with a different plasma voltage for each pixel.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jae-Young Lee
  • Patent number: 8916474
    Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef H•glauer
  • Patent number: 8912532
    Abstract: The invention relates to a top-emissive organic light-emitting diode (OLED) (10) arranged to emit light having different emission colors, comprising a multi-layered structure provided with a first electrode, a second electrode and a functional layer enabling light emission disposed between the first electrode and the second electrode, wherein thickness (H1, H2) of the functional layer is modulated by allowing at least a portion of the functional layer to interact with a thickness modulator (5a, 5b, 5c), wherein the functional layer comprises a hole injection layer or the electron injection layer.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: December 16, 2014
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
    Inventors: Dorothee Christine Hermes, Joanne Sarah Wilson, Petrus Alexander Rensing
  • Patent number: 8906772
    Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 9, 2014
    Assignee: UChicago Argonne, LLC
    Inventor: Anirudha V. Sumant
  • Patent number: 8906752
    Abstract: Ink compositions comprising polythiophenes and methicone that are formulated for inkjet printing the hole injecting layer (HIL) of an organic light emitting diode (OLED) are provided. Also provided are methods of inkjet printing the HILs using the ink compositions.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 9, 2014
    Assignee: Kateeva, Inc.
    Inventors: Inna Tregub, Rajsapan Jain, Michelle Chan
  • Patent number: 8884377
    Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo
  • Patent number: 8884310
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: November 11, 2014
    Assignees: SunEdison Semiconductor Limited (UEN201334164H), KSU Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry
  • Patent number: 8883571
    Abstract: A method of manufacturing a transistor includes: forming an oxide semiconductor film and a gate electrode on a substrate, the oxide semiconductor film having a channel region, and the gate electrode facing the channel region; and forming an insulating film covering the gate electrode and the oxide semiconductor film. Infiltration of moisture from the insulating film into the oxide semiconductor film is suppressed by the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventors: Narihiro Morosawa, Motohiro Toyota
  • Patent number: 8872194
    Abstract: An illumination device is disclosed. The illumination device includes a light source a pre-dip material that at least partially encapsulates the light source. The pre-dip material may include one or both of thermally-conductive particles and a cyclo-aliphatic composition. The pre-dip material may further include a resin and a hardener for the resin. Methods of manufacturing an illumination device are also disclosed.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 28, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Kum Soon Wong, Yean Chon Yaw, Kit Lai Wong
  • Patent number: 8853101
    Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Richard A. Farrell, Gerard M. Schmid, xU Ji
  • Patent number: 8847367
    Abstract: Provided are a hole-injecting material for an organic electroluminescent device (organic EL device) exhibiting high luminous efficiency at a low voltage and having greatly improved driving stability, and an organic EL device using the material. The hole-injecting material for an organic EL device is selected from benzenehexacarboxylic acid anhydrides, benzenehexacarboxylic acid imides, or N-substituted benzenehexacarboxylic acid imides. Further, the organic EL device has at least one light-emitting layer and at least one hole-injecting layer between an anode and a cathode arranged opposite to each other, and includes the above-mentioned hole-injecting material for an organic EL device in the hole-injecting layer. The organic EL device may contain a hole-transporting material having an ionization potential (IP) of 6.0 eV or less in the hole-injecting layer or a layer adjacent to the hole-injecting layer.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: September 30, 2014
    Assignee: Nippon Steel & Sumikin Chemical Co., Ltd.
    Inventors: Takayuki Fukumatsu, Ikumi Ichihashi, Hiroshi Miyazaki, Atsushi Oda
  • Patent number: 8846538
    Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 30, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bomy Chen, Long Ching Wang, Sychi Fang
  • Patent number: 8835247
    Abstract: A sensor array for detecting particles, the sensor array comprising a substrate having a plurality of holes, a plurality of electronic sensor chips each having a sensor active region being sensitive to the presence of particles to be detected, and an electric contacting structure adapted for electrically contacting the plurality of electronic sensor chips, wherein the plurality of electronic sensor chips and/or the electric contacting structure are connected to the substrate in such a manner that the plurality of holes in combination with the plurality of electronic sensor chips and/or the electric contacting structure form a plurality of wells with integrated particle sensors.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: September 16, 2014
    Assignee: NXP, B.V.
    Inventors: Michel De Langen, Ger Reuvers, Frans Meeuwsen
  • Patent number: 8835248
    Abstract: Techniques for fabricating metal lines in semiconductor systems are disclosed. The metal may be tungsten. A hybrid Chemical Vapor Deposition (CVD)/Physical Vapor Deposition (PVD) process may be used. A layer of tungsten may be formed using CVD. This CVD layer may be formed over a barrier layer, such as, but not limited to, TiN or WN. This CVD layer may completely fill some feature such as a trench or via. Then, a layer of tungsten may be formed over the CVD layer using PVD. The layers of tungsten may then be etched to form a wire or line. Techniques for forming metal wires using a hybrid CVD/PVD process may provide for low resistivity with a barrier metal, low surface roughness, and good gap filling.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: September 16, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Naoki Takeguchi
  • Patent number: 8816404
    Abstract: A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: August 26, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: YoungJoon Kim, SangMi Park, YongHyuk Jeong
  • Patent number: 8809132
    Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8803137
    Abstract: The present invention has been made in an effort to provide an organic light emitting display device comprising: a substrate; and subpixels formed on the substrate, each of the subpixels comprising an emission layer consisting of a first host layer made of a first host material, a mixed layer made of the first host material, a dopant material, and a second material, and a second host layer made of the second host material.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 12, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Seokjong Lee, Sehee Lee
  • Patent number: 8796149
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Patent number: 8790962
    Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 29, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Rui Huang, Yaojian Lin
  • Patent number: 8786027
    Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 22, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 8772826
    Abstract: It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer is comprised of a plurality of stacked semiconductor layers containing a chalcopyrite-based compound semiconductor. The semiconductor layers contain oxygen. A molar concentration of the oxygen in surfaces and their vicinities of the semiconductor layers where the semiconductor layers are stacked on each other is higher than average molar concentrations of the oxygen in the semiconductor layers.
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: July 8, 2014
    Assignee: KYOCERA Corporation
    Inventors: Hideaki Asao, Rui Kamada, Shuichi Kasai, Seiji Oguri, Isamu Tanaka, Nobuyuki Horiuchi, Kazumasa Umesato
  • Patent number: 8759164
    Abstract: In a method for manufacturing an integral imaging device, a layer of curable adhesive is first applied on a flexible substrate and half cured such that the curable adhesive is solidified but is capable of deforming under external forces. Then the curable adhesive is printed into a lenticular lens having a predetermined shape and size using a roll-to-roll processing device and fully cured such that the curable adhesive is capable of withstanding external forces to hold the predetermined shape and size. Last, a light emitting diode display is applied on the flexible substrate opposite to the lenticular lens such that an image plane of the light emitting diode display coincides with a focal plane of the lenticular lens.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: June 24, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chia-Ling Hsu
  • Patent number: 8753947
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: June 17, 2014
    Assignees: NthDegree Technologies Worldwide Inc, NASA
    Inventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 8753946
    Abstract: The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes depositing a first conductive medium within a plurality of channels of a base to form a plurality of first conductors; depositing within the plurality of channels a plurality of semiconductor substrate particles suspended in a carrier medium; forming an ohmic contact between each semiconductor substrate particle and a first conductor; converting the semiconductor substrate particles into a plurality of semiconductor diodes; depositing a second conductive medium to form a plurality of second conductors coupled to the plurality of semiconductor diodes; and depositing or attaching a plurality of lenses suspended in a first polymer over the plurality of diodes. In various embodiments, the depositing, forming, coupling and converting steps are performed by or through a printing process.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: June 17, 2014
    Assignees: NthDegree Technologies Worldwide Inc, NASA, an agency of the United States
    Inventors: William Johnstone Ray, Mark David Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 8723025
    Abstract: An organic device, including an organic compound having charge-transporting ability (i.e., transporting holes and/or electrons) and/or including organic light emissive molecules capable of emitting at least one of fluorescent light or phosphorescent light, has a charge transfer complex-contained layer including a charge transfer complex formed upon contact of an organic hole-transporting compound and molybdenum trioxide via a manner of lamination or mixing thereof, so that the organic hole-transporting compound is in a state of radical cation (i.e., positively charged species) in the charge transfer complex-contained layer.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: May 13, 2014
    Assignees: Rohm Co., Ltd., Mitsubishi Heavy Industries, Ltd.
    Inventors: Junji Kido, Toshio Matsumoto, Takeshi Nakada
  • Patent number: 8709957
    Abstract: A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Ibrahim Alhomoudi
  • Patent number: 8697579
    Abstract: A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Se-Myeong Jang, Gil-Sub Kim
  • Patent number: 8669187
    Abstract: A porous lift off layer facilitates removal of films from surfaces, such as semiconductors. A layer, with porosities typically larger than the film thickness is provided where no film is desired. The film is applied over the porous layer and also where it is desired. The porous material and the film are then removed from areas where film is not intended. The porous layer can be provided as a slurry, dried to open porosities, or fugitive particles within a field, which disassociate upon the application of heat or solvent. The film can be removed by etchant that enters through porosities that have arisen due to the film not bridging the spaces between solid portions. Etchant attacks both film surfaces. Particles may have diameters of four to ten times the film thickness. Particles may be silica, alumina and ceramics. Porous layers can be used in depressions or on flat surfaces.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: March 11, 2014
    Assignee: 1366 Technologies, Inc.
    Inventors: Emanuel M. Sachs, Andrew M. Gabor