Of Inductor (epo) Patents (Class 257/E21.022)
  • Patent number: 11289365
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device including an air gap underneath passive devices. The semiconductor device generally includes a substrate layer, a passive device layer, and a dielectric layer disposed between the substrate layer and the passive device layer, wherein the dielectric layer includes an air gap disposed beneath at least one passive device in the passive device layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: March 29, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Junjing Bao, Ye Lu, Haitao Cheng
  • Patent number: 11239621
    Abstract: An electrically conductive, single-piece flat part (100) for a plug with first and second contact pins (112, 114) are arranged in two parallel rows, and with a connector region for a cable. The part has a connecting element (102). Conductors (108, 110) which open into the first and second contact pins (112, 114) extend from the first and from the second side of the connecting element, the conductors (108, 110) which lie on the opposite sides of the connecting element (102) being connected to the connecting element (102) in a manner which is offset with respect to one another in such a way that the imaginary straight extension of a conductor (108, 110) runs on the one side of the connecting element (102) next to one or between two conductors (108, 110) on the opposite side of the connecting element (102).
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 1, 2022
    Assignee: NEXANS
    Inventors: Richard Riedel, Alexander Steinert, Stefan Kleber, Karl Schweigl
  • Patent number: 11056555
    Abstract: A semiconductor device having 3D inductor includes a first transverse inductor, a longitudinal inductor and a second transverse inductor. The first transverse inductor is formed on a first substrate, the second transverse inductor and the longitudinal inductor are formed on a second substrate. The second substrate is bonded to the first substrate to connect the first transverse inductor and the longitudinal inductor such that the first transverse inductor, the longitudinal inductor and the second transverse inductor compose a 3D inductor.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 6, 2021
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Cheng-Hung Shih, Nian-Cih Yang, Yi-Cheng Chen, Shang-Jan Yang
  • Patent number: 11031288
    Abstract: Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Sujit Sharan, Ravindranath Mahajan, Stefan Rusu, Donald S. Gardner
  • Patent number: 11011466
    Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 18, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind S. Bhagavat, Rahul Agarwal, Chia-Hao Cheng
  • Patent number: 10886771
    Abstract: An electronic device and methods for inductively charging an electronic device using another external electronic device. The electronic device may include an enclosure, a battery positioned within the enclosure, and an inductive coil coupled to the battery. The inductive coil may have two or more operational modes, including a power receiving operational mode for wirelessly receiving power and a power transmitting operational mode for wirelessly transmitting power. The electronic device may also have a controller coupled to the inductive coil for selecting one of the operational modes.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: January 5, 2021
    Assignee: Apple Inc.
    Inventors: Darshan R. Kasar, Christopher S. Graham, Eric S. Jol
  • Patent number: 10886769
    Abstract: An electronic device and methods for inductively charging an electronic device using another external electronic device. The electronic device may include an enclosure, a battery positioned within the enclosure, and an inductive coil coupled to the battery. The inductive coil may have two or more operational modes, including a power receiving operational mode for wirelessly receiving power and a power transmitting operational mode for wirelessly transmitting power. The electronic device may also have a controller coupled to the inductive coil for selecting one of the operational modes.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 5, 2021
    Assignee: Apple Inc.
    Inventors: Darshan R. Kasar, Christopher S. Graham, Eric S. Jol
  • Patent number: 10847300
    Abstract: There are provided an inductor and a method of manufacturing the same. The inductor includes: a body including a coil part; and cover parts disposed on upper and lower surfaces of the body. The coil part includes a plurality of through-vias penetrating through the upper and lower surfaces of the body and connection patterns disposed on the upper and lower surfaces of the body, disposed in the cover parts, and connecting the plurality of through-vias to each other.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jung Woo Choi, Jin Ho Hong, Il Jong Seo, Sa Yong Lee, Myung Sam Kang, Tae Hong Min
  • Patent number: 10847305
    Abstract: Disclosed herein is a coil component that includes an insulating substrate, a first coil part formed on the first surface of the insulating substrate, and a second coil part formed on the second surface of the insulating substrate. At least an innermost turn of the first coil part is radially separated by spiral-shaped slits into three or more conductor parts. At least an innermost turn of the second coil part is radially separated by spiral-shaped slits into three or more conductor parts. Inner peripheral ends of respective innermost to outermost conductor parts of the three or more conductor parts of the first coil part are connected to inner peripheral ends of the respective outermost to innermost conductor parts of the three or more conductor parts of the second coil part.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK CORPORATION
    Inventors: Syun Ashizawa, Masato Otsuka, Hanako Yoshino, Toshio Tomonari, Kohei Wada
  • Patent number: 10748697
    Abstract: A resonant power converter for operation in the radio frequency range, preferably in the VHF, comprises at least one PCB-embedded transformer. The transformer is configured for radio frequency operation and comprises a printed circuit board defining a horizontal plane, the printed circuit board comprising at least two horizontal conductive layers separated by an isolating layer, a first embedded solenoid forming a primary winding of the transformer and a second embedded solenoid being arranged parallel to the first solenoid and forming a secondary winding of the transformer, wherein the first and second embedded solenoids are formed in the conductive layers of the printed circuit board, wherein each full turn of an embedded solenoid has a horizontal top portion formed in an upper conductive layer, a horizontal bottom portion formed in a lower conductive layer, and two vertical side portions formed by vias extending between the upper and the lower conducting layers.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 18, 2020
    Assignee: Danmarks Tekniske Universitet
    Inventors: Mickey P. Madsen, Jakob Døllner Mønster
  • Patent number: 10734150
    Abstract: An inductor device (1) includes a magnetic body (2) and a conductor buried in the magnetic body (2), and the conductor includes first conductors (3) as metal pins. The magnetic body (2) is formed into a flat plate shape with a first main surface and a second main surface each having a predetermined shape, which oppose each other, and side surfaces connecting the first main surface and the second main surface. The conductor includes the first conductors (3) one end portions of which are exposed to the second main surface of the magnetic body (2) and a second conductor (4) which is connected to the other end portions of the first conductors (3).
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Norio Sakai, Mitsuyoshi Nishide, Shinichiro Banba, Tatsuyuki Yamada, Tetsuya Kanagawa, Atsuko Omori
  • Patent number: 10692645
    Abstract: A coupled inductor structure includes a first three-dimensional inductor structure and a second three-dimensional folded inductor structure. At least a portion of the first three-dimensional folded inductor structure is located within a volume bounded by the second three-dimensional folded inductor structure. By nesting the first three-dimensional folded inductor structure within the second three-dimensional folded inductor structure, a variety of coupling factors can be achieved while minimizing the size of the coupled inductor structure.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 23, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Marcus Granger-Jones, Baker Scott
  • Patent number: 10692964
    Abstract: An integrated circuit (IC) includes a circuit substrate having a front side surface and an opposite back side surface. Active circuitry is located on the front side surface. An inductive structure is located within a deep trench formed in the circuit substrate below the backside surface. The inductive structure is coupled to the active circuitry.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 23, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Roberto Giampiero Massolini, Daniel Carothers
  • Patent number: 10672704
    Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
  • Patent number: 10593450
    Abstract: Embodiments are directed to a method of forming a laminated magnetic inductor and resulting structures having multiple magnetic layer thicknesses. A first magnetic stack having one or more magnetic layers alternating with one or more insulating layers is formed in a first inner region of the laminated magnetic inductor. A second magnetic stack is formed opposite a major surface of the first magnetic stack in an outer region of the laminated magnetic inductor. A third magnetic stack is formed opposite a major surface of the second magnetic stack in a second inner region of the laminated magnetic inductor. The magnetic layers are formed such that a thickness of a magnetic layer in each of the first and third magnetic stacks is less than a thickness of a magnetic layer in the second magnetic stack.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 10573711
    Abstract: In one general aspect, an apparatus can include a first terminal, a second terminal, and a resistive element extending between the first terminal and the second terminal. The resistive element can include a first via in contact with a first segment of a first metal layer and a first segment of a second metal layer, and can include a second via in contact with the first segment of the second metal layer and a second segment of the first metal layer. The apparatus can also include a third via in contact with the second segment of the first metal layer and a third segment of the second metal layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: February 25, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Tyler Daigle, Andrew Jordan, Hrvoje Jasa, Gregory Maher
  • Patent number: 10506717
    Abstract: An inductor component 1a includes a resin layer 3 and an inductor electrode 6. The inductor electrode 6 includes metal pins 7a to 7d that extend in the resin layer 3 with end faces 70a to 70d of the metal pins 7a to 7d exposed from an upper surface 3a of the resin layer 3, and upper wiring plates 8a and 8b that are disposed on the upper surface 3a of the resin layer 3 and that connect the end faces 70a and 70c of the short metal pins 7a and 7c and the end faces 70b and 70d of the long metal pins 7b and 7d to each other. In this case, the inductor electrode 6 is formed of the metal pins 7a to 7d and the wiring plates 8a to 8c that each have a specific electrical resistance lower than that of a conductive paste and plating.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: December 10, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Shinichiro Banba, Mitsuyoshi Nishide, Norio Sakai
  • Patent number: 10505386
    Abstract: An electronic device and methods for inductively charging an electronic device using another external electronic device. The electronic device may include an enclosure, a battery positioned within the enclosure, and an inductive coil coupled to the battery. The inductive coil may have two or more operational modes, including a power receiving operational mode for wirelessly receiving power and a power transmitting operational mode for wirelessly transmitting power. The electronic device may also have a controller coupled to the inductive coil for selecting one of the operational modes.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 10, 2019
    Assignee: Apple Inc.
    Inventors: Darshan R. Kasar, Christopher S. Graham, Eric S. Jol
  • Patent number: 10404089
    Abstract: An electronic device and methods for inductively charging an electronic device using another external electronic device. The electronic device may include an enclosure, a battery positioned within the enclosure, and an inductive coil coupled to the battery. The inductive coil may have two or more operational modes, including a power receiving operational mode for wirelessly receiving power and a power transmitting operational mode for wirelessly transmitting power. The electronic device may also have a controller coupled to the inductive coil for selecting one of the operational modes.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: September 3, 2019
    Assignee: APPLE INC.
    Inventors: Darshan R. Kasar, Christopher S. Graham, Eric S. Jol
  • Patent number: 10354954
    Abstract: The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a metal projection protruding outward from an upper surface of the metal body. A dielectric layer is disposed over the substrate and surrounds the metal body and the metal projection. A barrier layer separates the metal body and the metal projection from the dielectric layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lu, Chung-Ju Lee, Hsiang-Huan Lee, Tien-I Bao
  • Patent number: 10256286
    Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Andreas Duevel, Telesphor Kamgaing, Valluri R. Rao, Uwe Zillmann
  • Patent number: 10256027
    Abstract: An embodiment of coil assembly includes a laterally disposed ferrite ring having a central opening. A laterally disposed annular conductive member is positioned above the ferrite ring and has a plurality of spaced-apart circumferential segments. A plurality of bond wires are connected at opposite ends thereof to outer and inner portions of the plurality of spaced-apart circumferential segments. A layer of mold compound covers the ferrite ring and the bond wires.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: April 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haiying Li, Benjamin Michael Sutton, Ming Li
  • Patent number: 10204731
    Abstract: Disclosed are a transmitting coil structure and wireless power transmitting terminal using the transmitting coil structure. The transmitting coil has a first winding and a second winding connected in parallel, so that the transmitting coil has a smaller inductance than the conventional transmitting coil in the condition of the same spatial magnetic field. When the receiving terminal is near the transmitting coil, the inductance of the transmitting coil is smaller, and the influence of the receiving terminal to the inductance of the transmitting coil is reduced significantly, and the effect to the impedance matching of the primary side transmitting coil and the resonant capacitor will not be too large, so as to improve the power transmission efficiency of the system.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: February 12, 2019
    Assignee: Ningbo WeiE Electronic Technology Co., Ltd.
    Inventor: Hengyi Su
  • Patent number: 10177213
    Abstract: A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 10003218
    Abstract: This disclosure pertains to wireless power transfer systems, and in particular (but not exclusively), to techniques to improve the coupling efficiency between a power transmitting unit and a power receiving unit within a computing device. The present disclosure includes a system which comprises a computing unit which includes a power receiving unit and a conductive surface. The conductive surface has an opening that is adjacent to the power receiving unit and a slot extending from the opening towards the perimeter of the conductive surface. The computing unit further includes a system base coupled to the power receiving unit wherein the power receiving unit is to provide power to the system base. The system also includes a power transmitting unit adjacent to the computing unit.
    Type: Grant
    Filed: December 20, 2014
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Songnan Yang, Janardhan Narayan, Jonathan Rosenfeld, Kerry Stevens, Patrick Chewning
  • Patent number: 9972564
    Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 15, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Lin Tsai, Yi-Feng Chang, Cheng-Jen Liu, Yi-Min Fu, Hung-Chi Chen
  • Patent number: 9929084
    Abstract: Electronic device comprising an interconnection structure comprising an alternating stack of arrays of conducting lines and dielectric layers in which: all the lines of a same array extend in a same plane and form an equipotential; a first pattern of a first array is such that the lines of the first array intersect at several intersections; a third pattern of a third array is similar, superimposed and aligned with the first pattern; a second pattern of a second array arranged between the first and third arrays is such that the lines of the second array intersect at several intersections offset with respect to those of the first and third patterns; a first conducting via extends from a line of the first and/or third array and is not in contact with the second array.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: March 27, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jose-Luis Gonzalez Jimenez
  • Patent number: 9917129
    Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: March 13, 2018
    Assignee: SONY CORPORATION
    Inventors: Takashi Yokoyama, Taku Umebayashi
  • Patent number: 9773878
    Abstract: A semiconductor device includes a first main electrode terminal and second main electrode terminal disposed on the principal surface of a semiconductor substrate so as to be spaced from one another, an insulating film formed on the principal surface of the semiconductor substrate, and a thin film resistance layer. One end side of the thin film resistance layer is connected to the first main electrode terminal and the other end side of the thin film resistance layer is connected to the second main electrode terminal, the thin film resistance layer being spirally formed on the insulating film in such a way as to surround the first main electrode terminal. The thin film resistance layer extends while oscillating in a thickness direction of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 9767957
    Abstract: A method making a three-dimensional inductor, the method including: forming a plurality of vias in a substrate or a molding compound, wherein the vias are arranged with spacings among them; forming a metal layer having interconnects, wherein the interconnects of the metal layer connect the plurality of vias on one end of the vias; forming a plurality of wires to connect the plurality of vias on the other end of the vias to form the 3D inductor; and tuning one or more of the plurality of wires to adjust a physical configuration and inductance value of the 3D inductor.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Monsen Liu, Chung-Hao Tsai, En-Hsiang Yeh, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 9721884
    Abstract: An inductor device includes a first insulating layer having a first via hole, a first metal layer formed on an upper surface of the first insulating layer and having a droop portion at an upper end-side of the first via hole, a second metal layer formed on a lower surface of the first insulating layer and having a first connection part exposed to a bottom surface of the first via hole, and a first metal-plated layer formed in the first via hole and configured to connect the first connection part and the droop portion of the first metal layer.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 1, 2017
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yasuyoshi Horikawa, Tsukasa Nakanishi, Tatsuaki Denda
  • Patent number: 9716056
    Abstract: A method for providing an inductively loaded integrated circuit includes providing a wafer with an integrated circuit formed thereon, the integrated circuit comprising at least one substrate via, including one or more substrate vias that are to be inductively loaded, and fabricating an inductive element on the backside of the wafer that electrically connects to the substrate vias that are to be inductively loaded. A corresponding apparatus includes a wafer with an integrated circuit formed on a top side of the wafer and an inductive element formed on a back side of the wafer, and at least one substrate via that extends through the wafer and electrically connects the inductive element to the integrated circuit. In certain embodiments, the inductive element comprises a plurality of conductive layers. In some embodiments, the inductive element comprises multiple turns on each conductive layer.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9690314
    Abstract: Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: June 27, 2017
    Assignee: Transphorm Inc.
    Inventors: James Honea, Yifeng Wu
  • Patent number: 9589831
    Abstract: A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: March 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yu Cheng, Keng-Yu Chen, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao
  • Patent number: 9516712
    Abstract: In some embodiments, a light device for generating light includes light emitting diodes (LEDs), and power supply circuitry including at least one switching regulator including switching elements to provide power to the LEDs. The light device includes a device support structure including a device connector and an LED support to support the LEDs, wherein the device connector is one end of the device support structure, and the power supply circuitry is supported by the device support structure. Other embodiments are described.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Shekhar Y. Borkar, Stephen G. Eichenlaub
  • Patent number: 9438112
    Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) on a group III-V die, and a driver IC for driving the output stage IC, the driver IC fabricated on a group IV die. The power converter also includes a composite power switch split between the group III-V die and the group IV die, wherein a depletion mode group III-V transistor of the composite power switch is monolithically integrated in the group III-V die, and a group IV control switch of the composite power switch is monolithically integrated in the group IV die. As a result, the depletion mode group III-V transistor may be operated as an enhancement mode transistor.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Alberto Guerra, Ahmed Masood
  • Patent number: 9438169
    Abstract: A frequency shifter configured to shift the frequency of a signal, the frequency shifter comprising: a resonant structure configured to mechanically resonate at a first frequency; and a plurality of capacitors, each capacitor having a variable plate separation distance, wherein the resonant structure is configured to cause the plate separation distance of each capacitor to oscillate so as to cause the frequency of the signal to shift by the first frequency.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: September 6, 2016
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventors: James Collier, Tim Newton
  • Patent number: 9383418
    Abstract: A method of fabricating fluxgate devices to measure the magnetic field in two orthogonal, in plane directions, by using a composite-anisotropic magnetic core structure.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: July 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anuraag Mohan, Dok Won Lee, William French, Erika L. Mazotti
  • Patent number: 9363902
    Abstract: This disclosure provides implementations of inductors, transformers, and related processes. In one aspect, a device includes a substrate having first and second surfaces. A first inducting arrangement includes a first set of vias, a second set of vias, a first set of traces arranged over the first surface connecting the first and second vias, and a second set of traces arranged over the second surface connecting the first and second vias. A second inducting arrangement is inductively-coupled and interleaved with the first inducting arrangement and includes a third set of vias, a fourth set of vias, a third set of traces arranged over the first surface connecting the third and fourth vias, and a fourth set of traces arranged over the second surface connecting the third and fourth vias. One or more sets of dielectric layers insulate portions of the traces from one another.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 7, 2016
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Chi Shun Lo, Jonghae Kim, Chengjie Zuo, Changhan Hobie Yun
  • Patent number: 9275786
    Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 1, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: David Francis Berdy, Chengjie Zuo, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Robert Paul Mikulka, Jonghae Kim
  • Patent number: 9269643
    Abstract: A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit layer. The chip includes an active surface, a back surface opposite to the active surface. The inducting coil is disposed around a periphery region of the chip. The molding compound covers the chip and the periphery region and exposes the active surface. The inducting coil is disposed at the molding compound. The redistribution circuit layer covers the active surface, part of the molding compound and part of the inducting coil, and electrically connects the chip.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: February 23, 2016
    Assignee: ChipMOS Technologies Inc.
    Inventor: Tsung-Jen Liao
  • Patent number: 9035457
    Abstract: A substrate with integrated passive devices and method of manufacturing the same are presented. The substrate may include through silicon vias, at least one redistribution layer having a 1st passive device pattern and stacked vias, and an under bump metal layer having a 2nd passive device pattern.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Fu Lin, Ming-Tse Lin, Yung-Chang Lin
  • Patent number: 8987054
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Darrell Truhitte
  • Patent number: 8981433
    Abstract: A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: March 17, 2015
    Assignee: NXP, B.V.
    Inventors: Lukas Frederik Tiemeijer, Vittorio Cuoco, Rob Mathijs Heeres, Jan Anne van Steenwijk, Marnix Bernard Willemsen, Josephus Henricus Bartholomeus van der Zanden
  • Patent number: 8941213
    Abstract: A semiconductor device includes: a spiral-shaped inductor formed to include a metal wire; and a horseshoe-shaped inductor formed to include the metal wire. The horseshoe-shaped inductor is arranged such that an opening of the horseshoe-shaped inductor is disposed opposite to the spiral-shaped inductor. Accordingly, unnecessary wave (spurious) output from a transmitting unit can be reduced as small as possible.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takao Kihara
  • Patent number: 8907460
    Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor. An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takasuke Hashimoto, Shinichi Uchida, Yasutaka Nakashiba, Takatsugu Nemoto
  • Patent number: 8900964
    Abstract: Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Jeffrey P. Gambino, Zhong-Xiang He, Alvin J. Joseph, Anthony K. Stamper, Timothy D. Sullivan
  • Patent number: 8866258
    Abstract: According to an exemplary embodiment, an interposer structure for electrically coupling a semiconductor die to a support substrate in a semiconductor package includes at least one through-wafer via extending through a semiconductor substrate, where the at least one through-wafer via provides an electrical connection between the semiconductor die and the support substrate. The interposer structure further includes a passive component including a trench conductor, where the trench conductor extends through the semiconductor substrate. The passive component further includes a dielectric liner situated between the trench conductor and the semiconductor substrate. The passive component can further include at least one conductive pad for electrically coupling the trench conductor to the semiconductor die. The passive component can be, for example, an inductor or an antenna.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: October 21, 2014
    Assignee: Broadcom Corporation
    Inventors: Wei Xia, Xiangdong Chen, Akira Ito
  • Patent number: 8860180
    Abstract: An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 14, 2014
    Assignee: Xilinx, Inc.
    Inventors: Jing Jing, Shuxian Wu, Parag Upadhyaya
  • Patent number: 8836078
    Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate having a horizontal surface. The semiconductor device includes an interconnect structure formed over the horizontal surface of the substrate. The interconnect structure includes an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The interconnect structure includes a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiu-Ying Cho