Ohmic Electrode (epo) Patents (Class 257/E21.046)
  • Patent number: 8969198
    Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: March 3, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Grigory Simin, Maxim S Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 8963167
    Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 24, 2015
    Assignee: Neokismet, LLC
    Inventors: Jawahar M. Gidwani, Anthony C. Zuppero
  • Patent number: 8878245
    Abstract: A transistor device having non-alloyed ohmic contacts formed by a process that improves the contact morphology and reduces metal spiking into the semiconductor layers. During fabrication, a regrowth mask is deposited on the semiconductor device. A portion of the regrowth mask and the epitaxial semiconductor layers is removed, defining areas for selective regrowth of a highly-doped semiconductor material. The remaining portion of the regrowth mask forms a regrowth mask residual layer. After regrowth, ohmic contacts are formed on the regrowth structures without the use of a high-temperature annealing process. The regrowth mask residual layer does not need to be removed, but rather remains on the device throughout fabrication and can function as a passivation layer and/or a spacer layer.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: November 4, 2014
    Assignee: Cree, Inc.
    Inventors: Primit Parikh, Sten Heikman
  • Patent number: 8759167
    Abstract: An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki
  • Patent number: 8741751
    Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8637339
    Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 28, 2014
    Assignee: Neokismet L.L.C.
    Inventors: Anthony C. Zuppero, Jawahar M. Gidwani
  • Patent number: 8597962
    Abstract: An improved method of fabricating a vertical semiconductor LED is disclosed. Ions are implanted into the LED to create non-conductive regions, which facilitates current spreading in the device. In some embodiments, the non-conductive regions are located in the p-type layer. In other embodiments, the non-conductive layer may be in the multi-quantum well or n-type layer.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: December 3, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: San Yu, Chi-Chun Chen
  • Patent number: 8535997
    Abstract: Provided is a direct contact technology by which a barrier metal layer between a Cu alloy wiring composed of pure Cu or a Cu alloy and a semiconductor layer can be eliminated, and the Cu alloy wiring can be directly and surely connected to the semiconductor layer within a wide process margin. The wiring structure is provided with the semiconductor layer and the Cu alloy film composed of pure Cu or the Cu alloy on a substrate in this order from the substrate side. A laminated structure is included between the semiconductor layer and the Cu alloy film. The laminated structure is composed of an (N, C, F) layer, which contains at least one element selected from among a group composed of nitrogen, carbon and fluorine, and a Cu—Si diffusion layer, which contains Cu and Si, in this order from the substrate side. Furthermore, at least the one element selected from among the group composed of nitrogen, carbon and fluorine is bonded to Si contained in the semiconductor layer.
    Type: Grant
    Filed: July 3, 2009
    Date of Patent: September 17, 2013
    Assignee: Kobe Steel, Ltd.
    Inventors: Nobuyuki Kawakami, Shinya Fukuma, Aya Miki, Mototaka Ochi, Shinya Morita, Yoshihiro Yokota, Hiroshi Goto
  • Publication number: 20120205739
    Abstract: The semiconductor device of this invention has unit cells, each of which includes: a substrate; a drift layer on the substrate; a body region in the drift layer; a first doped region of a first conductivity type in the body region; a second doped region of the first conductivity type arranged adjacent to the body region and in a surface region of the drift layer; a third doped region of the first conductivity type arranged between two adjacent unit cells' second doped region of the first conductivity type and in the surface region of the drift layer to contact with the second doped region of the first conductivity type; a gate insulating film arranged to contact with the surface of the drift layer at least between the first and second doped regions of the first conductivity type; a gate electrode on the gate insulating film; and first and second ohmic electrodes.
    Type: Application
    Filed: October 19, 2010
    Publication date: August 16, 2012
    Applicant: PANASONIC CORPORATION
    Inventor: Kenya Yamashita
  • Patent number: 8164087
    Abstract: A composition, comprising a medium of organic molecules, a plurality of nanoparticles dispersed in the medium, and a coating chemically bonded to a surface of the nanoparticles, wherein the composition is a semiconducting solid.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: April 24, 2012
    Assignee: Alcatel Lucent
    Inventors: Oleksandr Sydorenko, Subramanian Vaidyanathan
  • Patent number: 8003453
    Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: August 23, 2011
    Assignee: International Business Machines Corporation
    Inventors: Phaedon Avouris, Roy A. Carruthers, Jia Chen, Christopher G. M. M. Detavernier, Christian Lavoie, Hon-Sum Philip Wong
  • Patent number: 7985999
    Abstract: A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: July 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Oh, Jeong-Nam Han, Chang-Ki Hong, Woo-Gwan Shim, Im-Soo Park
  • Patent number: 7968368
    Abstract: A method of manufacturing a field effect transistor, which has high alignment accuracy between a gate electrode and source and drain electrodes and can provide a transparent device at a low cost. Since a patterned light blocking film is formed on the rear side of a substrate and used as a photomask for forming a gate electrode pattern and a source and drain electrode pattern on the front side of the substrate, the number of photomasks is reduced, and self-alignment between the gate electrode and the source and drain electrodes is carried out, thereby improving the alignment accuracy of these electrodes. Thereby, a method of manufacturing a high-accuracy low-cost field effect transistor can be provided.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: June 28, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hironori Wakana, Hiroyuki Uchiyama, Tetsufumi Kawamura, Shinichi Saito
  • Patent number: 7952089
    Abstract: An object of the invention is to provide a composite material with which a light emitting element can be manufactured to have superior heat resistance, and another is to have durability high enough to be driven stably for a long time. Another object is to provide a composite material with which a light emitting element can be manufactured to achieve both objects. Still another object is to provide a composite material with which a light emitting element can be manufactured to achieve the above objects and to have little increase in power consumption. One feature of a composite material of the invention which can achieve the above objects is to comprise an organic-inorganic hybrid material in which an organic group is covalently bonded to silicon in a skeleton composed of siloxane bonds, and a material which is capable of accepting or donating electrons from or to the organic group.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: May 31, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Ryoji Nomura, Takako Takasu
  • Patent number: 7888162
    Abstract: This application discloses a method of manufacturing a photoelectronic device comprising steps of providing a semiconductor stack layer, forming at least one metal adhesive on the semiconductor stack layer by a printing technology, forming an electrode by heating the metal adhesive to remove the solvent in the metal adhesive, wherein an ohmic contact is formed between the electrode and the semiconductor stack layer.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: February 15, 2011
    Assignee: Epistar Corporation
    Inventors: Yu-Ling Chin, Li-Pin Jou, Yu-Chih Yang, Yu-Cheng Yang, Wei-Shou Chen, Cheng-Ta Kuo
  • Patent number: 7867802
    Abstract: LED devices incorporating diamond materials and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: January 11, 2011
    Inventor: Chien-Min Sung
  • Patent number: 7858507
    Abstract: A method of fabricating a photoactive array having an integrated backplane is provided. The layers of the device may be stamped or deposited on a planar or a curved substrate, such as a semispherical or ellipsoidal substrate. Each metal layer may be stamped using an elastomeric stamp and a vacuum mold. By depositing the patterned and full-surface layers in a single process, a photosensitive array with an integrated transistor backplane may be fabricated, resulting in improved sensitivity and performance.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: December 28, 2010
    Assignee: The Regents of the University of Michigan
    Inventor: Stephen R. Forrest
  • Patent number: 7829448
    Abstract: Disclosed herein are a structure of a metal oxide semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) suitable for use in a semiconductor device, such as a single-pole-double-throw (SPDT) switch of a monolithic microwave integrated circuit (MMIC); and a method of producing the same. The MOS-PHEMT structure is characterized in having a gate dielectric layer formed by atomic deposition from a gate dielectric selected from the group consisting of Al2O3, HfO2, La2O3, and ZrO2, and thereby rendering the semiconductor structure comprising the same, such as a high frequency switch device, to have less DC power loss, less insertion loss and better isolation.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: November 9, 2010
    Assignee: National Chiao Tung University
    Inventors: Edward Yi. Chang, Yun-Chi Wu, Yueh-Chin Lin
  • Patent number: 7781802
    Abstract: As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N? silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both of the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer are hetero-joined to the semiconductor base, and are ohmically connected to the anode electrode.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: August 24, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Shigeharu Yamagami, Masakatsu Hoshi, Yoshio Shimoida, Tetsuya Hayashi, Hideaki Tanaka
  • Patent number: 7767572
    Abstract: Methods of forming a barrier layer for an interconnection structure are provided. In one embodiment, a method for forming an interconnect structure includes providing a substrate having a first conductive layer disposed thereon, incorporating oxygen into an upper portion of the first conductive layer, depositing a first barrier layer on the first conductive layer, and diffusing the oxygen incorporated into the upper portion of the first conductive layer into a lower portion of the first barrier layer. In another embodiment, a method for forming an interconnection structure includes providing a substrate having a first conductive layer disposed thereon, treating an upper surface of the first conductive layer with an oxygen containing gas, depositing a first barrier layer on the treated conductive layer, and depositing a second conductive layer on the first barrier layer while driving a portion of oxygen atoms from the treated conductive layer into the first barrier layer.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: August 3, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Chong Jiang, Anthony Chih-Tung Chan
  • Patent number: 7659628
    Abstract: Contact structures and methods for forming such contact structures are disclosed. An example contact structure includes a layer of semiconductor material having an interface and an electrical contact at the interface of the layer of semiconductor material, where the electrical contact includes a granular metal. An example method for forming a contact structure includes providing a substrate and producing a granular metal on at least part of the substrate, where the granular metal includes a cluster of metal islands extending essentially in a two-dimensional plane. The method further includes depositing a layer of a semiconductor material on top of the substrate and the cluster of metal islands.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: February 9, 2010
    Assignee: IMEC
    Inventors: Vladimir Arkhipov, Paul Heremans
  • Patent number: 7586131
    Abstract: A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines includes a core, at least the surface of which is electrically conductive, an insulating layer that covers the core, and a semiconductor layer that covers the insulating layer. Each of the function lines contacts with, and crosses, the conductor lines. Each of the transistors includes a first ohmic contact region, which is defined by a region where one of the conductor lines crosses one of the function lines and which makes an ohmic contact with the semiconductor layer, a second ohmic contact region, which also makes an ohmic contact with the semiconductor layer, and a channel region, which is defined in the semiconductor layer between the first and second ohmic contact regions.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: September 8, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hirohiko Nishiki, Kazuki Kobayashi
  • Patent number: 7534712
    Abstract: The semiconductor device comprises a silicon substrate 10 having a device region 11, a transistor including a gate electrode 20 formed in the device region 11 with the gate insulation film 14 formed therebetween, and a dummy metal layer 52 formed over the gate electrode 20 with an inter-layer insulation film 32 formed therebetween, formed of a metal material having the property of occluding hydrogen and having a peripheral part positioned outer of a region where the region for the gate electrode 20 formed in and the device region 11 overlap each other.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: May 19, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Masatoshi Takami
  • Patent number: 7465650
    Abstract: This invention includes methods of forming plugs containing polysilicon, and methods of forming FLASH memory circuitry. In one implementation, a method of forming a plug containing polysilicon includes providing a substrate having an opening formed therein. Polysilicon is formed within the opening to less than fill the opening. The polysilicon within the opening is exposed to an atmosphere containing H2 and a temperature of at least 500° C. After such exposing, metal is formed within the opening over the polysilicon. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: December 16, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Garo J. Derderian
  • Patent number: 7368822
    Abstract: The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resistance of the ohmic contact is adjusted by the thicknesses of the three layers.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: May 6, 2008
    Assignee: National Chiao Tung University
    Inventors: Cheng-Shih Lee, Edward Yi Chang, Ke-Shian Chen