Device Having At Least One Potential-jump Barrier Or Surface Barrier, E.g., Pn Junction, Depletion Layer, Carrier Concentration Layer (epo) Patents (Class 257/E21.04)

  • Patent number: 10840417
    Abstract: A method for manufacturing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment, a method includes applying a conversion layer including a luminescence conversion material to a support plate including a glass, arranging at least two optoelectronic semiconductor chips over the conversion layer on a side remote from the support plate and forming an envelope material free from a luminescence conversion material between the optoelectronic semiconductor chips, thereby forming a workpiece.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: November 17, 2020
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Matthias Knoerr
  • Patent number: 9041090
    Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Akira Goda, Durai Vishak Nirmal Ramaswamy
  • Patent number: 9006849
    Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: April 14, 2015
    Inventor: Yimin Guo
  • Patent number: 8987696
    Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sonehara, Nobuaki Yasutake
  • Patent number: 8927366
    Abstract: A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hae Lee, Ki-hyun Hwang, Jin-gyun Kim
  • Patent number: 8884404
    Abstract: The description relates to a method of patterning a semiconductor device to create a through substrate via. The method produces a through substrate via having no photoresist material therein. An intermediate layer deposited over an interlayer dielectric prevents etching solutions from etching interlayer dielectric sidewalls to prevent peeling. The description relates to a semiconductor apparatus including a semiconductor substrate having a through substrate via therein. The semiconductor apparatus further includes an interlayer dielectric over the semiconductor substrate and an intermediate layer over semiconductor substrate and over sidewalls of the interlayer dielectric.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Fang Li, Chun-Li Lin, Chun-Sheng Wu, Ding-I Liu
  • Patent number: 8865554
    Abstract: A method for fabricating a nonvolatile memory device includes forming a structure having a plurality of first interlayer insulating layers and a plurality of sacrificial layers alternately stacked over a substrate, forming main channel holes configured to penetrate the structure, sequentially forming a preliminary charge trap layer, a tunnel insulating layer, and a channel layer on the inner walls of the main channel holes, forming a trench configured to penetrate the plurality of sacrificial layers on both sides of each of the main channel holes, and forming insulating oxide layers by oxidizing the preliminary charge trap layer on inner sides of the first interlayer insulating layers. In accordance with this technology, since the charge trap layer is separated for each memory cell, the spread of charges may be prevented and the reliability of a nonvolatile memory device may be improved.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyun-Sik Doo
  • Patent number: 8803266
    Abstract: A storage node of a magnetic memory device includes: a lower magnetic layer, a tunnel barrier layer formed on the lower magnetic layer, and a free magnetic layer formed on the tunnel barrier. The free magnetic layer has a magnetization direction that is switchable in response to a spin current. The free magnetic layer has a cap structure surrounding at least one material layer on which the free magnetic layer is formed.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-seok Kim, U-In Chung, Jai-kwang Shin, Kee-won Kim, Sung-chul Lee, Ung-hwan Pi
  • Patent number: 8765544
    Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: July 1, 2014
    Assignee: Broadcom Corporation
    Inventor: Akira Ito
  • Publication number: 20140124893
    Abstract: An electrical device includes a semiconductor material. The semiconductor material includes a first region of the semiconductor material having a first conductivity type, a second region of the semiconductor material having a second conductivity type complementary to the first conductivity type and an intermediate region of the semiconductor material between the first region and the second region. The first and second regions lie next to each other the intermediate region so as to form a diode structure. A shape of the intermediate region tapers from the first region to the second region.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Josef Dietl, Raimund Peichl, Gabriele Bettineschi
  • Patent number: 8716852
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Patent number: 8709202
    Abstract: Components of a plasma processing apparatus includes a backing member with gas passages attached to an upper electrode with gas passages. To compensate for the differences in coefficient of thermal expansion between the metallic backing member and upper electrode, the gas passages are positioned and sized such that they are misaligned at ambient temperature and substantially concentric at an elevated processing temperature. Non-uniform shear stresses can be generated in the elastomeric bonding material, due to the thermal expansion. Shear stresses can either be accommodated by applying an elastomeric bonding material of varying thickness or using a backing member comprising of multiple pieces.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: April 29, 2014
    Assignee: Lam Research Corporation
    Inventors: Anthony De La Llera, Allan K. Ronne, Jaehyun Kim, Jason Augustino, Rajinder Dhindsa, Yen-Kun Wang, Saurabh J. Ullal, Anthony J. Norell, Keith Comendant, William M. Denty, Jr.
  • Patent number: 8704210
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 22, 2014
    Assignee: University of Connecticut
    Inventor: Pu-Xian Gao
  • Publication number: 20140103436
    Abstract: A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8674332
    Abstract: One device disclosed herein includes first and second sidewall spacers positioned above a semiconducting substrate, wherein the first and second sidewall spacers are comprised of at least a conductive material, a conductive word line electrode positioned between the first and second sidewall spacers and first and second regions of variable resistance material positioned between the conductive word line electrode and the conductive material of the first and second sidewall spacers, respectively. This example also includes a base region of a bipolar transistor in the substrate below the word line electrode, an emitter region formed below the base region and first and second collector regions formed in the substrate within the base region, wherein the first collector region is positioned at least partially under the first region of variable resistance material and the second collector region is positioned at least partially under the second region of variable resistance material.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte Ltd
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Quek
  • Publication number: 20140057422
    Abstract: A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Inventors: XIAN LIU, MANDANA TADAYONI, CHIEN-SHENG SU, NHAN DO
  • Publication number: 20140054667
    Abstract: A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Inventor: Yuri Tkachev
  • Patent number: 8637385
    Abstract: According to one exemplary embodiment, a method for fabricating a high voltage durability transistor comprises forming a gate over a gate oxide layer formed over a substrate, aligning an exposure mask with the gate, and selectively blocking exposure of the gate during gate implant doping, by exposure shields formed in the exposure mask, thereby producing the high voltage durability transistor. In one embodiment, an exemplary high voltage durability transistor comprises a gate formed over a gate oxide layer, the gate oxide layer being situated over a semiconductor substrate, where the gate has a reduced doping implant due to selective implant blocking provided by exposure shields formed in an exposure mask. The selective implant blocking results in an enhanced dielectric barrier so as to produce a high voltage durability transistor. The enhanced dielectric barrier has a depletion region with an increased thickness.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: January 28, 2014
    Assignee: Broadcom Corporation
    Inventors: Akira Ito, Henry KuoShun Chen
  • Publication number: 20140021590
    Abstract: A manufacturing method provides a semiconductor device with a substrate layer and an epitaxial layer adjoining the substrate layer. The epitaxial layer includes first columns and second columns of different conductivity types. The first and second columns extend along a main crystal direction along which channeling of implanted ions occurs from a first surface into the epitaxial layer. A vertical dopant profile of one of the first and second columns includes first portions separated by second portions. In the first portions a dopant concentration varies by at most 30%. In the second portions the dopant concentration is lower than in the first portions. The ratio of a total length of the first portions to the total length of the first and second portions is at least 50%. The uniform dopant profiles improve device characteristics.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Laven, Dieter Fuchs, Werner Schustereder, Roman Knoefler
  • Patent number: 8633561
    Abstract: A superjunction device that includes a termination region having a transition region adjacent the active region thereof, the transition region including a plurality of spaced columns.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: January 21, 2014
    Assignee: Siliconix Technology C. V.
    Inventors: Ali Husain, Srinkant Sridevan
  • Patent number: 8629519
    Abstract: A tunneling magnetoresistance sensor including a substrate, an insulating layer, a tunneling magnetoresistance component and an electrode array is provided. The insulating layer is disposed on the substrate. The tunneling magnetoresistance component is embedded in the insulating layer. The electrode array is formed in a single metal layer and disposed in the insulating layer either below or above the TMR component. The electrode array includes a number of separate electrodes. The electrodes are electrically connected to the tunneling magnetoresistance component to form a current-in-plane tunneling conduction mode. The tunneling magnetoresistance sensor in this configuration can be manufactured with a reduced cost and maintain the high performance at the same time.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 14, 2014
    Assignee: Voltafield Technology Corporation
    Inventors: Chien-Min Lee, Kuang-Ching Chen, Fu-Tai Liou
  • Patent number: 8624397
    Abstract: This wiring layer structure includes: an underlying substrate of a semiconductor substrate or a glass substrate; an oxygen-containing Cu layer or an oxygen-containing Cu alloy layer which is formed on the underlying substrate; an oxide layer containing at least one of Al, Zr, and Ti which is formed on the oxygen-containing Cu layer or the oxygen-containing Cu alloy layer; and a Cu alloy layer containing at least one of Al, Zr, and Ti which is formed on the oxide layer.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: January 7, 2014
    Assignees: Mitsubishi Materials Corporation, Ulvac, Inc.
    Inventors: Kazunari Maki, Kenichi Yaguchi, Yosuke Nakasato
  • Patent number: 8617960
    Abstract: A capacitive microphone transducer integrated into an integrated circuit includes a fixed plate and a membrane formed in or above an interconnect region of the integrated circuit. A process of forming an integrated circuit containing a capacitive microphone transducer includes etching access trenches through the fixed plate to a region defined for the back cavity, filling the access trenches with a sacrificial material, and removing a portion of the sacrificial material from a back side of the integrated circuit.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 31, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Brian E. Goodlin, Wei-Yan Shih, Lance W. Barron
  • Patent number: 8614104
    Abstract: A ferroelectric capacitor is formed over a semiconductor substrate (10), and thereafter, interlayer insulating films (48, 50, 52) covering the ferroelectric capacitor are formed. Next, a contact hole (54) reaching a top electrode (40) is formed in the interlayer insulating films (48, 50, 52). Next, a wiring (58) electrically connected to the top electrode (40) through the contact hole (54) is formed on the interlayer insulating films (48, 50, 52). At the time of forming the top electrode (40), conductive oxide films (40a, 40b) are formed, and then a cap film (40c) composed of a noble metal exhibiting less catalytic action than Pt and having a thickness of 150 nm or less is formed on the conductive oxide films (40a, 40b).
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 24, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Publication number: 20130330899
    Abstract: A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 12, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huiming Bu, Ming Cai, Kevin K. Chan, Dechao Guo, Ravikumar Ramachandran, Liyang Song, Chun-Chen Yeh
  • Publication number: 20130307080
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yue-Der Chih, Jam-Wem Lee, Cheng-Hsiung Kuo, Tsung-Che Tsai, Ming-Hsiang Song, Hung-Cheng Sung, Roger Wang
  • Patent number: 8574968
    Abstract: This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: November 5, 2013
    Assignees: Soitec, Arizona Board of Regents for and on Behalf of Arizona State University
    Inventors: Chantal Arena, Christiaan J. Werkhoven, Ronald Thomas Bertram, Jr., Ed Lindow, Subhash Mahajan, Ranjan Datta, Rahul Ajay Trivedi, Ilsu Han
  • Patent number: 8575605
    Abstract: An organic light-emitting display device includes: a substrate having a transistor region and a thin-film transistor having a gate electrode, a source/drain electrode and an active layer sequentially formed on the transistor region, wherein a portion of the source/drain electrode is between the active layer and substrate.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: November 5, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Seong-Kweon Heo
  • Publication number: 20130256789
    Abstract: A fabrication method of a power semiconductor device is provided. Firstly, a plurality of trenched gate structures is formed in the base. Then, a body mask is used for forming a pattern layer on the base. The pattern layer has at least a first open and a second open for forming at least a body region and a heavily doped region in the base respectively. Then, a shielding structure is formed on the base to fill the second open and line at least a sidewall of the first open. Next, a plurality of source doped regions is formed in the body region by using the pattern layer and the shielding structure as the mask. Then, an interlayer dielectric layer is formed on the base and a plurality of source contact windows is formed therein to expose the source doped regions.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: SUNG-NIEN TANG, HSIU-WEN HSU
  • Patent number: 8530290
    Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-hoon Yang, Jin-Wook Seo, Sei-Hwan Jung, Ki-Yong Lee
  • Publication number: 20130221427
    Abstract: A semiconductor device includes a first contact in low Ohmic contact with a source region of the device and a first portion of a body region of the device formed in an active area of the device, and a second contact in low Ohmic contact with a second portion of the body region formed in a peripheral area of the device. The minimum width of the second contact at a first surface of the device is larger than the minimum width of the first contact at the first surface so that maximum current density during commutating the semiconductor device is reduced and thus the risk of device damage during hard commutating is also reduced.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Ralf Siemieniec, Oliver Blank, Anton Mauder, Franz Hirler
  • Publication number: 20130217175
    Abstract: In one embodiment, a method includes depositing a CZT(S, Se) precursor layer onto a substrate, introducing a source-material layer comprising Sn(S, Se) into proximity with the precursor layer, and annealing the precursor layer in proximity with the source-material layer in a constrained volume.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: AQT Solar, Inc.
    Inventors: Vardaan Chawla, Mariana Rodica Munteanu
  • Publication number: 20130218241
    Abstract: Thermoelectric devices and methods for making and using the devices and their intermediates are provided. Membrane-supported thermoelectric modules are fabricated by dispensing thermoelectric powder into select locations of a membrane to form electrically-isolated columns of thermoelectric material. The powder is then sintered or fused to form thermoelectric elements, which are then electrically connected and combined with thermal interface films to form the modules. The modules are the building blocks of electrical current generating, thermoelectric cooling and heat scavenging thermoelectric devices.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: NANOHMICS, INC.
    Inventors: Steve M. Savoy, Byron G. Zollars, Qizhen Xue, Jeremy J. John, Paul A. Parks
  • Patent number: 8497537
    Abstract: A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Wensheng Wang, Ko Nakamura
  • Publication number: 20130187240
    Abstract: A semiconductor device including a semiconductor layer of a first conductivity type in a cell region, a first base layer of a second conductivity type on the semiconductor layer in the cell region; a second base layer of the second conductivity type on the semiconductor layer in an intermediate region; a conductive region of a first conductivity type in the first base layer; a gate electrode on a channel region placed between the conductive region and the semiconductor layer; a first electrode connected to the first and second base layers; a second electrode connected to the semiconductor layer; and a gate pad on the semiconductor layer via an insulating film in a pad region and connected to the gate electrode, an impurity concentration gradation in the gate pad side of the second base layer has a gentler VLD structure than an impurity concentration gradation in the first base layer.
    Type: Application
    Filed: September 14, 2012
    Publication date: July 25, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kazutoyo TAKANO
  • Publication number: 20130161717
    Abstract: A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL) current and a method for fabricating the three-dimensional non-volatile memory device. The non-volatile memory device includes a channel structure formed over a substrate including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked, and a first selection gate and a second selection gate that are disposed on a first side and a second side of the channel structure, wherein the first selection gate and the second selection gate contact sidewalls of the multiple channel layers, respectively, wherein a work function of a material forming the first selection gate is different from a work function of a material forming the second selection gate.
    Type: Application
    Filed: September 7, 2012
    Publication date: June 27, 2013
    Inventors: Sang-Moo CHOI, Byung-Soo Park, Sang-Hyun Oh, Han-Soo Joo
  • Publication number: 20130137248
    Abstract: A method for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.
    Type: Application
    Filed: September 26, 2012
    Publication date: May 30, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Patent number: 8450822
    Abstract: Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and an optically transparent layer contacting the polymer layer and covering the cavity.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Robert K. Leidy, Richard J. Rassel
  • Publication number: 20130105894
    Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 2, 2013
    Applicant: International Business Machines Corporation
    Inventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
  • Publication number: 20130107620
    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 2, 2013
    Inventor: Toru Tanzawa
  • Publication number: 20130102136
    Abstract: A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 25, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Yen HSIEH, Chang MING-CHING, Chun-Hung LEE, Yih-Ann LIN, De-Fang CHEN, Chao-Cheng CHEN
  • Publication number: 20130089974
    Abstract: A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.
    Type: Application
    Filed: September 11, 2012
    Publication date: April 11, 2013
    Inventors: Sung-hae Lee, Ki-hyun Hwang, Jin-gyun Kim
  • Publication number: 20130061901
    Abstract: Provided is a high temperature thermoelectric converting module including a plurality of p type thermoelectric elements; a plurality of n type thermoelectric elements; a plurality of electrodes; and a lead line. The plurality of p type thermoelectric elements, the plurality of n type thermoelectric elements, and the plurality of electrodes are electrically serially connected to each other, a pair of connecting lines that connects the lead line to one of the plurality of electrodes to output to the outside is further included, at least one electrode which is disposed at the high temperature side and the plurality of p type and n type thermoelectric elements are bonded with an intermediate layer therebetween. The plurality of p type and n type thermoelectric elements contain silicon as a component and the intermediate layer is formed as a layer containing aluminum and silicon and components other than silicon of the thermoelectric elements.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 14, 2013
    Inventors: Tomotake TOHEI, Shinichi Fujiwara, Takahiro Jinushi, Zenzo Ishijima
  • Patent number: 8389321
    Abstract: A solar cell includes a substrate, a protective layer located over a first surface of the substrate, a first electrode located over a second surface of the substrate, at least one p-type semiconductor absorber layer located over the first electrode, an n-type semiconductor layer located over the p-type semiconductor absorber layer, and a second electrode over the n-type semiconductor layer. The p-type semiconductor absorber layer includes a copper indium selenide (CIS) based alloy material, and the second electrode is transparent and electrically conductive. The protective layer has an emissivity greater than 0.25 at a wavelength of 2 ?m, has a reactivity with a selenium-containing gas lower than that of the substrate, and may differ from the first electrode in at least one of composition, thickness, density, emissivity, conductivity or stress state. The emissivity profile of the protective layer may be uniform or non-uniform.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: March 5, 2013
    Assignee: MiaSole
    Inventors: Chris Schmidt, John Corson
  • Patent number: 8389976
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Arijit Raychowdhury, Ali Keshavarzi, Juanita Kurtin, Vivek De
  • Patent number: 8378435
    Abstract: A method of packaging a pressure sensing die includes providing a lead frame with lead fingers and attaching the pressure sensing die to the lead fingers such that bond pads of the die are electrically coupled to the lead fingers and a void is formed between the die and the lead fingers. A gel material is dispensed via an underside of the lead frame into the void such that the gel material substantially fills the void. The gel material is then cured and the die and the lead frame are encapsulated with a mold compound. The finished package does not include a metal lid.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: February 19, 2013
    Inventors: Wai Yew Lo, Lan Chu Tan
  • Patent number: 8362479
    Abstract: A semiconductor device which comprises a channel layer formed from a semiconductor channel component material in the form of crystalline micro particles, micro rods, crystalline nano particles, or nano rods, and doped with a semiconductor dopant.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: January 29, 2013
    Assignees: Panasonic Corporation, Cambridge Enterprise Ltd.
    Inventors: Kiyotaka Mori, Henning Sirringhaus
  • Patent number: 8350252
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 8, 2013
    Assignee: University of Connecticut
    Inventor: Pu-Xian Gao
  • Patent number: 8349716
    Abstract: Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: January 8, 2013
    Assignees: International Business Machines Corporation, GlobalFoundries Inc.
    Inventors: Ming Cai, Christian Lavoie, Ahmet S. Ozcan, Bin Yang, Zhen Zhang
  • Publication number: 20120329221
    Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.
    Type: Application
    Filed: September 5, 2012
    Publication date: December 27, 2012
    Applicant: Broadcom Corporation
    Inventor: Akira Ito