Circuit For Characterizing Or Monitoring Manufacturing Process, E.g., Whole Test Die, Wafer Filled With Test Structures, Onboard Devices Incorporated On Each Die, Process/product Control Monitors Or Pcm, Devices In Scribe-line/kerf, Drop-in Devices (epo) Patents (Class 257/E21.524)
  • Patent number: 10224286
    Abstract: Embodiments of the disclosure provide an interconnect structure including: a first die having a first surface and an opposing second surface, and a groove within first surface of the first die; an adhesive dielectric layer mounted to the opposing second surface of the first die; a second die having a first surface mounted to the adhesive dielectric layer, and an opposing second surface, wherein the adhesive dielectric layer is positioned directly between the first and second dies; and a through-semiconductor via (TSV) including a first TSV metal extending from the first surface of the first die to the adhesive dielectric layer, and a second TSV metal substantially aligned with the first TSV metal and extending from the adhesive dielectric layer to the opposing second surface of the second die, wherein the TSV includes a metal-to-metal bonding interface between the first and second TSV metals within the adhesive dielectric layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke G. England, Kenneth J. Giewont
  • Patent number: 9000434
    Abstract: A semiconductor device including a semiconductor substrate having a surface including an active semiconductor device including one of a laser and a photodiode; and a visual indicator disposed on the semiconductor body and at least adjacent to a portion of said active semiconductor device, the indicator having a state that shows if damage to the active semiconductor device may have occurred.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: April 7, 2015
    Assignee: Emcore Corporation
    Inventors: Richard Carson, Elaine Taylor, Douglas Collins
  • Patent number: 8963150
    Abstract: A semiconductor device includes a circuit board including a ground portion, and a semiconductor package disposed on the circuit board. The semiconductor package includes an external connecting pad and an exposed pad. The exposed pad and the ground portion are electrically connected at a first surface of the exposed pad. A semiconductor chip is disposed on a second surface of the exposed pad and electrically connected to the external connecting pad. The first surface of the exposed pad is located external to the semiconductor package, and the second surface of the exposed pad is located within the semiconductor package. A test pad is disposed on the semiconductor chip and is electrically connected to the exposed pad.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: February 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Hyun Yeo, Yong-Bum Kim, Byung-Kil Jeon, Bong-Ju Jun
  • Patent number: 8946706
    Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Chang Kil Kim
  • Patent number: 8932884
    Abstract: Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Noah D. Zamdmer
  • Patent number: 8872178
    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: October 28, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Alan Hales
  • Patent number: 8873920
    Abstract: A light-guiding cover structure includes a top cover unit and a light-guiding unit. The top cover unit has a plurality of receiving spaces formed therein. The light-guiding unit includes a plurality of light-guiding groups, wherein each light-guiding group includes a plurality of optical fiber cables received in the corresponding receiving space, and each optical fiber cable has two opposite ends exposed from the bottom surface of the top cover unit and respectively facing at least one light-emitting device and at least one light-sensing device that have been disposed under the top cover unit. Therefore, the optical fiber cables received in the corresponding receiving space, thus when the light-guiding cover structure is applied to the LED package chip classification system, the aspect of the LED package chip classification system can be enhanced.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: October 28, 2014
    Assignee: Youngtek Electronics Corporation
    Inventors: Bily Wang, Kuei-Pao Chen, Hsin-Cheng Chen, Cheng-Chin Chiu
  • Patent number: 8847221
    Abstract: A stacked semiconductor device includes: an internal circuit; a through electrode provided to penetrate through a semiconductor substrate; a test wiring to which a predetermined potential different from a substrate potential is supplied at a time of a test; a first switch arranged between the through electrode and the internal circuit; a second switch arranged between the through electrode and the test wiring; and a control circuit that exclusively turns on the first and the second switches. Thereby, it becomes possible to perform an insulation test in a state that the through electrode and the internal circuit are cut off. Thus, even when a slight short-circuit that does not lead to a current defect occurs, the short circuit can be detected.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: September 30, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Kayoko Shibata
  • Patent number: 8846448
    Abstract: The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an electrically-insulating adhesive which couples the packages. A pressure generator and a variable frequency microwave source are coupled to a process chamber which encapsulates a package-on-package semiconductor structure. The package-on-package semiconductor structure is simultaneously heated by the variable frequency microwave source at variable frequency, variable temperature, and variable duration and exposed to an elevated pressure by the pressure generator. This combination for microwave heating and elevated pressure limits the amount of warpage introduced while preventing void formation within an electrically-insulating adhesive which couples the substrates of the package-on-package semiconductor structure.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Kuei-Wei Huang, Tsai-Tsung Tsai, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8809077
    Abstract: In a method of manufacturing of a semiconductor device according to an embodiment, an inspection transistor is subjected to silicidation and subsequently a characteristic of the inspection transistor is measured after the inspection transistor and a product transistor on a substrate are subjected to an annealing process. Thereafter, based on the measured characteristic, a characteristic adjustment annealing process to make a characteristic of the product transistor close to a desired characteristic is performed, and then the product transistor is subjected to silicidation.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Amane Oishi
  • Patent number: 8692248
    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 8, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Alan Hales
  • Patent number: 8673657
    Abstract: In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate, and, at the same time, five isolation insulating films extending in one specific direction are formed within a monitor area at a fixed spacing. Then, a gate insulation film and a gate electrode are formed within the circuit area on the semiconductor substrate, and, at the same time, five gate insulation films and five gate electrodes extending in the same direction as the isolation insulating films are formed within the monitor area at the same spacing as that of the isolation insulating films.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 8674355
    Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chi Tseng, Heng-Hsin Liu, Shu-Cheng Kuo, Chien-Chang Lee, Chun-Hung Lin
  • Patent number: 8658437
    Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: February 25, 2014
    Assignee: Princo Middle East FZE
    Inventors: Yeong-yan Guu, Ying-jer Shih
  • Patent number: 8648339
    Abstract: A semiconductor device includes a plurality of first data input/output terminals, a plurality of second data input/output terminals, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a plurality of first data input/output pads connected with the first data input/output terminals, a first test circuit, and a first memory portion. The first test circuit generates a first test result in response to a data output from the first memory portion at a test operation. The second semiconductor chip includes a plurality of second data input/output pads connected with the second data input/output terminals, a second and a third test circuits, and a second memory portion.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: February 11, 2014
    Assignee: Elpida Memory, Inc.
    Inventors: Takahiro Koyama, Sadayuki Okuma
  • Patent number: 8629435
    Abstract: A first test structure includes a first isolation region, a first gate electrode over the first isolation region, a first and a second semiconductor fin, and a first contact plug over the first and the second semiconductor fins. A second test structure includes a second isolation region, a second gate electrode over the second isolation region, a third semiconductor fin and a dielectric fin, and a second contact plug over the third semiconductor fin. The first, the second, and the third semiconductor fins and the dielectric fin have substantially a same fin height. A method includes measuring a first capacitance between the first gate electrode and the first contact plug, measuring a second capacitance between the second gate electrode and the second contact plug, and calculating the same fin height from a capacitance difference between the second capacitance and the first capacitance.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Horn Tsai, Hsiao-Han Liu
  • Patent number: 8623673
    Abstract: A test structure and method for monitoring process uniformity. Embodiments of the invention include test structures having a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region in a first metallization layer, a defect-dispersing region in the second metallization layer above the defect-generating region; and a defect-detecting region in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density. The defect-detecting region may include a test pattern such as, a comb-serpentine structure. Embodiments may include more than one defect-generating region, more than one defect-dispersing region, or more than one defect-detecting region.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Tze-Man Ko, Yiheng Xu, Shaoning Yao
  • Patent number: 8623772
    Abstract: A method of forming patterns of a semiconductor device includes forming a hard mask layer and a first sacrificial layer over a first region and a second region of a semiconductor substrate, etching the first sacrificial layer to form a first sacrificial pattern having a first width in the first region and second sacrificial patterns having a second width in the second region, wherein the second width is narrower than the first width, forming a first spacer surrounding sidewalls of the first sacrificial pattern and a second spacer surrounding sidewalls of the second sacrificial patterns, removing the first and the second sacrificial patterns; and etching the first and second spacers.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: January 7, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jae Doo Eom
  • Patent number: 8610121
    Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 17, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, Tony P. Chiang, Alexander Gorer, David E. Lazovsky
  • Patent number: 8604475
    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Alan Hales
  • Patent number: 8592813
    Abstract: A semiconductor device includes: a through-electrode formed in a perpendicular direction so as to extend therethrough; a series circuit section formed from a plurality of test-ready switches successively connected in series and driven by a driving voltage transmitted to the through-electrode through a predetermined different layer through-electrode of a different semiconductor device stacked on an upper layer side or a lower layer side; and a pair of test terminals connected to end portions of the series circuit section and adapted to be used for measurement of conduction of the series circuit section.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: November 26, 2013
    Assignee: Sony Corporation
    Inventor: Takenori Sugawara
  • Patent number: 8586982
    Abstract: A semiconductor test device including a plurality of conductive layers, each of the layers comprising integrated circuit devices, a plurality of insulating layers between the conductive layers, a plurality of heat generating structures positioned between the insulating layers and the conductive layers, each of the heat generating structures being sized and positioned to only heat a predetermined limited area of the plurality of layers, a plurality of thermal monitors positioned within each of the plurality of layers, a control unit operatively connected to the heat generating structures and the thermal monitors, the control unit individually cycling the heat generating structures on and off for multiple heat cycles, such that different areas of the layers are treated to different heat cycles.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Luke D. LaCroix, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 8519388
    Abstract: The present invention relates to a method and system for testing integrity of a passivation layer (108) covering a semiconductor device. A structured layer of electrically conducting material (104) is deposited onto at least a portion of a top surface of a substrate (102) of the semiconductor device. The structured layer (104) comprises a plurality of bands (104.1, 104.2) connected to at least two contacts (106.1, 106.2) and disposed on the at least a portion of the top surface such that one of consecutive bands (104.1, 104.2) and consecutive portions of the bands (104.1, 104.2) are connected to different contacts (106.1, 106.2). A passivation layer (108) is deposited onto the at least a portion of the top surface of the substrate (102) and the structured layer (104) such that material of the passivation layer(108) is disposed between the bands of conducting material (104.1, 104.2) and on top of the structured layer (104).
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 27, 2013
    Assignee: NXP B.V.
    Inventors: Lucie A. Rousseville, Sebastien Jacqueline, Patrice Gamand, Dominique Yon
  • Patent number: 8507908
    Abstract: A probe comprises: contact parts to be electrically connected to input/output terminals of an IC device built in a semiconductor wafer under test; interconnect parts at the front ends of which the contact parts are provided; a plurality of beam parts on the top surface of which the interconnect parts are provided along the longitudinal direction; and a base part supporting the plurality of beam parts all together in a cantilever fashion, the beam parts are supported by the base part at a rear end region of the beam parts, and grooves are provided between the adjoining beam parts in the rear end region.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: August 13, 2013
    Assignee: Advantest Corporation
    Inventor: Koichi Wada
  • Patent number: 8501502
    Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: August 6, 2013
    Assignee: Princo Middle East FZE
    Inventors: Yeong-yan Guu, Ying-jer Shih
  • Patent number: 8466037
    Abstract: In a method for producing a very thin chip including an integrated circuit, a circuit structure is produced in a defined section of a semiconductor wafer. The defined wafer section is subsequently released from the semiconductor wafer. For this purpose, the wafer section is firstly freed such that it is held only via local web-like connections on the remaining semiconductor wafer, which web-like connections are arranged at a lateral periphery of the wafer section. The web-like connections are subsequently severed.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: June 18, 2013
    Assignee: Institut fuer Mikroelektronik Stuttgart
    Inventors: Joachim N. Burghartz, Wolfgang Appel, Martin Zimmermann
  • Publication number: 20130126866
    Abstract: A semiconductor device in one embodiment includes a wiring board having a wiring pattern; an N semiconductor elements(where N denotes a natural number equal to or greater than 2) mounted on a wiring board; and a current detection parts for detecting a current flowing through m semiconductor elements (where m denotes a natural number equal to or greater than 1 but less than M) of M semiconductor elements(where M denotes a natural number equal to or greater than 1 but equal to or less than N) mounted on the wiring board and selected from the N semiconductor elements. The M semiconductor elements are electrically connected in parallel through the wiring pattern, and the m semiconductor elements are electrically connected in parallel to the other semiconductor elements of the M semiconductor elements through the current detection part.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 23, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Patent number: 8420498
    Abstract: An alignment method of chips that are formed on a surface of a semiconductor wafer with alignment marks corresponding to the chips includes the steps of irradiating an alignment mark corresponding to a predetermined alignment chip in a predetermined area including the chips with a laser light; detecting reflected waves from the alignment mark of the predetermined alignment chip to obtain a position of the alignment mark of the predetermined alignment chip; irradiating an alignment mark of an alternative chip different from the predetermined alignment chip with the laser light in case of not being able to obtain the position of the alignment mark of the predetermined alignment chip; obtaining a position of the alignment mark of the alternative chip by detecting the reflected waves from the alignment mark of the alternative chip; and aligning the chips in the predetermined area based on positions of alignment marks including the position of the alignment mark of the alternative chip.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 16, 2013
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Yukihiro Tanemura
  • Patent number: 8362480
    Abstract: A Characterization Vehicle (CV) and a method for forming it which yields a gain in efficiency for IC yield ramp improvements by enabling faster learning cycles and diagnosis while reducing costs. A plurality of SF experiments are combined into a single full flow mask set with many inline testing points. Smaller pads are arranged in a way supporting testing of interleaved pad frames, parallel testing, and the usage of stacked test structures, or Devices Under Test (DUT's).
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: January 29, 2013
    Assignee: PDF Solutions, Inc.
    Inventors: Christopher Hess, John Kibarian, Amit Joag, Abdul Mobeen Mohammed, Ben Shieh, David Stashower
  • Patent number: 8362483
    Abstract: A thin film transistor (TFT) substrate includes a TFT that including a gate electrode, a source electrode, and a drain electrode formed on an insulating substrate divided into a display area and a non-display area to provide test driving signals provided from the outside to the display area, a test signal line connected to the drain electrode of the TFT, a pad unit signal line insulated from the test signal line by an insulating layer and connected to signal lines formed in the display area, and a jumping pad electrode electrically connecting the test signal line and the pad unit signal line to each other through a contact hole that penetrates the insulating layer, connected to a driving circuit for driving the display area, and providing driving signals provided from the driving circuit to the pad unit signal line and a flat panel display (FPD) including the same.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: January 29, 2013
    Assignee: LG Display Co., Ltd.
    Inventor: Bunggoo Kim
  • Patent number: 8350393
    Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 8, 2013
    Assignee: Wintec Industries, Inc.
    Inventor: Kong-Chen Chen
  • Patent number: 8334582
    Abstract: A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wei Chen, Shang-Yun Hou, Hao-Yi Tsai, Anbiarshy N. F. Wu, Yu-Wen Liu
  • Patent number: 8323991
    Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: December 4, 2012
    Assignee: Infineon Technologies AG
    Inventors: Armin Fischer, Alexander Von Glasow, Jochen Von Hagen
  • Patent number: 8309951
    Abstract: In one disclosed embodiment, the present test structure for determining gate-to-body current in a floating body FET includes a floating body FET situated over a semiconductor layer, where the floating body FET includes a first gate and first and second source/drain regions. The floating body test structure further includes a second gate and a first contact situated over the first source/drain region. A gate-to-channel current measured between the second gate and the first contact is utilized to determine the gate-to-body tunneling current. The gate-to-body tunneling current can be determined by subtracting the gate-to-channel current from twice a source/drain current of the floating body FET. The test structure may also include a second contact situated on a doped region in the semiconductor layer, where a diode current flow through the doped region determines a body voltage for the floating body FET.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: November 13, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sushant S. Suryagandh, Ciby Thomas Thuruthiyil
  • Patent number: 8299464
    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: October 30, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Alan Hales
  • Patent number: 8274165
    Abstract: A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: insulating layers formed in the plurality of groove portions; a rectangular unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode including an extended terminal portion extended from the unit region to the inside of the groove portion. The semiconductor substrate is manufactured by forming a plurality of groove portions along scribe lines; embedding an insulating material in the plurality of groove portions and planarizing a surface to form insulating layers; and forming a wiring electrode including an extended terminal portion extended from a rectangular unit region in contact with at least any one of the plurality of groove portions to the inside of the groove portion.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: September 25, 2012
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8274080
    Abstract: A semiconductor wafer includes semiconductor chip areas on a semiconductor substrate, the semiconductor chip areas having thereon semiconductor circuit patterns and inner guard ring patterns surrounding the semiconductor circuit patterns; and scribe lanes on the semiconductor substrate between the semiconductor chip areas, the scribe lanes having thereon outer guard ring patterns surrounding the inner guard ring patterns and a process monitoring pattern between the outer guard ring patterns, the outer guard ring patterns and the process monitoring pattern being merged with each other.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Hyun Han
  • Patent number: 8211720
    Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: July 3, 2012
    Assignee: Infineon Technologies AG
    Inventors: Armin Fischer, Alexander Von Glasow, Jochen Von Hagen
  • Patent number: 8211716
    Abstract: The present invention aims to increase the number of test elements of a TEG without increasing the area of each of slice areas. Test electrode pads are disposed in alignment in one row in each of areas separated from semiconductor chips provided over a semiconductor wafer. Test elements are formed corresponding to these test electrode pads and in areas lying directly therebelow. Electrode terminals of the test elements are electrically coupled to the test electrode pads adjacent to the corresponding electrode pads and the test electrode pads further adjacent thereto with being spaced one test electrode pad apart. Upon testing, probe pins are brought into contact with the odd-numbered test electrode pads to conduct testing. Next, the probe pins are brought into contact with the even-numbered test electrode pads while being shifted by one electrode pad pitch thereby to conduct testing.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Shinkawata
  • Patent number: 8193006
    Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: June 5, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Fa Chou, Ding-Ming Kwai
  • Publication number: 20120115256
    Abstract: A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.
    Type: Application
    Filed: January 20, 2012
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David E. LACKEY, Chandramouili VISWESWARIAH, Paul S. ZUCHOWSKI
  • Patent number: 8173534
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 8, 2012
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Rainer Holmer
  • Patent number: 8124428
    Abstract: A method for determining the presence of a sacrificial layer under a structure. The method includes providing at least one structure arranged above a substrate having a major surface lying in a plane, the at least one structure being clamped at at least one side. The method further includes exerting a force, such as a mechanical force, on the at least one structure. The force may have a predetermined amplitude and a component perpendicular to the substrate. Still further, the method includes determining the deflection of the at least one structure perpendicular to the plane of the substrate, and correlating the deflection of the at least one structure to the presence of a sacrificial layer between the substrate and the structure.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: February 28, 2012
    Assignee: Imec
    Inventor: Gregory Van Barel
  • Patent number: 8084769
    Abstract: A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: December 27, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Sheng-Hao Lin, Chien-Hsing Lee, Da-Ching Chiou, Sun-Chin Wei, Min-Yi Chang, Cheng-Tung Huang, Tung-Hsing Lee, Tzyy-Ming Cheng
  • Patent number: 8084770
    Abstract: In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: December 27, 2011
    Assignee: Spansion LLC
    Inventors: Steven Avanzino, Suzette K. Pangrle, Manuj Rathor, An Chen, Sameer Haddad, Nicholas Tripsas, Matthew Buynoski
  • Patent number: 8039837
    Abstract: A semiconductor test structure includes a PFET transistor, having a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact. The source region and drain region float, and the body contact is electrically connected to the body of the PFET transistor and to the ground. This grounds the body of the PFET transistor, and the body contact of the test structure is electrically connected to a capacitor that is electrically connected to ground.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Oliver D. Patterson, Ishtiaq Ahsan
  • Patent number: 8026523
    Abstract: A nitride semiconductor free-standing substrate includes a surface inclined in a range of 0.03° to 1.0° from a C-plane, and an off-orientation that an angle defined between a C-axis and a tangent at each point on a whole surface of the substrate becomes maximum is displaced in a range of 0.5° to 16° from a particular M-axis orientation of six-fold symmetry M-axis orientations. The substrate does not include a region of ?0.5°<?<+0.5° on the surface, where ? represents a displacement angle of the off-orientation on a surface of the substrate from the particular M-axis orientation.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: September 27, 2011
    Assignee: Hitachi Cable, Ltd.
    Inventor: Hajime Fujikura
  • Patent number: 7989803
    Abstract: In a semiconductor wafer that has semiconductor devices arranged in a plurality of device-formation-regions and a TEG placed in dividing regions that define the device-formation-regions, a TEG-placement portion is arranged in the dividing regions partially expanded in width, and the TEG is placed in the TEG-placement portion. Additionally, a protective sheet is stuck to the semiconductor wafer, then plasma etching is performed, and the TEG is removed in a state where it remains in the dividing region and stuck to the protective sheet together with the protective sheet by peeling off the protective sheet, thereby the device-formation-regions are divided into individual pieces, and the semiconductor chips are manufactured.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: August 2, 2011
    Assignee: Panasonic Corporation
    Inventors: Kiyoshi Arita, Teruaki Nishinaka
  • Patent number: 7948059
    Abstract: In a semiconductor device comprising a ceramic substrate, a surface mount component, and sealing resin and obtained by division into pieces, the ceramic substrate is composed of a multiple piece substrate provided with dividing grooves for the division into pieces on both front and rear surfaces in advance, a plurality of the surface mount components are mounted on the multiple piece substrate and sealed collectively by the sealing resin, and the substrate is divided along the dividing grooves. Further, when the shortest distance from an end on the front surface of the ceramic substrate to an end of the surface mount component is set to “a” ?m, a thickness of the ceramic substrate is set to “b” ?m, and sum of depths of the dividing grooves on the front and rear surfaces of the ceramic substrate is set to “c” ?m, a relationship of a?269×c/b+151 is established.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 24, 2011
    Assignee: Hitachi Metals, Ltd.
    Inventors: Yoshio Ozeki, Toshiaki Takai, Makoto Ohta, Takahiro Umeyama
  • Patent number: 7935965
    Abstract: A test vehicle and method for electrical characterization of misalignment, for example resulting from double patterning processes, that enables characterization of patterns on wafers which have finished processing. It includes a structure and method for measurement of a space-sensitive electrical parameter to characterize gaps between features of different sub-patterns on a semiconductor wafer portion, and may further comprise a test structure for measuring feature dimensions.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: May 3, 2011
    Assignee: PDF Solutions, Inc.
    Inventor: Tomasz Brozek