Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

Abstract: A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a trench, and a contact layer. The first gate structure is disposed on a front-side of the buried dielectric layer, and the second gate structure is disposed on a backside of the buried dielectric layer. The first source/drain region and a second source/drain region are disposed between the first gate structure and the second gate structure. The trench is formed in the buried dielectric layer, and the contact layer is disposed in the trench and electrically coupled to the second source/drain region, where the contact structure and the second gate structure are formed of the same material.

Abstract: A manufacturing method for multiple MEMS sound transducers includes manufacturing a reconstructed wafer, separating multiple chips from the wafer, and encapsulating the chips in a molding material. A piezoelectric element of the particular chips is exposed to become deflectable along a stroke axis. The reconstructed wafer is connected to multiple diaphragms associated with the particular chips, wherein the diaphragms are each connected to the associated piezoelectric element so that the diaphragms are each deflectable together with the at least one associated piezoelectric element along the stroke axis. MEMS sound transducers, each of which including at least one of the chips and one of the diaphragms, are isolated. A MEMS sound transducer, which has been manufactured using the aforementioned manufacturing method, is also disclosed.

Abstract: A method for processing a substrate in a plasma chamber is provided. The method includes providing a substrate on which an underlying layer to be etched and a mask are formed. The method further includes forming a protective film on the mask. The method further includes performing an anisotropic deposition to selectively form a deposition layer on a top portion of the mask.

Abstract: Methods and apparatuses for performing cycles of aspect ratio dependent deposition and aspect ratio independent etching on lithographically patterned substrates are described herein. Methods are suitable for reducing variation of feature depths and/or aspect ratios between features formed and partially formed by lithography, some partially formed features being partially formed due to stochastic effects. Methods and apparatuses are suitable for processing a substrate having a photoresist after extreme ultraviolet lithography. Some methods involve cycles of deposition by plasma enhanced chemical vapor deposition and directional etching by atomic layer etching.

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Abstract: In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.

Abstract: An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed.

Abstract: A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

Abstract: Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.

Abstract: Various embodiments include field effect transistors (FETs) and related integrated circuit (IC) layouts. One FET includes: a silicon substrate including a set of trenches; a first oxide abutting the silicon substrate; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer, wherein the silicon layer includes a plurality of salicide regions; a gate structure overlying the second oxide between adjacent salicide regions; and a first contact contacting the gate structure; a second contact contacting one of the salicide regions; a third oxide partially filling the set of trenches and extending above the silicon layer overlying the SiGe layer; and an air gap in each of the set of trenches, the air gap surrounded by the third oxide.

Abstract: A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.

Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device.

Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.

Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

Abstract: A semiconductor device includes an assembly of two integrated circuits. The assembly has a layer of photoresist filling the space between the two integrated circuits, and at least one electrically conducting pillar within the resist and electrically coupling the two integrated circuits.

Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.

Abstract: A semiconductor structure includes a photonic modulator and a field effect transistor on a same substrate. The photonic modulator includes a modulator semiconductor structure and a semiconductor contact structure employing a same semiconductor material as a gate electrode of a field effect transistor. The modulator semiconductor structure includes a lateral p-n junction, and the semiconductor contact structure includes another lateral p-n junction. To form this semiconductor structure, the modulator semiconductor structure in the shape of a waveguide and an active region of a field effect transistor region can be patterned in a semiconductor substrate. A gate dielectric layer is formed on the modulator semiconductor structure and the active region, and is subsequently removed from the modulator semiconductor structure.

Abstract: A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board (20) including a plurality of insulating resin layers, semiconductor element-mounting terminals (18) formed on the uppermost surface of the board, and external connection terminals (12) formed on the bottom surface thereof. Each external connection terminal (12) is formed as a bump projected downward from the bottom surface of the package, and each bump is filled with the insulating resin (14) while the surface thereof is covered by a metal (16). Wiring (24), (26) including a conductor via (26a) electrically connect the metal of the metal layer 16 and the semiconductor element-mounting terminals (18).

Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via opening. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and fills the via opening. The buffer layer further covers a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.

Abstract: A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern.

Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.

Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line contact hole obtained by etching the semiconductor substrate; a bit line contact plug having a smaller width than that of the bit line contact hole; and a bit line connected to the upper portion of the bit line contact plug, thereby preventing a short of the bit line contact plug and the storage node contact plug to improve characteristics of the semiconductor device.

Abstract: A semiconductor package includes: a wiring board; and a semiconductor device which is formed on the wiring board; wherein the semiconductor device includes: a semiconductor chip; and a penetration electrode, one end of which is fixed on one plane of the semiconductor chip, and the other end of which penetrates the semiconductor chip and is fixed on the other plane of the semiconductor chip, the penetration electrode penetrating the semiconductor chip in such a manner that the penetration electrode is not contacted to a wall plane of the semiconductor chip by a space portion formed in the semiconductor chip; and the wiring board and the semiconductor device are electrically connected via the penetration electrode.

Abstract: An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Abstract: A method of fabricating an integrated circuit device includes forming first and second preliminary mask structures on a hard mask layer in respective first and second regions of the substrate. Spacers are formed on opposing sidewalls of the first and second preliminary mask structures, and the first preliminary mask structure is selectively removed from between the spacers in the first region. The hard mask layer is etched using the spacers and the second preliminary mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region and a second mask pattern including the opposing sidewall spacers and the second preliminary mask structure therebetween in the second region.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.

Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.

Abstract: A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract: The invention is directed to a semiconductor device having a via hole and a method of manufacturing the same that achieve both the prevention of a barrier layer insufficiently covering the via hole and the control of via resistance at the same time. A semiconductor substrate having a pad electrode on its front surface is prepared. The semiconductor substrate is etched from its back surface to its front surface to form a via hole exposing the pad electrode. A first barrier layer is then formed in the via hole by a sputtering method or a PVD method and reverse-sputtering (etching). By this reverse-sputtering, the barrier layer on the bottom of the via hole is removed to expose the pad electrode. A second barrier layer is then formed on the pad electrode exposed in the via hole. The via resistance is controlled by adjusting only the thickness of the second barrier layer.

Abstract: An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.

Abstract: Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned at an angle to the first structure, and the plurality of pad structures are intersecting at least one of the linear structures in the first structure. An electronic device with at least one semiconductor device, methods for manufacturing a semiconductor device and a mask system are also covered.

Abstract: Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed.

Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate.

Abstract: In manufacturing a semiconductor device including a substrate having a (111)-plane orientation and an off-set angle in a range between 3 degrees and 4 degrees, a capacitor, a transistor and a diffusion resistor are formed in the substrate, each of which are separated by a junction separation layer. A first silicon nitride film is formed by low pressure CVD over a surface of the substrate except a bottom portion of a contact hole and a portion over the junction separation layer, and a silicon oxide film is formed by low pressure CVD over the first silicon nitride film. A second silicon nitride film as a protecting film is formed by plasma CVD so as to cover the semiconductor device finally. Therefore, the semiconductor device having high reliability can be obtained.

Abstract: According to one embodiment, a collector electrode including metal is used for a sink region for connecting an n+ type buried layer, so that the sink region can be narrowly formed. Further, an interval between a base region and the collector electrode can be reduced, thereby considerably decreasing the size of the transistor. Furthermore, collector resistance is reduced, so that the performance of the transistor can be improved.

Abstract: An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semiconductor substrate; creating a plurality of voids inside the insulating layer, with the plurality of voids spanning across a predefined area and being substantially confined within a range of depth below a top surface of the insulating layer; creating at least one via hole in the insulating layer, with the via hole passing through the predefined area; and filling the via hole, and the plurality of voids inside the insulating layer through at least the via hole, with a conductive material to form a local metallization. A semiconductor structure having the local metallization is also provided.

Abstract: A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We planarize the copper layer to form a copper interconnect in the interconnect opening. The copper interconnect is over polished to form a depression. We form metal silicide layer over the copper interconnect using a low temperature sputtering process. We can form a cap layer over the metal silicide layer.

Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.

Abstract: A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.

Abstract: An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Abstract: A semiconductor device (having an interlayer insulating film) which is sufficiently low in the dielectric constant and high in the mechanical strength is provided. A manufacturing method of a semiconductor device includes: a step of forming a dielectric thin film in which a plurality of pores are arranged around a skeleton mainly made of a Si—O bond, on a surface of a semiconductor substrate on which a desired element region is formed; a step of applying patterning on a surface of the dielectric thin film through a mask; and a step of bringing a gas containing at least one kind of tetramethylcyclotetrasiloxane (TMCTS), hexamethyldisilazane (HMDS) and trimethylchlorosilane (TMCS) molecules into contact with the patterned surface of the dielectric thin film.

Abstract: A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board.

Abstract: A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the first conductive layer and first dielectric layer. A second dielectric layer is formed over the second conductive layer. A polymer material is deposited over the second dielectric layer and second conductive layer. A third conductive layer is formed over the polymer material and second conductive layer. The third conductive layer is electrically connected to the second conductive layer. A first solder bump is formed over the third conductive layer. A conductive via is formed through a back surface of the substrate. The conductive via is electrically connected to the first conductive layer. The polymer material has a low coefficient of thermal expansion.