Manufacture Or Treatment Of Devices Consisting Of Plurality Of Solid-state Components Formed In Or On Common Substrate Or Of Parts Thereof; Manufacture Of Integrated Circuit Devices Or Of Parts Thereof (epo) Patents (Class 257/E21.532)
  • Patent number: 10580667
    Abstract: A heat treatment apparatus is provided with two cool chambers, that is, a first cool chamber and a second cool chamber. A semiconductor wafer before treatment is alternately carried into the first cool chamber or the second cool chamber and then transported to a heat treatment part by a transport robot after a nitrogen purge is performed. The semiconductor wafer after being heat-treated in the heat treatment part is alternately transported to the first cool chamber or the second cool chamber to be cooled. A sufficient cooling time is secured for the independent semiconductor wafer, and a reduction in throughput as the whole heat treatment apparatus can be suppressed.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: March 3, 2020
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Takayuki Aoyama, Yasuaki Kondo, Shinji Miyawaki, Shinichi Kato, Kazuhiko Fuse, Hideaki Tanimura, Akitsugu Ueda, Hikaru Kawarazaki, Masashi Furukawa
  • Patent number: 10566321
    Abstract: In a method for wafer-to-wafer bonding, an integrated circuit (IC) wafer and a phase-change material (PCM) switch wafer are provided. The IC includes at least one active device, and has an IC substrate side and a metallization side. The PCM switch wafer has a heat spreading side and a radio frequency (RF) terminal side. A heat spreader is formed in the PCM switch wafer. In one approach, the heat spreading side of the PCM switch wafer is bonded to the metallization side of the IC wafer, then a heating element is formed between the heat spreader and a PCM in the PCM switch wafer. In another approach, a heating element is formed between the heat spreader and a PCM in the PCM switch wafer, then the RF terminal side of the PCM switch wafer is bonded to the metallization side of the IC wafer.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: February 18, 2020
    Assignee: Newport Fab, LLC
    Inventors: Gregory P. Slovin, David J. Howard
  • Patent number: 9530964
    Abstract: In a method of manufacturing a display, the method includes: forming a display device on a substrate attached to a first surface of a carrier; arranging, on a second surface of the carrier, a shield that corresponds to at least a portion of edge areas of the substrate and comprises non-transparent shielding areas; and irradiating light onto the second surface of the carrier to separate a portion of the substrate from the carrier.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 27, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Donghoon Lee, Joonhyung Kim
  • Patent number: 9023688
    Abstract: A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors, where the interconnection layers include copper or aluminum; forming a shielding heat conducting layer overlaying the interconnection layers; forming an isolation layer overlaying the shielding heat conducting layer; forming a second semiconductor layer overlying the isolation layer, and processing the second semiconductor layer at a temperature greater than about 400° C., where the interconnection layers are kept at a temperature below about 400° C.
    Type: Grant
    Filed: June 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Albert Karl Henning
  • Patent number: 9000418
    Abstract: A field-effect transistor includes a semiconductor layer (14) having a portion functioning as a channel region. The semiconductor layer (14) includes, as its constituent components, a plurality of electrically conductive microparticles (52), organic semiconductor molecules (53) bonded to the microparticles (52) so as to link the microparticles to one another (52), and cyclic molecules. Each of the organic semiconductor molecules (53) includes a ?-electron conjugated chain as its main chain, and the ?-electron conjugated chain is insulated by cyclic molecules.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: April 7, 2015
    Assignee: Panasonic Corporation
    Inventors: Takayuki Takeuchi, Kenji Harada, Nobuaki Kambe, Jun Terao
  • Patent number: 8987865
    Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 24, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Mankoo Lee
  • Patent number: 8957430
    Abstract: A light emitting device is fabricated by providing a mounting substrate and an array of light emitting diode dies adjacent the mounting substrate to define gaps. A gel that is diluted in a solvent is applied on the substrate and on the array of light emitting dies. At least some of the solvent is evaporated so that the gel remains in the gaps, but does not completely cover the light emitting diode dies. For example, the gel substantially recedes from the substrate beyond the array of light emitting diode dies and also substantially recedes from an outer face of the light emitting diode dies. Related light emitting device structures are also described.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Cree, Inc.
    Inventor: Matthew Donofrio
  • Patent number: 8859391
    Abstract: A method for manufacturing a semiconductor device including: forming a wiring layer on a surface side of a first semiconductor wafer; forming a buried film so as to fill in a level difference on the wiring layer, the level difference being formed at a boundary between a peripheral region of the first semiconductor wafer and an inside region being on an inside of the peripheral region, and the level difference being formed as a result of a surface over the wiring layer in the peripheral region being formed lower than a surface over the wiring layer in the inside region, and making the surfaces over the wiring layer in the peripheral region and the inside region substantially flush with each other; and opposing and laminating the surfaces over the wiring layer formed in the first semiconductor wafer to a desired surface of a second semiconductor wafer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: October 14, 2014
    Assignee: Sony Corporation
    Inventor: Hiroyasu Matsugai
  • Patent number: 8828779
    Abstract: A backside illumination (BSI) CMOS image sensing process includes the following steps. A substrate having an active side is provided. A curving process is performed to curve the active side. A reflective layer is formed on the active side, so that at least a curved mirror is formed on the active side.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Xin Zhao
  • Patent number: 8822281
    Abstract: A semiconductor device has a semiconductor die mounted over a carrier. An encapsulant is deposited over the semiconductor die and carrier. An insulating layer is formed over the semiconductor die and encapsulant. A plurality of first vias is formed through the insulating layer and semiconductor die while mounted to the carrier. A plurality of second vias is formed through the insulating layer and encapsulant in the same direction as the first vias while the semiconductor die is mounted to the carrier. An electrically conductive material is deposited in the first vias to form conductive TSV and in the second vias to form conductive TMV. A first interconnect structure is formed over the insulating layer and electrically connected to the TSV and TMV. The carrier is removed. A second interconnect structure is formed over the semiconductor die and encapsulant and electrically connected to the TSV and TMV.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: September 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Seung Uk Yoon
  • Patent number: 8779517
    Abstract: A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng
  • Patent number: 8754538
    Abstract: A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: June 17, 2014
    Assignee: Infineon Technologies AG
    Inventor: Jörg Ortner
  • Patent number: 8748237
    Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: June 10, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Mankoo Lee
  • Patent number: 8742547
    Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazutaka Yoshizawa, Taiji Ema
  • Patent number: 8728846
    Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Barry Jon Male, Philip L. Hower
  • Patent number: 8647945
    Abstract: A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Geng Wang, Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi
  • Patent number: 8637862
    Abstract: A device housing is provided. The device housing includes a substrate, a silicon dioxide film formed on the substrate, and a zinc oxide film formed on the silicon dioxide film. The silicon dioxide film has micrometer sized structures. The zinc oxide film has nanometer sized structures. A method for making the device housing is also described there.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: January 28, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd, Hon Hai Precision Industry Co., Ltd.
    Inventors: Hsin-Pei Chang, Wen-Rong Chen, Huann-Wu Chiang, Cheng-Shi Chen, Ying-Ying Wang
  • Patent number: 8598682
    Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: December 3, 2013
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Mankoo Lee
  • Patent number: 8592107
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Patent number: 8563366
    Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: October 22, 2013
    Assignees: Intermolecular Inc., Kabushiki Kaisha Toshiba, Sandisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Mankoo Lee
  • Patent number: 8551830
    Abstract: There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first semiconductor layer transistor formed in the first semiconductor layer, a wiring layer which is deposited on the first semiconductor layer and in which metal wires are formed, a second semiconductor layer deposited on the wiring layer and a second semiconductor layer transistor formed in the second semiconductor layer. It is noted that insulation of a gate insulating film of the first semiconductor layer transistor is almost equal with that of a gate insulating film of the second semiconductor layer transistor and the gate insulating film of the second semiconductor layer transistor is formed by means of radical oxidation or radical nitridation.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: October 8, 2013
    Assignees: Advantest Corporation, National University Corporation Tohoku University
    Inventors: Tadahiro Ohmi, Koji Kotani, Kazuyuki Maruo, Takahiro Yamaguchi
  • Patent number: 8492884
    Abstract: A stacked leadframe assembly is disclosed. The stacked leadframe assembly includes a first die having a surface that defines a mounting plane, a first leadframe stacked over and attached to the first die, a second die stacked over and attached to the first leadframe; and a second leadframe stacked over and attached to the second die. The leadframes have die paddles with extended side panels that have attachment surfaces in the mounting plane.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: July 23, 2013
    Assignee: Linear Technology Corporation
    Inventor: David Alan Pruitt
  • Publication number: 20130134544
    Abstract: An energy harvesting integrated circuit (IC) includes electrical connectors, each having a portion of a first material and a portion of a second material. The first and the second materials have a thermoelectric potential. The IC includes a trace of the first material coupled to the first material of each electrical connector, and a trace of the second material coupled to the second material of each electrical connector and the first trace. A portion of the second trace extends away from a portion of the first trace. The IC has charge storing elements coupled to the first and/or second traces. The first material and the second material are heated to create an electron flow from a thermal gradient between a first zone of the heated first and second materials and a second zone of the first and the second materials away from the first zone.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventor: Henry L. Sanchez
  • Patent number: 8426235
    Abstract: A capacitive electromechanical transducer includes a substrate, a cavity formed by a vibrating membrane held above the substrate with a certain distance between the vibrating membrane and the substrate by supporting portions arranged on the substrate, a first electrode whose surface is exposed to the cavity, and a second electrode whose surface facing the cavity is covered with an insulating film, wherein the first electrode is provided on a surface of the substrate or a lower surface of the vibrating membrane and the second electrode is provided on a surface of the vibrating membrane or a surface of the substrate so as to face the first electrode. In this transducer, fine particles composed of an oxide film of a substance constituting the first electrode are arranged on the surface of the first electrode, and the diameter of the fine particles is 2 to 200 nm.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: April 23, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Chienliu Chang
  • Patent number: 8420453
    Abstract: A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: April 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Yoon, Byeong-Soo Kim, Kyoung-Sub Shin, Hong Cho, Hyung-Yong Kim
  • Patent number: 8373236
    Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 12, 2013
    Assignees: NXP, B.V., Interuniversitair Microelektronica Centrum VZW
    Inventors: Erwin Hijzen, Joost Melai, Wibo Van Noort, Johannes Donkers, Philippe Meunier-Beillard, Andreas M. Piontek, Li Jen Choi, Stefaan Van Huylenbroeck
  • Patent number: 8362574
    Abstract: FinFETs and methods of making FinFETs are provided. The FinFET contains two or more fins over a semiconductor substrate; two or more epitaxial layers over side surfaces of the fins; and metal-semiconductor compounds over an upper surfaces of the epitaxial layers. The fin has side surfaces that are substantially vertical relative to the upper surface of the semiconductor substrate. The epitaxial layer has an upper surface that extends at an oblique angle with respect to the side surface of the fin. The FinFET can contain a contact over the metal-semiconductor compounds.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: January 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Kawasaki, Chung-hsun Lin
  • Patent number: 8329360
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Publication number: 20120299127
    Abstract: A dynamic quantity sensor device includes: first and second dynamic quantity sensors having first and second dynamic quantity detecting units; and first and second substrates, which are bonded to each other to provide first and second spaces. The first and second units are air-tightly accommodated in the first and second spaces, respectively. A SOI layer of the first substrate is divided into multiple semiconductor regions by trenches. First and second parts of the semiconductor regions provide the first and second units, respectively. The second part includes: a second movable semiconductor region having a second movable electrode, which is provided by a sacrifice etching of the embedded oxide film; and a second fixed semiconductor region having a second fixed electrode. The second sensor detects the second dynamic quantity by measuring a capacitance between the second movable and fixed electrodes, which is changeable in accordance with the second dynamic quantity.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 29, 2012
    Applicant: DENSO CORPORATION
    Inventors: Tetsuo FUJII, Keisuke GOTOH, Kenichi AO
  • Patent number: 8299613
    Abstract: The invention relates to a method for connecting two joining surfaces, particularly in the field of semiconductors, wherein at least one joining surface is produced by depositing a layer comprising 20 to 40% gold and 80 to 60% silver onto a substrate and selectively removing the silver from the deposited layer in order to produce a nanoporous gold layer as a joining surface. The joining surface with the nanoporous gold layer and an additional joining surface are disposed one above the other and pressed together.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: October 30, 2012
    Assignee: Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung E.V.
    Inventor: Hermann Oppermann
  • Patent number: 8278746
    Abstract: Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: October 2, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi-Chuan Ding, Chia-Ching Chen
  • Patent number: 8268674
    Abstract: A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. A lower-layer insulating film is provided under and around the semiconductor constituent. A plurality of lower-layer wirings are electrically connected to the electrodes for external connection of the semiconductor constituent, and provided under the lower-layer insulating film. An insulation layer is provided on the lower-layer insulating film in the periphery of the semiconductor constituent. An upper-layer insulating film is provided on the semiconductor constituent and the Insulation layer. A plurality of upper-layer wirings are provided on the upper-layer insulating film. A base plate on which the semiconductor constituent and the insulation layer are mounted is removed.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: September 18, 2012
    Assignee: Teramikros, Inc.
    Inventor: Hiroyasu Jobetto
  • Patent number: 8242007
    Abstract: Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: August 14, 2012
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Jong-ho Park, Chang-ki Jeon, Hyi-jeong Park
  • Patent number: 8232603
    Abstract: A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Gregory G. Freeman, Kevin McStay, Shreesh Narasimha
  • Publication number: 20120168873
    Abstract: Transmission gates, methods of fabricating transmission gates, and design structures for a transmission gate. The transmission gate includes an n-channel field effect transistor characterized by terminals that are asymmetrically doped and a p-channel field effect transistor characterized by terminals that are asymmetrically doped.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Publication number: 20120104538
    Abstract: Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 3, 2012
    Applicant: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Publication number: 20120086082
    Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 12, 2012
    Inventors: PIERRE MALINGE, JACK M. HIGMAN, SANJAY R. PARIHAR
  • Publication number: 20120045869
    Abstract: A low thermal conductivity material layer covers a peripheral portion of the bottom surface of the conductive plate of a chip bonder head. The center portion of the conductive plate is exposed or covered with another conductive plate laterally surrounded by the low thermal conductivity material layer. During bonding, the chip bonder head holds a first substrate upside down and heats the first substrate through the conductive plate. Heating of a fillet, i.e., the laterally extruding portion, of a pre-applied underfill material is reduced because the temperature at the exposed surfaces of the low thermal conductivity material layer is lower than the temperature at the bottom surface of the conductive plate. The longer curing time and the more uniform shape of the fillet in the bonded structure enhance the structural reliability of the bonded substrates.
    Type: Application
    Filed: August 23, 2010
    Publication date: February 23, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Gaynes, Jae-Woong Nah
  • Patent number: 8120164
    Abstract: A semiconductor chip package and printed circuit board assembly including the same which have a variable mounting orientation include a semiconductor chip disposed on a first surface of an insulating substrate, connectors symmetrically disposed at respective first and opposite second sides of the insulating substrate, a plurality of input/output connecting leads and power connecting leads electrically connected by connecting members to a plurality of internal circuits of the semiconductor chip, at least two internal circuits of the plurality of internal circuits being substantially similar circuits, and a radiating pad disposed on a second opposite surface of the insulating substrate and which is electrically connected to the semiconductor chip.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-woo Jeong, Yong-gwang Won
  • Publication number: 20120032271
    Abstract: A novel semiconductor inverter is presented. The semiconductor structure is simple and has a reduced number of semiconductor junctions. It offers the advantage of being very small in area, very fast and very efficient. The current conductivity from either of the two main terminals to the output terminal is controlled by the gate voltage by means of depleting and enhancing the areas underneath the gate oxide. The signal isolation is obtained mainly by the carrier depletion of the channel region. Having a reduced number of semiconductor junctions, the intrinsic current leakage can be very small. This inverter is the elementary component for latches, memory and logic elements based on this technology.
    Type: Application
    Filed: October 25, 2010
    Publication date: February 9, 2012
    Inventors: Fabio Alessio Marino, Paolo Menegoli
  • Patent number: 8093085
    Abstract: A method of forming a suspension object on a monolithic substrate is provided. A silicon base layer of the monolithic substrate has a circuit layer composed of at least one wet etching region, at least one circuit region, and at least one microstructure region. The wet etching region is used to partition the circuit region and the microstructure region, and extends downwards to a surface of the silicon base layer, so as to form an etching path for etching the silicon base layer from above the substrate. Next, an upper surface and a lower surface of the silicon base layer are respectively etched through dry etching, such that the microstructure region is suspended.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: January 10, 2012
    Assignee: Memsor Corporation
    Inventor: Siew Seong Tan
  • Patent number: 8084851
    Abstract: A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: December 27, 2011
    Assignee: Cufer Asset Ltd. L.L.C.
    Inventor: John Trezza
  • Patent number: 8084310
    Abstract: Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: December 27, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Bencherki Mebarki, Li Yan Miao, Christopher Dennis Bencher, Jen Shu
  • Publication number: 20110298058
    Abstract: FinFETs and methods of making. FinFETs are provided. The FinFET contains two or more fins over a semiconductor substrate; two or more epitaxial layers over side surfaces of the fins; and metal-semiconductor compounds over an upper surfaces of the epitaxial layers. The fin has side surfaces that are substantially vertical relative to the upper surface of the semiconductor substrate. The epitaxial layer has an upper surface that extends at an oblique angle with respect to the side surface of the fin. The FinFET can contain a contact over the metal-semiconductor compounds.
    Type: Application
    Filed: June 4, 2010
    Publication date: December 8, 2011
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventors: Hirohisa Kawasaki, Chung-hsun Lin
  • Publication number: 20110298114
    Abstract: A stacked leadframe assembly is disclosed. The stacked leadframe assembly includes a first die having a surface that defines a mounting plane, a first leadframe stacked over and attached to the first die, a second die stacked over and attached to the first leadframe; and a second leadframe stacked over and attached to the second die. The leadframes have die paddles with extended side panels that have attachment surfaces in the mounting plane.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 8, 2011
    Inventor: David Alan PRUITT
  • Publication number: 20110300668
    Abstract: An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 8, 2011
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventor: Pirooz Parvarandeh
  • Patent number: 8071454
    Abstract: A method for manufacturing a dielectric isolation type semiconductor device comprises: forming a plurality of trenches in a first region on a major surface of a semiconductor substrate; forming a first dielectric layer on the major surface of the semiconductor substrate and a first thick dielectric layer in the first region by oxidizing a surface of the semiconductor substrate; bonding a semiconductor layer of a first conductive type to the semiconductor substrate via the first dielectric layer; forming a first semiconductor region by implanting an impurity into a part of the semiconductor layer above the first thick dielectric layer; forming a second semiconductor region by implanting an impurity of a second conductive type into a part of the semiconductor layer so as to surround the first semiconductor region separating from the first semiconductor region.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: December 6, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hajime Akiyama
  • Publication number: 20110278539
    Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Patent number: 8058160
    Abstract: A method of forming the gate patterns of a nonvolatile memory device comprises stacking a gate insulating layer and a first conductive layer over a semiconductor substrate; forming isolation hard mask patterns over the first conductive layer; etching the first conductive layer using the isolation hard mask patterns as etch barriers, thus exposing the gate insulating layer; etching the gate insulating layer using the isolation hard mask patterns as etch barriers, thus exposing the semiconductor substrate; after exposing the semiconductor substrate, forming a passivation layer on the sidewalls of the first conductive layers and on the sidewalls of the gate insulating layers; and etching the semiconductor substrate using the passivation layer and the isolation hard mask patterns as etch barriers, thus forming trenches in the semiconductor substrate.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: November 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chan Sun Hyun
  • Patent number: 8053287
    Abstract: A method of making a backside illuminated sensor is provided. A substrate is provided and a high energy ion implantation is performed over the substrate to implant a first doped region. A layer is formed over the substrate and a self-align high energy ion implantation is performed over the substrate to implant a second doped region over the first doped region. The combined thickness of the first and second doped region is greater than 50 percent of thickness of the substrate and the distance between back surface of the substrate and the first and second doped regions is less than 50 percent of thickness of the substrate. In this way, an enlarged light sensing region is formed through which electrons generated from back surface of the surface may easily reach the pixel.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Hsu, Dun-Nian Yaung