Manufacture Of Specific Parts Of Devices (epo) Patents (Class 257/E21.536)

  • Patent number: 9890468
    Abstract: A method of making a breath sensing tube includes: (A) dispersing a nanowire material in a solution in a dielectriphoretic bath, such that the nanowire material is formed into individual nanowires and nanowire aggregates; (B) adsorbing the nanowire aggregates on a bath electrode through dielectrophoresis so as to obtain a nanowire-containing solution containing the individual nanowires; contacting sensor electrodes of a substrate with the nanowire-containing solution; and subjecting the nanowire-containing solution to dielectrophoresis, so that one of the individual nanowires is adsorbed to the sensor electrodes to interconnect the sensor electrodes.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: February 13, 2018
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chien-Chong Hong, Kuan-Wen Chen, Wei-Han Wang, Chung-Hsuan Wu
  • Patent number: 9647056
    Abstract: Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes. Moreover, each of the semiconductor devices may include a supporting pattern connected to sidewalls of the plurality of electrodes. Related methods of forming semiconductor devices are also provided. For example, the methods may include forming the supporting pattern before forming the plurality of electrodes.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: May 9, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junho Yoon, Gyungjin Min, Jaehong Park, Yongmoon Jang, Je-Woo Han
  • Patent number: 9035282
    Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christos D. Dimitrakopoulos, Keith E. Fogel, Jeehwan Kim, Hongsik Park
  • Patent number: 9035390
    Abstract: A thin film transistor substrate is equipped with: an insulating substrate (10a); a gate electrode (2) constituted by a stack of a first barrier metal layer (3) formed of titanium and disposed over the insulating substrate (10a), a first copper layer (4) disposed over the first barrier metal layer (3), and a second barrier metal layer (5) formed of titanium and disposed over the first copper layer (4); a gate insulating layer (7) disposed covering the gate electrode (2); and a semiconductor layer (8) disposed over the gate insulating layer (7), and having a channel region (C) disposed overlapping the gate electrode (2).
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 19, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tohru Amano
  • Patent number: 9024388
    Abstract: One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: May 5, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kisik Choi, Ruilong Xie
  • Patent number: 8895340
    Abstract: A process for forming a carbon nanotube field effect transistor (CNTFET) device includes site-specific nanoparticle deposition on a CNTFET that has one or more carbon nanotubes, a source electrode, a drain electrode, and a sacrificial electrode on a substrate with an interposed dielectric layer. The process includes control of PMMA removal and electrodeposition in order to select nanoparticle size and deposition location down to singular nanoparticle deposition. The CNTFET device resulting in ultra-sensitivity for various bio-sensing applications, including detection of glucose at hypoglycemic levels.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: November 25, 2014
    Assignee: Georgetown University
    Inventors: Makarand Paranjape, Yian Liu
  • Patent number: 8884390
    Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-I Cheng, Chih-Kang Chao, Volume Chien, Chi-Cherng Jeng, Pin Chia Su, Chih-Mu Huang
  • Patent number: 8822266
    Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: September 2, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Peter Deane, Reda R. Razouk
  • Patent number: 8796813
    Abstract: A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: August 5, 2014
    Assignee: MediaTek Inc.
    Inventors: Ming-Da Tsai, George Chien, Cheng-Chou Hung
  • Patent number: 8691658
    Abstract: A method for aligning an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned back stack of semiconductor wafers. The method for aligning the electronic CMOS structure may include forming alignment marks in the process of fabricating the structure to be buried on a front side, which is used for bonding of the semiconductor wafer, which includes the structure to be buried. The alignment marks may be formed on the edge of the semiconductor wafer. The method for aligning the electronic CMOS structure may include providing a cover wafer with first thinned portions of the wafer thickness provided from the bonding side at positions corresponding to positions of the alignment marks.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: April 8, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventors: Holger Klingner, Jens Ungelenk
  • Patent number: 8633051
    Abstract: An object is to prevent a reduction of definition (or resolution) (a peripheral blur) caused when reflected light enters a photoelectric conversion element arranged at a periphery of a photoelectric conversion element arranged at a predetermined address. A semiconductor device is manufactured through the steps of: forming a structure having a first light-transmitting substrate, a plurality of photoelectric conversion elements over the first light-transmitting substrate, a second light-transmitting substrate provided so as to face the plurality of photoelectric conversion elements, a sealant arranged so as to bond the first light-transmitting substrate and the second light-transmitting substrate and surround the plurality of photoelectric conversion elements; and thinning the first light-transmitting substrate by wet etching.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: January 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Munehiro Kozuma, Hikaru Tamura, Kazuko Yamawaki, Takashi Hamada, Shunpei Yamazaki
  • Publication number: 20140001642
    Abstract: Interposers for use in the fabrication of electronic devices include semiconductor-on-insulator structures having fluidic microchannels therein. The interposers may include a multi-layer body in which a semiconductor material is bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel may extend in a lateral direction through at least one of the layer of dielectric material and the semiconductor material. The interposers may include redistribution layers and electrical contacts on opposing sides thereof. Semiconductor structures include one or more semiconductor devices coupled with such interposers. Such interposers and semiconductor structures may be formed by fabricating a semiconductor-on-insulator type structure using a direct bonding method and defining one or more fluidic microchannels at a bonding interface during the direct bonding process.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: SOITEC
    Inventor: Mariam Sadaka
  • Patent number: 8536683
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Patent number: 8525354
    Abstract: A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: September 3, 2013
    Assignee: United Microelectronics Corporation
    Inventors: Hui-Min Wu, Ming-I Wang, Kuan-Yu Wang, Kun-Che Hsieh, Chien-Hsin Huang
  • Patent number: 8513800
    Abstract: After a semiconductor chip is cut out, an In-10 atom % Ag pellet is placed on a metal film. Next, an epoxy sheet on a stiffener is stuck to a ceramic substrate. At this time, the In alloy pellet is sandwiched between a central protrusion portion and the metal film. Then, an In alloy film is formed from the In alloy pellet by heating, melting, and then cooling the In alloy pellet. As a result, the semiconductor chip and a heat spreader are bonded via the metal film and the In alloy film.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: August 20, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takaki Kurita, Osamu Igawa
  • Publication number: 20130163852
    Abstract: In one embodiment, a semiconductor target for determining overlay error, if any, between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The target comprises at least a plurality of first structures that are invariant for a plurality of first rotation angles with respect to a first center of symmetry (COS) of the first structures and a plurality of second structures that are invariant for a plurality of second rotation angles with respect to a second COS of the second structures. The first rotation angles differ from the second rotation angles, and first structures and second structures are formed on different layers of the substrate or separately generated patterns on a same layer of the substrate.
    Type: Application
    Filed: December 27, 2011
    Publication date: June 27, 2013
    Applicant: KLA-TENCOR TECHNOLOGIES CORPORATION
    Inventor: Mark Ghinovker
  • Patent number: 8461021
    Abstract: The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring structure over the seal ring region, forming a second seal ring structure over the seal ring region and adjacent to the first seal ring structure, and forming a first passivation layer disposed over the first and second seal ring structures. A semiconductor device fabricated by such a method is also provided.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 11, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dun-Nian Yaung, Jen-Cheng Liu, Jen-Shyan Lin, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 8435821
    Abstract: A sensor and method for fabricating a sensor is disclosed that in one embodiment bonds an etched semiconductor substrate wafer to an etched device wafer comprising a silicon on insulator wafer to create a suspended structure, the flexure of which is determined by an embedded sensing element to measure absolute pressure. Interconnect channels embedded in the sensor facilitate streamlined packaging of the device while accommodating interconnectivity with other devices.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: May 7, 2013
    Assignee: General Electric Company
    Inventors: Sisira Kankanam Gamage, Naresh Venkata Mantravadi, Michael Klitzke, Terry Lee Cookson
  • Publication number: 20130095580
    Abstract: A method for formation of a semiconductor device including a first mono-crystalline layer comprising first transistors and first alignment marks, the method comprising forming a doped layer within a wafer, forming a second mono-crystalline layer on top of the first mono-crystalline layer by transferring at least a portion of the doped layer using layer transfer step, and processing second transistors on the second mono-crystalline layer comprising a step of forming a gate dielectric, wherein the second transistors are horizontally oriented.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 18, 2013
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Ze'ev Wurman
  • Patent number: 8390117
    Abstract: A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode 9 is formed in a region outside of an element mounting region of a substrate 5. The projected electrode 9 includes a protruding portion that protrudes from the front face of a molding resin portion 10. The distal end of the protruding portion is a flat face 13. In addition, a portion of the projected electrode 9 whose cross section is larger than the protruding portion is positioned inside the molding resin portion 10.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: March 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshiaki Shimizu, Yuichiro Yamada, Toshiyuki Fukuda
  • Patent number: 8357561
    Abstract: A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: January 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chi Fu, Gwo-Yuh Shiau, Liang-Lung Yao, Yuan-Chih Hsieh, Feng-Jia Shiu
  • Publication number: 20120326278
    Abstract: A mask for a semiconductor process step includes an indicia section. The indicia section on the mask is used to produce a field of separated polygon elements with a defined negative space in the field providing an indicia.
    Type: Application
    Filed: June 23, 2011
    Publication date: December 27, 2012
    Applicant: EXAR CORPORATION
    Inventors: OSCAR JOSEPH SALDANHA, PEKKA KALERVO OJALA, DAVID RICHARD MOOG
  • Patent number: 8338917
    Abstract: The present disclosure provides a method of fabricating a semiconductor device, the method including providing a substrate having a seal ring region and a circuit region, forming a first seal ring structure over the seal ring region, forming a second seal ring structure over the seal ring region and adjacent to the first seal ring structure, and forming a first passivation layer disposed over the first and second seal ring structures. A semiconductor device fabricated by such a method is also provided.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: December 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dun-Nian Yaung, Jen-Cheng Liu, Jeng-Shyan Lin, Wen-De Wang, Shu-Ting Tsai
  • Patent number: 8338296
    Abstract: The present disclosure is related to a method for forming a catalyst nanoparticle on a metal surface, the nanoparticle being suitable for growing a single nanostructure, in particular a carbon nanotube, the method comprising at least the steps of: providing a substrate, having a metal layer on at least a portion of the substrate surface, depositing a sacrificial layer at least on the metal layer, producing a small hole in the sacrificial layer, thereby exposing the metal layer, providing a single catalyst nanoparticle into the hole, removing the sacrificial layer. The disclosure is further related to growing a carbon nanotube from the catalyst nanoparticle.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: December 25, 2012
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. LEUVEN R&D
    Inventors: Hari Pathangi Sriraman, Ann Witvrouw, Philippe M. Vereecken
  • Patent number: 8324714
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface in which a semiconductor element region where a plurality of functional elements are formed is formed; a multilevel wiring layer disposed on the main surface of the semiconductor substrate; a first organic insulating material layer disposed on the multilevel wiring layer; a groove that penetrates the multilevel wiring layer on a scribe region that surrounds the semiconductor element region; and an organic insulating material that is spaced from the first organic insulating material layer and disposed in the groove.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: December 4, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Jun Tsukakoshi, Yoshitaka Aiba
  • Publication number: 20120299204
    Abstract: A method for fabricating an overlay mark, including the steps of: forming a patterned layer on a substrate, wherein the patterned layer comprises at least one mark element forming region, wherein each mark element forming region comprises two column recesses and a plurality of row recesses, and the row recesses connect the two column recesses; growing a mark material from the sidewalls of the column recesses and the row recesses so that the mark material merges in the column recesses and the row recesses; and removing the patterned layer. Consequently, an overlay mark including mark elements with high image contrast is fabricated.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Chui Fu Chiu
  • Patent number: 8298919
    Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shoetsu Kogawa, Satoru Nakayama, Seigo Kamata, Shigemitsu Seito
  • Patent number: 8293549
    Abstract: A method of fabricating a pixel array substrate is disclosed. The reflective pixel array substrate can be made by utilizing five photo masks only. The reflective pixel array substrate includes a substrate, a thin film transistor, a reflective electrode, an insulating layer and numerous protruding bumps. The step between the protrusion bump and the substrate cause the reflective electrode thereon to have a corrugated structure. The gate electrode of the thin film transistor and the protruding bumps are made of a same conductive layer. The drain electrode connects the reflective electrode, and the drain electrode and the reflective electrode are made of a same conductive layer.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: October 23, 2012
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Kai-Hung Huang, Li-Wen Wang
  • Patent number: 8288841
    Abstract: A handle wafer for microelectronic functional wafers, including at least one cavity through the thickness of the wafer, this cavity including a viewing window in solid or solidified material.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: October 16, 2012
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Jean-Charles Souriau, Stéphane Caplet
  • Patent number: 8288211
    Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate. At least one of the substrates may include a raised feature formed under at least one of the metal layers. One of the metal layer may have a diffusion barrier layer and a “keeper” layer formed thereover, wherein the keeper layers keeps the metal confined to a particular area. By using such a “keeper” layer, the substrate components may be heated to clean their surfaces, without activating or spending the bonding mechanism.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: October 16, 2012
    Assignee: Innovative Micro Technology
    Inventors: John S. Foster, Alok Paranjpye, Douglas L. Thompson
  • Patent number: 8288269
    Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: October 16, 2012
    Assignee: LSI Corporation
    Inventors: Jeffrey Hall, Shawn Nikoukary, Amar Amin, Michael Jenkins
  • Patent number: 8278696
    Abstract: A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a charge storage insulating film formed on the tunnel insulating film and including at least two separated low oxygen concentration portions and a high oxygen concentration portion positioned between the adjacent low oxygen concentration portions and having a higher oxygen concentration than the low oxygen concentration portions, a charge block insulating film formed on the charge storage insulating film, and control gate electrodes formed on the charge block insulating film and above the low oxygen concentration portions.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: October 2, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Ryota Fujitsuka
  • Patent number: 8264064
    Abstract: A semiconductor device includes a semiconductor substrate on which an internal circuit is formed in a central position an insulating layer formed over the semiconductor substrate, and a moisture-resistant ring formed by a metal plug embedded in the insulating layer, the moisture-resistant ring surrounding the internal circuit, the moisture-resistant ring extending over the semiconductor substrate in a shape, the moisture-resistant ring including a first extending portion linearly extending in a first direction in parallel to the surface of the semiconductor substrate, a vertical portion connected to the first extending portion extending in a second direction orthogonal to the first extending portion, and a second extending portion orthogonal to the vertical portion and parallel to the surface of the semiconductor substrate, the second extending portion spaced apart from the first extending portion, the second extending portion crossing the vertical portion.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: September 11, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kenichi Watanabe
  • Patent number: 8242603
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: August 14, 2012
    Assignee: Agere Systems Inc.
    Inventors: Joseph J. Check, Edward B. Harris, Lyle K. Mantz, II, Richard R. Kiser, Patricia J. Leith
  • Patent number: 8236592
    Abstract: A method for forming a semiconductor device is provided including processing a wafer having a target material; forming a first pattern over the target material; forming a protection layer over the first pattern; and forming a second pattern, over the target material and not over the protection layer, without an etching step between the forming the first pattern and the forming the second pattern.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: August 7, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ryoung-han Kim, Thomas Ingolf Wallow, Harry Jay Levinson, Jongwook Kye, Alden R. Acheta
  • Patent number: 8236690
    Abstract: A method for fabricating a semiconductor package substrate, including: preparing a copper clad laminate and half etching a copper foil on a wire bonding pad side of the copper clad laminate; depositing a first etching resist on the opposite sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: August 7, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyoung Ro Yoon, Young Hwan Shin, Yoon Su Kim, Tae Gon Lee
  • Publication number: 20120168752
    Abstract: The invention provides a testkey structure for testing a chip. The testkey structure includes a metal pad and a first groove, wherein the first groove is disposed on the metal pad. The first groove is located between a first signal lead and a second signal lead of the chip. According to the first groove, the first signal lead and the second signal lead could be separated from each other to prevent the first signal lead and the second signal lead from shorting.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Inventor: Kun-Tai Wu
  • Patent number: 8187920
    Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: May 29, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Anuraag Mohan, Peter Smeys
  • Patent number: 8183700
    Abstract: Many holes are formed in an interlayer insulating film and the surface of the interlayer insulating film is covered with a metal film, with its surface undulated by openings or recesses formed to scatter reflection light. The size of the recesses is about the size of contact holes of elements. Hence the recesses are not detectable by an image recognition apparatus. The size of the metal film, however, is set so that it can be detected by the image recognition apparatus.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: May 22, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Mutsuo Nishikawa, Kazuhiko Ikoma
  • Patent number: 8178429
    Abstract: Fabrication of a semiconductor structure is achieved by using a Dip Pen Nanolithography (DPN) tip to apply a metal catalyst to a prepared substrate. The catalyst is applied in a predetermined pattern, and crystal growth is established at the catalyst site.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 15, 2012
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Ryan P. Lu, Ayax D. Ramirez, Stephen D. Russell
  • Publication number: 20120112256
    Abstract: Semiconductor devices and methods of fabricating the devices are provided. An example device may include a substrate and a gate structure on the substrate. The gate structure includes a control gate having at least three distinct gate regions. First and second control gate regions are configured as a first field type, such as a high-gate or low-gate type. A third control gate region configured as a second field type (different from the first field type) is at least partially disposed between the first and second control gate regions.
    Type: Application
    Filed: November 4, 2010
    Publication date: May 10, 2012
    Applicant: Globalfoundries Singapore Pte, Ltd.
    Inventors: Shyue Seng Tan, Ying Keung Leung, Elgin Quek
  • Patent number: 8169059
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Oliver Nagy
  • Patent number: 8163656
    Abstract: In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto the exposed surface. Under pressure, the soft material flows laterally between the guiding plate and the substrate. Such pressure induced flow can reduce the lateral dimension of line spacing or the size of holes and increase the size of mesas. The same process also can repair defects such as line edge roughness and sloped sidewalls. This process will be referred to herein as pressed self-perfection by liquefaction or P-SPEL.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: April 24, 2012
    Inventors: Stephen Y. Chou, Ying Wang, Xiaogan Liang, Yixing Liang
  • Patent number: 8163657
    Abstract: In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto the exposed surface. Under pressure, the soft material flows laterally between the guiding plate and the substrate. Such pressure induced flow can reduce the lateral dimension of line spacing or the size of holes and increase the size of mesas. The same process also can repair defects such as line edge roughness and sloped sidewalls. This process will be referred to herein as pressed self-perfection by liquefaction or P-SPEL.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: April 24, 2012
    Inventors: Stephen Y. Chou, Ying Wang, Xiaogan Liang, Yixing Liang
  • Publication number: 20120091598
    Abstract: A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Ren Cheng, Yi-Hsien Chang, Allen Timothy Chang, Ching-Ray Chen, Li-Cheng Chu, Hung-Hua Lin, Yuan-Chih Hsieh, Lan-Lin Chao
  • Publication number: 20120083102
    Abstract: An improved, lower cost method of processing substrates, such as to create solar cells is disclosed. In addition, a modified substrate carrier is disclosed. The carriers typically used to carry the substrates are modified so as to serve as shadow masks for a patterned implant. In some embodiments, various patterns can be created using the carriers such that different process steps can be performed on the substrate by changing the carrier or the position with the carrier. In addition, since the alignment of the substrate to the carrier is critical, the carrier may contain alignment features to insure that the substrate is positioned properly on the carrier. In some embodiments, gravity is used to hold the substrate on the carrier, and therefore, the ions are directed so that the ion beam travels upward toward the bottom side of the carrier.
    Type: Application
    Filed: October 1, 2010
    Publication date: April 5, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Nicholas Bateman, Kevin Daniels, Atul Gupta, Russell Low, Benjamin Riordon, Robert Mitchell, Steven Anella
  • Patent number: 8148189
    Abstract: A method is described to create a thin semiconductor lamina adhered to a ceramic body. The method includes defining a cleave plane in a semiconductor donor body, applying a ceramic mixture to a first face of the semiconductor body, the ceramic mixture including ceramic powder and a binder, curing the ceramic mixture to form a ceramic body, and cleaving a lamina from the semiconductor donor body at the cleave plane, the lamina remaining adhered to the ceramic body. Forming the ceramic body this way allows outgassing of volatiles during the curing step. Devices can be formed in the lamina, including photovoltaic devices. The ceramic body and lamina can withstand high processing temperatures. In some embodiments, the ceramic body may be conductive.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: April 3, 2012
    Assignee: Twin Creeks Technologies, Inc.
    Inventors: Aditya Agarwal, Kathy J Jackson
  • Patent number: 8148275
    Abstract: A method for forming dielectric films including metal nitride silicate on a silicon substrate, comprises a first step of depositing a film containing metal and silicon on a silicon substrate in a non-oxidizing atmosphere using a sputtering method; a second step of forming a film containing nitrogen, metal and silicon by nitriding the film containing metal and silicon; and a third step of forming a metal nitride silicate film by oxidizing the film containing nitrogen, metal and silicon.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: April 3, 2012
    Assignees: Canon Kabushiki Kaisha, Canon Anelva Corporation
    Inventors: Yusuke Fukuchi, Naomu Kitano
  • Publication number: 20120074591
    Abstract: A semiconductor wafer assembly formed by bonding a support wafer to a thin wafer using a double-sided bonding release tape. The support wafer provides support for the thin target wafer such that existing handling tools can accommodate transporting and processing the assembly without compromising the profile of the thin target wafer.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventor: Arthur Paul Riaf
  • Patent number: 8139173
    Abstract: A liquid crystal display, having an improved application of electric field to the molecules of liquid crystal, includes a substrate and a pixel array bonded to the surface of this substrate, and the pixel array includes at least a thin-film transistor and a pixel electrode connected with this thin-film transistor, and the pixel electrode is formed in a layer higher than the thin-film transistor in relation to the substrate.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: March 20, 2012
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Tetsufumi Kawamura, Takeshi Sato, Mutsuko Hatano, Mieko Matsumura