For Group Iii-v Compound Semiconductor Integrated Circuits (epo) Patents (Class 257/E21.539)
  • Patent number: 8722526
    Abstract: Embodiments relate to growing an epitaxy gallium-nitride (GaN) layer on a porous silicon (Si) substrate. The porous Si substrate has a larger surface area compared to non-porous Si substrate to distribute and accommodate stress caused by materials deposited on the substrate. An interface adjustment layer (e.g., transition metal silicide layer) is formed on the porous silicon substrate to promote growth of a buffer layer. A buffer layer formed for GaN layer may then be formed on the silicon substrate. A seed-layer for epitaxial growth of GaN layer is then formed on the buffer layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: May 13, 2014
    Assignee: Veeco ALD Inc.
    Inventor: Sang In Lee
  • Patent number: 8697505
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a first layer. A second layer is disposed on the first layer and different from the first layer in composition. An interface is between the first layer and the second layer. A third layer is disposed on the second layer. A gate is disposed on the third layer. A source feature and a drain feature are disposed on opposite sides of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second and the third layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Chen, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 8569161
    Abstract: Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a method for fabricating a semiconductor device comprises forming a dielectric layer on an active side of a semiconductor substrate. The dielectric layer has openings aligned with corresponding wirebond sites at the active side of the substrate. The method further includes forming a plurality of wirebond sites located at the openings in the dielectric layer. The wirebond sites are electrically coupled to an integrated circuit in the semiconductor substrate and electrically isolated from each other. Individual wirebond sites are formed by electrolessly depositing nickel into the openings and forming a wirebond film on the nickel without forming a seam between the nickel and the dielectric layer.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Lindgren
  • Publication number: 20120217639
    Abstract: A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween.
    Type: Application
    Filed: September 2, 2010
    Publication date: August 30, 2012
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAIHSA
    Inventors: Masahiro Sugimoto, Akinori Seki, Akira Kawahashi, Yasuo Takahashi, Masakatsu Maeda
  • Publication number: 20120208357
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 16, 2012
    Applicant: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
  • Patent number: 8143147
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: March 27, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
  • Patent number: 8035131
    Abstract: A method for forming a nitride semiconductor laminated structure includes forming a first layer that is an n-type or i-type first layer composed of a group III nitride semiconductor using an H2 carrier gas; forming a second layer by laminating a p-type second layer composed of a group III nitride semiconductor and containing Mg on the first layer using an H2 carrier gas; and forming a third layer that is an n-type or i-type third layer composed of a group III nitride semiconductor on the second layer using an H2 carrier gas after forming the second layer. A method for manufacturing a nitride semiconductor device includes the method steps for forming the nitride semiconductor laminated structure.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: October 11, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Hirotaka Otake, Hiroaki Ohta, Shin Egami
  • Patent number: 7727792
    Abstract: A laser diode epitaxial wafer has an n-type GaAs substrate, an n-type cladding layer formed on the n-type GaAs substrate, an active layer formed on the n-type cladding layer, and a p-type cladding layer formed on the active layer. The n-type cladding layer, the active layer, and the p-type cladding layer are formed of an AlGaInP-based material. The p-type cladding layer has carbon as a p-type impurity. The p-type cladding layer has a carrier concentration in the range of not less than 8.0×1017 cm?3 and not more than 1.5×1018 cm?3.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: June 1, 2010
    Assignee: Hitachi Cable, Ltd.
    Inventor: Ken Kurosu
  • Patent number: 7700387
    Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: April 20, 2010
    Assignee: The United States of America as Represented by the Director, National Security Agency
    Inventors: John L. Fitz, Daniel S. Hinkel, Scott C. Horst
  • Patent number: 7678593
    Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: March 16, 2010
    Assignee: The United States of America, as represented by the Director, National Security Agency
    Inventors: John L. Fitz, Daniel S. Hinkel, Scott C. Horst
  • Patent number: RE45084
    Abstract: The present invention is a method of fabricating an optical device using multiple sacrificial spacer layers. The first step in this process is to fabricate the underlying base structure and deposit an optical structure thereon. A facet is then created at the ends of the optical structure and alternating sacrificial and intermediate layers are fabricated on the device. A mask layer is deposited on the structure, with openings created in the layers to allow use of an etchant. User-defined portions of the spacer layers are subsequently removed with the etchant to create air gaps between the intermediate layers.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: August 19, 2014
    Assignee: National Security Agency
    Inventors: John L. Fitz, Daniel S. Hinkel, Scott C. Horst