Abstract: A semiconductor substrate capable of detecting operating current of a MOSFET and diode current in a miniaturized MOSFET such as a trench-gate type MOSFET is provided. A semiconductor substrate includes a main current region and a current sensing region in which current smaller than main current flowing in the main current region flows. The main current region has a source electrode disposed on a main surface, the source electrode being in contact with a p-type semiconductor region (body) and an n+-type semiconductor region (source), and the current sensing region has a MOSFET current detecting electrode and a diode current detecting electrode on a main surface, the MOSFET current detecting electrode being in contact with the p-type semiconductor region (body) and the n+-type semiconductor region (source), the diode current detecting electrode being in contact with the p-type semiconductor region (body).

Abstract: Provided is a method for creating a mask blank that include a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detect of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer.

Abstract: A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

Abstract: A double patterned semiconductor structure is provided. The structure includes a first patterned and cured low-k structure located on a first portion of an antireflective coating, and a second patterned and cured low-k structure located on a second portion of the antireflective coating, wherein the second patterned and cured low-k structure is spaced apart from the first patterned and cured low-k dielectric structure.

Abstract: A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.

Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

Abstract: A multichip module (MCM) has redundant I/O connections between its dice. That is, the number of inter-die I/O connections used is larger than the number of connections ordinarily used to provide connectivity between the dice. Defective connections are discovered through testing after MCM assembly and avoided, with signals being rerouted through good (e.g., not defective) redundant connections. The testing can be done at assembly time and the results stored in nonvolatile memory. Alternatively, the MCM can perform the testing itself dynamically, e.g., at power up, and use the test results to configure the inter-die I/O connections.

Abstract: A method and test circuit for electrically measuring the critical dimension of a fin of a FinFET is disclosed. The method comprises measuring the resistance of a first gate test structure, measuring the resistance of a second gate test structure, computing a linear equation relating sheet resistance to gate width, computing a Y intercept value of the linear equation to derive an external resistance value, computing a sheet resistance value for the first gate test structure based on the external resistance value, measuring the resistance of a doped fin test structure, and computing a critical dimension of a fin based on the sheet resistance value.

Abstract: To provide a semiconductor wafer surface protection sheet having good adhesion to irregularities on a patterned surface of a semiconductor wafer and having good peelability after wafer grinding. Specifically, a semiconductor wafer surface protection sheet is provided that includes a base layer having a tensile elasticity at 25° C., E(25), of 1 GPa or more; a resin layer A that satisfies the condition EA(60)/EA(25)<0.1, where EA(25) is a tensile elasticity at 25° C. and EA(60) is a tensile elasticity at 60° C., the EA(60) ranging from 0.005 MPa to 1 MPa; and a resin layer B having a tensile elasticity at 60° C., EB(60), of 1 MPa or more and having a thickness of 0.1 ?m to less than 100 ?m, the EB(60) being larger than the EA(60) of the resin layer A.

Abstract: The present invention discloses a substrate including a flexible film, a plurality of sprocket holes disposed along a first direction on two sides of the flexible film, and a plurality of first chip zones disposed along the first direction on the flexible film, of which each first chip zone includes at least a testing module, an input module, a chip and an output module disposed along a second direction, where the first direction is orthogonal to the second direction.

Abstract: A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.

Abstract: Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node.

Abstract: A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a spatial alignment in more than one direction between the semiconductor die and another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies and/or an angular alignment of the semiconductor dies to be determined.

Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.

Abstract: The present invention is directed to an interconnect for an implantable medical device. The interconnect includes a first conductive layer, a second conductive layer introduced over the first conductive layer, and a third conductive layer introduced over the second conductive layer. One of the first conductive layer, the second conductive layer, and the third conductive layer comprises titanium-niobium (Ti—Nb).

Abstract: Disclosed herein are various electrical test structures for evaluating semiconductor devices that employ high-k dielectrics and/or metal gate electrode structures. In one example, the test structure disclosed herein includes a first line formed over an isolation material, a first active region defined in a semiconducting substrate and a first extension formed over an isolation material, the first extension extending from a first side of the first line, wherein the first extension is positioned proximate the first active region and wherein the first line and the first extension are comprised of at least one of a high-k layer of insulating material or a metal layer.

Abstract: A semiconductor structure includes semiconductor devices on a substrate, a moisture barrier on the substrate surrounding the semiconductor devices, and a metal conductive redistribution layer formed over the moisture barrier. The metal conductive redistribution layer and the moisture barrier define a closed compartment containing the semiconductor devices.

Abstract: A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.

Abstract: Methods and systems for communicating via flip-chip die and package waveguides are disclosed and may include communicating one or more signals between sections of an integrated circuit via one or more waveguides integrated in a multi-layer package. The integrated circuit may be bonded to the multi-layer package. The waveguides may be configured via switches in the integrated circuit or by MEMS switches integrated in the multi-layer package. The signals may include a microwave signal and a low frequency control signal that may configure the microwave signal. The low frequency control signal may include a digital signal. The waveguides may comprise metal and/or semiconductor layers deposited on and/or embedded within the multi-layer package.

Abstract: Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a base material, and a developable polymer resist material is applied over the grafted polymer brush material. The resist material is at least partially miscible in the grafted polymer brush material. As such, the resist material at least partially dissolves within the grafted polymer brush material to form an intertwined material of grafted polymer brush macromolecules and resist polymer macromolecules. Adhesion between the developable polymer resist and the base material may be thereby enhanced. Also disclosed are related semiconductor device structures.

Abstract: In one embodiment, a body region of a body-contacted silicon-on-insulator (SOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) is connected to a gate of another MOSFET in a sensing circuit to form a floating body node. The voltage at the floating body node is accurately obtained at the output of the sensing circuit and used to provide an estimate of required floating body voltage over a full device operating range.

Abstract: Methods and structure are provided to facilitate isolation of respective ground plane regions in an SOTB semiconductor device. In one aspect a shallow STI trench can be combined with Si:C or Si:C/SiGe layers to confine n-type and p-type regions. In a further aspect, Ge can be implanted at the bottom of a shallow STI trench and subsequently oxidized to form SiGe oxide thereby extending the effective isolation provided by the shallow STI trench. In an aspect, a shallow STI trench can be extended to expose an underlying layer of SiGe, wherein the SiGe is subsequently oxidized to extending the effective isolation provide by the shallow STI trench. Such aspects enable a shallow STI trench to be seamlessly filled while having an extended region of isolation.

Abstract: Methods and systems for configuring one or more electrical waveguides in an integrated circuit by adjusting a geometry of the one or more electrical waveguides, and communicating one or more electrical signals between components within the integrated circuit via the one or more electrical waveguides. The geometry of the one or more electrical waveguides may be configured by adjusting a length of the one or more electrical waveguides utilizing switches in the integrated circuit. The switches may include CMOS transistors. The one or more signals may include a microwave signal and a low frequency digital control signal that configures the microwave signal. The electrical waveguides may include metal and/or semiconductor layers deposited on and/or embedded within the integrated circuit.

Abstract: Whether there is a defect such as chipping of a die or separation of a resin in a wafer level package is electrically detected. A peripheral wiring is disposed along four peripheries of a semiconductor substrate outside a circuit region and pad electrodes P1-P8. The peripheral wiring is formed on the semiconductor substrate and is made of a metal layer that is the same layer as or an upper layer of a metal layer forming the pad electrodes P1-P8, or a polysilicon layer. A power supply electric potential Vcc is applied to a first end of the peripheral wiring, while a ground electric potential Vss is applied to a second end of the peripheral wiring through a resistor R2. A detection circuit is connected to a connecting node N1 between the peripheral wiring and the resistor R2, and is structured to generate an anomaly detection signal ERRFLG based on an electric potential at the connecting node N1.

Abstract: A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.

Abstract: A 3D chip package is disclosed that includes a carrier substrate with a first cavity and a second cavity formed therein. A first structure is attached to the carrier substrate at least partially in the first cavity, and a second structure is attached to the carrier substrate at least partially in the second cavity, where the first and second structures include electrical circuitry. A shield layer may be disposed between the carrier substrate and the first structure and/or the second structure for isolating the first structure and/or the second structure at least one of electrically, magnetically, optically, or thermally. In some embodiments, the shield layer may be a dielectric shield layer for dielectrically coupling the first structure and the second structure. The first structure and the second structure may be homogeneous or heterogeneous.

Abstract: A chip includes: a chip body; and a metal layer formed on the chip body, and including a metal interconnect region electrically connected to the chip body, a light trapping region, and a light reflective region that adjoins the light trapping region and that is able to reflect light. The light trapping region is formed with a plurality of gaps and has a plurality of metal members. Adjacent ones of the metal members are separated by the gaps. Each of the gaps is configured with a width in such a manner that most light irradiating the light trapping region will pass through the gaps and be trapped in the chip body so as to form brightness contrast between the light trapping region and the light reflective region.

Abstract: A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.

Abstract: An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad.

Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.

Abstract: A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded.

Abstract: Provided is a semiconductor chip having a double bump structure. The semiconductor chip may include a semiconductor substrate, a circuit region on a surface of the semiconductor substrate, a pad on the semiconductor substrate and connected to the circuit region, a first bump on the pad, and a second bump on the first bump. The second bump may be arranged at one side of an upper surface of the first bump and the upper surface of the first bump may include a test area configured to interface with a probe tip, wherein the test area is an area of the upper surface of the first bump exposed by the second bump.

Abstract: A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip's direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.

Abstract: A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a vertical spacing between a surface of the semiconductor die and a surface of another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies to be determined.

Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer that has a portion over the metal pad. A dummy pattern is disposed adjacent to the metal pad. The dummy pattern is level with, and is formed of a same material as, the metal pad. The dummy pattern forms at least a partial ring surrounding at least a third of the metal pad.

Abstract: A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits.

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.

Abstract: An embodiment of a testing system for carrying out electrical testing of at least one first through via extending, at least in part, through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the first through via and to electrical-connection elements carried by the first body for electrical connection towards the outside; the first electrical test circuit enables detection of at least one electrical parameter of the first through via through the electrical-connection elements.

Abstract: Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.

Abstract: A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by a current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, a second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first via hole wiring is surrounded.

Abstract: An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride.

Abstract: A first presspin includes a foot, whereby a base of the foot is provided for contacting a contact element of a power semiconductor device, such as within a power semiconductor module including a base plate and at least one power semiconductor device, which is arranged on the base plate and contacted by at least one further presspin. An insulation means is provided for electrically an outer surface of the foot. A power semiconductor module is also provided including a base plate, at least one power semiconductor device arranged on the base plate, and at least one of the aforementioned first presspin provided with the aforementioned insulation means. A power semiconductor module assembly is also provided including multiple power semiconductor modules as specified above, whereby the power semiconductor modules are arranged side by side to each other with electric connections between adjacent power semiconductor modules.

Abstract: An integrated circuit configured for at-speed testing is described. The integrated circuit includes a first die. The first die includes a transition launch point. The integrated circuit also includes a second die. The second die includes a first observe point. The integrated circuit further includes a first through silicon via. The first through silicon via couples the first die to the second die.

Abstract: Antenna switch modules and methods of making the same are provided. In certain implementations, an antenna switch module includes a package substrate, an integrated filter, and a silicon on insulator (SOI) die attached to the package substrate. The SOI die includes a capacitor configured to operate in the integrated filter and a multi throw switch for selecting amongst the RF signal paths. In some implementations, a surface mount inductor is attached to the package substrate adjacent the SOI die and is configured to operate in the integrated filter with the capacitor. In certain implementations, the inductor is formed from a conductive layer of the package substrate disposed beneath a layer of the package substrate used to attach the SOI die.

Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device package are disclosed. A method of manufacturing a semiconductor device comprises the steps of testing the semiconductor device using at least a first monitoring pad connected to an internal circuit of the semiconductor device via at least a first fuse circuit; after testing the semiconductor device, electrically disconnecting the first monitoring pad from the internal circuit by opening the first fuse circuit; and after testing of the semiconductor device, electrically connecting at least a first auxiliary pad to the first monitoring pad with at least a first connecting terminal, wherein the first auxiliary pad is connected, through at least a first conductive line, to at least a first power pad of the semiconductor device.

Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.

Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.

Abstract: A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.