Abstract: A flexible foil-based package is disclosed which comprises at least one flexible foil substrate on which at least one electronic device is mounted in flip-chip mounting technology. The flexible foil substrate is bent so that a recess is created in which the electronic device is arranged. A casting compound is applied to cover the electronic device.

Abstract: A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.

Abstract: A substrate structure includes at least one detachable first substrate unit and a substrate body. The detachable first substrate unit includes a plurality of corners and a plurality of first engagement portions. Each of the first engagement portions is disposed at each of the corners of the detachable first substrate unit. The substrate body includes a plurality of second substrate units, at least one opening and a plurality of second engagement portions. The opening is substantially defined by a plurality of sidewalls of the second substrate units, and includes a plurality of corners. Each of the second engagement portions is disposed at each of the corners of the opening. The detachable first substrate unit is disposed in the opening, and the second engagement portions are engaged with the first engagement portions.

Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

Abstract: Disclosed is a printed circuit unit that includes a flexible member which has an upper surface and a lower surface and includes a first end and a second end. An output pad is disposed at the first end and is implemented to be connected to a bent display panel. A connecting unit is disposed at the second end and is implemented to be connected to a system board, and a drive chip is located between the output pad and the connecting unit.

Abstract: In one embodiment, an apparatus includes a microelectronic package comprising a plurality of semiconductor chips connected to a substrate and a stiffener mounted on the substrate. The stiffener is mounted on the substrate with the semiconductor chips disposed within an opening in the stiffener and the opening defines an asymmetric shape relative to the semiconductor chips to control overall warpage in the microelectronic package by the stiffener.

Abstract: A wiring substrate includes a first wiring structure. The first wiring structure has a first insulation layer including a reinforcement material. A first wiring layer is embedded in the first insulation layer. A second wiring structure having a higher wiring density than the first wiring structure is formed on the first insulation layer. The second wiring structure includes at least one second insulation layer and two or more second wiring layers. A lower surface of the first wiring layer is flush with a lower surface of the first insulation layer. The reinforcement material is located toward the second wiring structure from a thickness-wise center of the first insulation layer and laid out at a thickness-wise center of a thickness from the lower surface of the first insulation layer to an upper surface of the uppermost second wiring layer in the second wiring structure.

Abstract: A flow passage member includes a wall formed of ceramics, a space surrounded by the wall being a flow passage through which a fluid flows, a ratio of an area occupied by a grain boundary phase in an inner surface of a wall part of the wall in which wall part heat exchange is conducted being smaller than a ratio of an area occupied by a grain boundary phase in an outer surface of the wall part.

Abstract: The present disclosure provides a display device and a method for assembling the same. The display device includes an electronic device and a flexible printed circuit board. The electronic device includes a lead region and a port located at the lead region, the flexible printed circuit board includes a first portion and a second portion. The first portion is a connector; the second portion includes connecting fingers through which the flexible printed circuit board is connected to the port through the connecting finger. The second portion of the flexible printed circuit board is arranged at a predetermined region, the predetermined region comprises the lead region and an extension region which is arranged outside the lead region and in a same plane where the lead region is located.

Abstract: A method of fabricating an electronic package is provided, including: providing a carrier body having a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since temporary material is required. The present invention further provides the electronic package thus fabricated.

Abstract: OBJECT To improve the strength of a probe guide and improve the abrasion resistance of the probe guide. MEANS FOR SETTLEMENT A guide plate 20 is formed of a silicon plate 22 having guide holes 23 respectively adapted to support contact probes 13, the inner walls of the guide holes 23 include a guide film 25 formed on the inner wall surfaces of corresponding penetration-processed holes 24 of the silicon plate 22, the cross-sectional areas of the penetration-processed holes 24 gradually increase toward a first surface of the silicon plate 22, and the film thickness of the guide film 25 gradually increases toward the first surface of the silicon plate 22. By employing such a configuration, as compared with the tilts of the inner wall surfaces of the penetration-processed holes 24, the tilts of the inner wall surfaces of the guide holes 23 can be suppressed, and the strength of the silicon plate 20 can be improved. Accordingly, the abrasion resistance of a probe guide 100 can be improved.

Abstract: A semiconductor package includes a frame including a through-hole, an electronic component disposed in the through-hole, a redistribution portion disposed below the frame and the electronic component, a metal layer disposed on an inner surface of the frame, and a conductive layer disposed between the metal layer and the electronic component, and covering the frame and the electronic component.

Abstract: A testing jig includes a substrate and a plurality of conductive elastic pieces, wherein the substrate has a recess and a plurality of circuits; the recess is located on a top surface of the substrate, while the circuits are provided on the top surface of the substrate. The conductive elastic pieces are provided on the substrate, and are respectively electrically connected to the circuits. Each of the conductive elastic pieces has a contact portion located within an orthographic projection range of the recess, wherein each of the contact portions contacts a pad of a DUT. Whereby, attenuation happens while transmitting test signals with high frequency can be effectively reduces by using the conductive elastic pieces to transmit test signals.

Abstract: The card connector includes a card connector base and a limiting structure. The card connector base includes a first area and a second area, the limiting structure includes a first limiting part and a second limiting part; the first limiting part is used to limit a first data card in the first area, and the second limiting part is used to limit a second data card or a third data card in the second area; a first spring plate group is disposed in the first area and is configured to electrically connect to edge connectors of the first data card; a second spring plate group and a third spring plate group are disposed in different positions of the second area; the second spring plate group is configured to electrically connect to edge connectors of the second data card; the third spring plate group is configured to electrically connect to edge connectors of the third data card.

Abstract: The present application discloses a light-emitting device including a first support structure having a first surface, a plurality of light-emitting elements arranged on the first surface, and a first adhesive layer arranged on the first support structure. Each light-emitting element has a side wall, a bottom surface, a first electrode pad, and a second electrode pad arranged on the bottom surface. The first adhesive layer surrounds the side wall and does not directly contact the bottom surface. The first support structure includes a plurality of through holes located on positions corresponding to the first electrode pad and the second electrode pad.

Abstract: The solid-state imaging device of the present disclosure includes a signal processing unit including an AD converter that digitizes an analog pixel signal read from each pixel of the pixel array unit to a signal line, the signal processing unit transferring digitized pixel data at a first speed higher than a frame rate; a memory unit that stores the pixel data transferred from the signal processing unit; a data processing unit that reads pixel data at a second speed lower than the first speed from the memory unit; and a control unit that, when the pixel data is read from the memory unit, controls to stop operation of a current source connected with the signal line and operation of at least the AD converter of the signal processing unit.

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract: A display device includes a display panel, a first film-like printed circuit board including a first terminal portion, the first film-like printed circuit board extending from one side of the display panel in a direction away from the display panel, a touch panel provided so as to be opposed to the display panel, and a second film-like printed circuit board including a second terminal portion, the second film-like printed circuit board extending from one side of the touch panel in the direction away from the display panel, the one side of the touch panel corresponding to a side parallel with and adjacent to the one side of the display panel. The first terminal portion and the second terminal portion are provided so that a connecting direction of the first or second terminal portions is different from a connecting direction of the second or first terminal portions.

Abstract: A semiconductor device includes an insulating substrate including a metal plate, an insulating plate, and a circuit plate laminated sequentially in order; a semiconductor element fixed to the circuit plate; a wiring member connected to an electrode provided on a surface of the semiconductor element, the circuit plate, or the electrode and the circuit plate; a plastic housing having a hollow shape to receive the insulating substrate, the semiconductor element, and the wiring member therein, the plastic housing having an inner frame on an inner surface and a step formed in a front end of the inner frame; and a sealing material made of a thermosetting resin to seal the insulating substrate, the semiconductor element, and the wiring member inside the plastic housing.

Abstract: Provided is a liquid discharging apparatus which includes a modulation circuit which generates a modulation signal which is obtained by pulse-modulating a source signal, a transistor which generates an amplified modulation signal by amplifying the modulation signal, a low pass filter which generates a drive signal by smoothening the amplified modulation signal, a piezoelectric element which is displaced by receiving the drive signal, and a circuit substrate on which the transistor is mounted. The transistor includes a first electrode, a second electrode, a third electrode, and a clip which has conductivity, is electrically connected to the first electrode. Furthermore, the circuit substrate has a first land corresponding to the first electrode, a second land corresponding to the second electrode, and a third land corresponding to the third electrode. In addition, a part of the clip is connected to the third land.

Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.

Abstract: A method of fabricating packaging for a product comprises forming a plurality of conductive tracks on a sheet of material and forming a physical barrier, such as a hole, for impeding fluid flow between adjacent conductive tracks. The method may further comprise depositing first and second regions conductive fluid onto adjacent first and second conductive tracks either side of the physical barrier and mounting an electronic device having first and second terminals such that the electronic device forms a bridge over the physical barrier and the first ands second terminals contact the first and second conductive adjacent tracks.

Abstract: A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.

Abstract: When a multilayer ceramic substrate with a cavity is reduced in thickness, a bottom wall portion defining the bottom of the cavity is reduced in thickness, thereby leading to the problem that the bottom wall portion is likely to be broken. A bottom wall portion defining a cavity of a multilayer ceramic substrate has a stack structure formed with a high thermal expansion coefficient layer sandwiched between first and second low thermal expansion coefficient layers. This configuration generates compression stress in the low thermal expansion coefficient layers during a cooling process after firing, thereby allowing the mechanical strength at the bottom wall portion to be improved.

Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Abstract: A packaging method comprises steps of forming a plurality of pads and another circuit pattern on a substrate, forming a second dry film pattern including opening exposing the pad, mounting a solder coating ball in the opening of the second dry film pattern, performing a reflow process on the solder coating ball in order to allow the solder coating ball to have a modified pattern, delaminating the second dry film pattern, and forming a solder pattern including the modified pattern of the solder coating ball in a solder to mount a chip on the substrate using the solder pattern.

Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Abstract: The semiconductor device according to the present invention includes a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead arranged around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Abstract: A sensor arrangement is provided, the sensor arrangement including a chip including a sensor circuit configured to detect a bending of the chip; and a package structure configured to protect the chip; wherein the package structure includes a first region and a second region, and wherein the package structure is configured such that it is easier to be deformed in the first region than in the second region.

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract: A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.

Abstract: The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved.

Abstract: A carrier body for a semiconductor component, in particular for an optoelectronic semiconductor component, is specified. Said carrier body has a connecting layer and a conductor layer, which are connected to one another via main areas facing one another. The connecting layer, the conductor layer or both the connecting layer and the conductor layer has/have at least one thinned region in which the layer thickness of said layer(s) is less than the maximum layer thickness of said layer(s). The connecting layer is either completely electrically conductive and electrically insulated at least from parts of the conductor layer or it is electrically insulating at least in parts. Furthermore, a semiconductor component comprising the electrical connection conductor and also a method for producing the carrier body are specified.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.

Abstract: In an electronic component mounting structure, a semiconductor element (an electronic component) provided with an electrode pad and a board provide with an electrode pad corresponding to the electrode pad are connected via a conductive material portion. On a surface of the board, there is formed solder resist having an opening regulating an area of the electrode pad. The conductive material portion is formed to protrude from a surface of the solder resist. An elastic coefficient of the conductive material portion is lower than that of the solder resist. A solder bump and the conductive material portion are connected via a metal layer. The conductive material portion is formed to have an area larger than that of the opening of the solder resist. An edge of the conductive material portion is adhered to a portion of the surface of the solder resist. Thus, in a case of mounting an electronic component on a board by flip-chip connection, a reliability of connection can be secured.

Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Abstract: This method for producing a non-plane comprises fitting a flexible component onto a carrier by means of hybridization columns, each column having a first height and including a volume of solder material formed between two surfaces wettable by said solder material added to the flexible component and to the carrier respectively, said wettable surfaces being surrounded by zones non-wettable by the solder material, the wettable surfaces and the volume of solder material being determined as a function of a second height required for the flexible component relative to the carrier at the place where the column is formed, such that the column varies from the first height to the second height when the volume of material is brought to a temperature higher than or equal to its melting point and heating the volumes of solder material of the columns to a temperature higher than or equal to the melting point of said material in order to melt it.

Abstract: A semiconductor substrate having a first lateral dimension is combined with a flexible film piece having a second lateral dimension by arranging the semiconductor substrate in a recess of the film piece. The semiconductor substrate has circuit structures produced using lithography process steps. After the semiconductor substrate has been arranged in the recess of the film piece, a patterned layer of an electrically conductive material is produced above the semiconductor substrate and the film piece using lithography process steps. The patterned layer extends from the semiconductor substrate up to the flexible film piece and forms a number of electrically conductive contact tracks between the semiconductor substrate and the film piece.

Abstract: The semiconductor device according to the present invention includes a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead arranged around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package collectively sealing the semiconductor chip, the island, the lead and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Abstract: A method of manufacture of a semiconductor packaging system includes: providing a base substrate having edges; mounting an electrical interconnect on the base substrate; and applying an encapsulant having a reference marker and an opening over the electrical interconnect, the reference marker around the electrical interconnect based on physical locations of the edges.

Abstract: The present disclosure relates to a method of fabricating a micromachined CMOS-MEMS integrated device as well as the devices/apparatus resulting from the method. In the disclosed method, the anisotropic etching (e.g., DRIE) for isolation trench formation on a MEMS element is performed on the back side of a silicon wafer, thereby avoiding the trench sidewall contamination and the screen effect of the isolation beams in a plasma etching process. In an embodiment, a layered wafer including a substrate and a composite thin film thereon is subjected to at least one (optionally at least two) back side anisotropic etching step to form an isolation trench (and optionally a substrate membrane). The method overcomes drawbacks of other microfabrication processes, including isolation trench sidewall contamination.

Abstract: A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals.

Abstract: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention is that the integrated circuit products are produced a batch at a time, and that singulation of the batch into individualized integrated circuit products uses a non-linear (e.g., non-rectangular or curvilinear) sawing or cutting action so that the resulting individualized integrated circuit packages no longer need to be completely rectangular. Another aspect of the invention is that the integrated circuit products can be produced with semiconductor assembly processing such that the need to provide an external package or container becomes optional.

Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed.

Abstract: Embodiments of the present invention provide electrical bussing for multichip leadframes. In various embodiments, a leadframe may comprise a first die paddle for receiving a first microelectronic device, a second die paddle for receiving a second microelectronic device, and at least one electrical bus disposed between the first die paddle and the second die paddle.