Internal Lead Connections, E.g., Via Connections, Feedthrough Structures (epo) Patents (Class 257/E23.011)
  • Patent number: 10734430
    Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yi Koan Hong, Taeseong Kim
  • Patent number: 10530329
    Abstract: A micro-electrical-mechanical system (MEMS) guided wave device includes a plurality of electrodes arranged below a piezoelectric layer (e.g., either embedded in a slow wave propagation layer or supported by a suspended portion of the piezoelectric layer) and configured for transduction of a lateral acoustic wave in the piezoelectric layer. The piezoelectric layer permits one or more additions or modifications to be made thereto, such as trimming (thinning) of selective areas, addition of loading materials, sandwiching of piezoelectric layer regions between electrodes to yield capacitive elements or non-linear elastic convolvers, addition of sensing materials, and addition of functional layers providing mixed domain signal processing utility.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 7, 2020
    Assignee: Qorvo US, Inc.
    Inventor: Kushal Bhattacharjee
  • Patent number: 10389332
    Abstract: A micro-electrical-mechanical system (MEMS) guided wave device includes a single crystal piezoelectric layer and at least one guided wave confinement structure configured to confine a laterally excited wave in the single crystal piezoelectric layer. A bonded interface is provided between the single crystal piezoelectric layer and at least one underlying layer. A multi-frequency device includes first and second groups of electrodes arranged on or in different thickness regions of a single crystal piezoelectric layer, with at least one guided wave confinement structure. Segments of a segmented piezoelectric layer and a segmented layer of electrodes are substantially registered in a device including at least one guided wave confinement structure.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 20, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Kushal Bhattacharjee
  • Patent number: 10374573
    Abstract: A micro-electrical-mechanical system (MEMS) guided wave device includes a single crystal piezoelectric layer and at least one guided wave confinement structure configured to confine a laterally excited wave in the single crystal piezoelectric layer. A bonded interface is provided between the single crystal piezoelectric layer and at least one underlying layer. A multi-frequency device includes first and second groups of electrodes arranged on or in different thickness regions of a single crystal piezoelectric layer, with at least one guided wave confinement structure. Segments of a segmented piezoelectric layer and a segmented layer of electrodes are substantially registered in a device including at least one guided wave confinement structure.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 6, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Kushal Bhattacharjee
  • Patent number: 10348269
    Abstract: A micro-electrical-mechanical system (MEMS) guided wave device includes a piezoelectric layer including multiple thinned regions of different thicknesses each bounding in part a different recess, different groups of electrodes on or adjacent to different thinned regions and arranged for transduction of lateral acoustic waves of different wavelengths in the different thinned regions, and at least one bonded interface between the piezoelectric layer and a substrate. Optionally, a buffer layer may be intermediately bonded between the piezoelectric layer and the substrate. Methods of producing such devices include locally thinning a piezoelectric layer to define multiple recesses, bonding the piezoelectric layer on or over a substrate layer to cause the recesses to be bounded in part by either the substrate or an optional buffer layer, and defining multiple groups of electrodes on or over the different thinned regions.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: July 9, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Kushal Bhattacharjee
  • Patent number: 10304765
    Abstract: A semiconductor device package includes a substrate, a first insulation layer, a support film and an interconnection structure. The substrate has a first sidewall, a first surface and a second surface opposite to the first surface. The first insulation layer is on the first surface of the substrate and has a second sidewall. The first insulation layer has a first surface and a second surface adjacent to the substrate and opposite to the first surface of the first insulation layer. The support film is on the second surface of the substrate and has a third sidewall. The support film has a first surface adjacent to the substrate and a second surface opposite to the first surface of the support film. The interconnection structure extends from the first surface of the first insulation layer to the second surface of the support film via the first insulation layer and the support film. The interconnection structure covers the first, second and third sidewalls.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 28, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Ming-Hung Chen, Hsu-Chiang Shih
  • Patent number: 10269746
    Abstract: Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Wei Kuo, Hsiao-Tsung Yen, Min-Chie Jeng, Yu-Ling Lin
  • Patent number: 10236239
    Abstract: An apparatus includes a multilayer package substrate having a plurality of layers. The apparatus also includes a first heat sink disposed over the package substrate. The first heat sink is configured to connect to a semiconductor device and to provide an electrical ground for the semiconductor device. The apparatus includes a second heat sink disposed in the package substrate. The first heat sink overlaps substantially all of the first electrically conductive layer and no dielectric material exists in the multilayer package substrate in a region of contact of the first heat sink and the first electrically conductive layer.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: March 19, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Nathan Perkins
  • Patent number: 10201090
    Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Ying-Chou Tsai
  • Patent number: 10157829
    Abstract: A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen
  • Patent number: 10090247
    Abstract: A method for forming a conductive structure for a semiconductor device includes depositing a barrier layer in a trench formed in a dielectric material and forming an interface layer over the barrier layer. A main conductor is formed over the interface layer, and the main conductor is recessed selectively to the interface layer and the barrier layer to a position below a top surface of the dielectric layer. The interface layer is selectively wet etched to the main conductor and the barrier layer using a chemical composition having an oxidizer, wherein the chemical composition is buffered to include a pH above 7. The barrier layer is selectively etching to the main conductor and the interface layer.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Cornelius B. Peethala, David L. Rath
  • Patent number: 9735134
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via substantially penetrating through the molding material, wherein the through-via has an end. The end of the through-via is tapered and has rounded sidewall surfaces. The package further includes a redistribution line electrically coupled to the through-via.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 9601474
    Abstract: A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: March 21, 2017
    Assignee: Invensas Corporation
    Inventors: Shou-Lung Chen, Ching-Wen Hsaio, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
  • Patent number: 9591747
    Abstract: To provide a module board capable of suppressing depression of a top face of insulating resin near the center of a substrate by arranging multiple columnar connection terminals not only on a peripheral area of the substrate but also between multiple electronic components that are mounted. Multiple electronic components 4 and 4h are mounted on one face of a substrate 5 and the multiple electronic components 4 and 4h are sealed with insulating resin 3. Multiple columnar connection terminals 2 and 7 are arranged on a peripheral area of the substrate 5 and in one or more small areas 8 on the substrate 5, respectively. The one or more small areas 8 are set at positions on the substrate 5, which is not on the peripheral area of the substrate 5 and on which the multiple electronic components 4 and 4h are not mounted.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 7, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masaaki Mizushiro
  • Patent number: 9383401
    Abstract: There is provided with an electronic device including: a main board, a plurality of electronic substrates, a first chain, a measuring unit and a controller, in which the plurality of electronic substrates each are mounted on the main board via solder joints, the first chain connects the solder joints in series throughout all of the electronic substrates, comprising a plurality of second chains each being a part of the first chain and connecting the solder joints in each corresponding one of the electronic substrates, the measuring unit measures an electrical resistance of the first chain and electrical resistances of the second chains, and the controller detects, if the electrical resistance of the first chain is equal to or higher than a first threshold value, the second chain having an electrical resistance equal to or higher than a corresponding second threshold value from among the second chains.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: July 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takahiro Omori, Kenji Hirohata
  • Patent number: 9287440
    Abstract: A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang
  • Patent number: 9040986
    Abstract: A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Fang Chen, Hsiang-Tai Lu, Chih-Hsien Lin
  • Patent number: 9040346
    Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Edward Fuergut
  • Patent number: 9040414
    Abstract: A semiconductor device and methods directed toward preventing a leakage current between a contact plug and a line adjacent to the contact plug, and minimizing capacitance between adjacent lines.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 26, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young Jin Lee
  • Patent number: 9041185
    Abstract: A semiconductor device includes a substrate, a first land formed in a first surface of the substrate, a second land formed in a second surface of the substrate, a first terminal coupled to the second land, a line coupled to the first land and the second land, a second terminal formed in the second surface of the substrate and a branch line coupled to the line and the second terminal. The second terminal is coupled to the first land and the second land and is not coupled to other lands in the first surface. The second surface is different surface from the first surface.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: May 26, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Naoto Akiyama, Toshiaki Umeshima
  • Patent number: 9041210
    Abstract: A through silicon via with sidewall roughness and methods of manufacturing the same are disclosed. The method includes forming a via in a substrate and roughening a sidewall of the via by depositing material within the via. The method further includes removing a backside of the substrate to form a through via with a roughened sidewall structure.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Jessica A. Levy, Cameron E. Luce, Daniel S. Vanslette, Bucknell C. Webb
  • Patent number: 9034769
    Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Bossler, Jaspreet S. Gandhi, Christopher J. Gambee, Randall S. Parker
  • Patent number: 9035450
    Abstract: A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface. The interconnect region has a core substrate, interconnect layers formed on both surfaces thereof, plural first through holes and plural first vias that pass through the interconnect layer on the side of the first main surface for forming impedance matching capacitances. Each first through hole is connected to a first signal interconnect at a position spaced part from the first signal electrode by a first interconnect length and each first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Ryuichi Oikawa
  • Patent number: 9035472
    Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takaharu Nagasawa
  • Patent number: 9029903
    Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 9030024
    Abstract: Disclosed is a semiconductor device with through-silicon vias (TSVs) that comprises a primary TSV group, a plurality of signal lines connected to the primary TSV group, a redundant TSV group and connection circuitry responsive to a control signal having a predetermined value to electrically connect the signal lines to the redundant TSV group.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: May 12, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 9024391
    Abstract: A semiconductor structure includes a substrate, a shallow trench isolation (STI) structure embedded in the substrate, a stressor embedded in the substrate, and a conductive plug over and electrically coupled with the stressor. A same-material region is sandwiched by the STI structure and an entire sidewall of the stressor, and the same-material region is a continuous portion of the substrate.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mei-Hsuan Lin, Chih-Hsun Lin, Chih-Kang Chao, Ling-Sung Wang
  • Patent number: 9024422
    Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: May 5, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Shih-Ping Hsu, I-Ta Tsai
  • Patent number: 9024448
    Abstract: A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Gwon Jang, Young-Lyong Kim, Ae-Nee Jang
  • Patent number: 9018741
    Abstract: A semiconductor package is presented which has a suitable structure for effectively shielding electromagnetic wave interference (EMI) in a cavity area to which a semiconductor chip is attached. The semiconductor package is assembled such that a lower substrate to which the semiconductor chip is attached is adhered to an EMI shielding & electric I/O body having various types of EMI shielding & electric I/O metal patterns by soldering. Further, the EMI shielding & electric I/O body is adhered to an upper substrate by soldering thereby simplifying assembling of the semiconductor package.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: April 28, 2015
    Inventors: Dong In Kim, Jae Ung Lee, Eunnara Cho, Min Ju Kim
  • Patent number: 9006100
    Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook Kye, Rod Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 9006102
    Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte Ltd
    Inventors: Yu Hong, Liu Huang, Zhao Feng
  • Patent number: 9000573
    Abstract: A package on package structure includes a connection substrate having a main body and electrically conductive posts, the main body includes a first surface and an opposite second surface, and each electrically conductive post passes through the first and second surfaces, and each end of the two ends of the electrically conductive post protrudes from the main body; a first package device arranged on a side of the first surface of the connection substrate; a package adhesive arranged on a side of the second surface of the connection substrate; and a second package device arranged on a side of the package adhesive furthest away from the first package device.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: April 7, 2015
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventors: Chien-Chih Chen, Hong-Xia Shi, Shih-Ping Hsu
  • Patent number: 8994182
    Abstract: The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from a second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers, and a second metallization layer on the second surface of the substrate and within the via. A portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers. The semiconductor die further includes a dielectric solder barrier on the second metallization layer. Preferably, the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 31, 2015
    Assignee: Cree, Inc.
    Inventors: Helmut Hagleitner, Fabian Radulescu
  • Patent number: 8994176
    Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Hsien-Wei Chen, Yu-Feng Chen, Chun-Hung Lin, Ming-Kai Liu, Chun-Lin Lu
  • Patent number: 8994181
    Abstract: Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
  • Patent number: 8987869
    Abstract: An integrated circuit device including an interlayer insulating layer on a substrate, a wire layer on the interlayer insulating layer, and a through-silicon-via (TSV) contact pattern having an end contacting the wire layer and integrally extending from inside of a via hole formed through the interlayer insulating layer and the substrate to outside of the via hole.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-gi Jin, Jeong-woo Park, Ju-il Choi
  • Patent number: 8987914
    Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Yi-Hsuan Hsiao, Chih-Ping Chen
  • Patent number: 8987884
    Abstract: A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8987921
    Abstract: A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 24, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ulrike Scholz, Ralf Reichenbach
  • Patent number: 8987916
    Abstract: A method for increasing metal density around selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and increasing area of a metal layer which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Douglas M. Reber
  • Patent number: 8981568
    Abstract: A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: March 17, 2015
    Assignee: HSIO Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8981562
    Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen
  • Patent number: 8981532
    Abstract: In a semiconductor device, the thickness of an insulating film formed in a through hole is reduced, while an annular groove having an insulating material embedded therein is provided so as to ensure a sufficient total thickness of the insulator, whereby a through silicon via is provided with an insulating ring which is improved in both processability and functionality.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: March 17, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Koji Torii
  • Patent number: 8975753
    Abstract: A three-dimensional interconnect includes a first substrate bonded to a second substrate, the first substrate including a device layer and a bulk semiconductor layer, a metal pad disposed on the second substrate, an electrically insulating layer disposed between the first and second substrates. The structure has a via-hole extending through the device layer, the bulk semiconductor layer and the electrically insulating layer to the metal pad on the second substrate. The structure has a dielectric coating on a sidewall of the via-hole, and a plasma-treated region of the metal pad disposed on the second substrate. The structure includes a via metal monolithically extending from the plasma-treated region of the metal pad through the via-hole and electrically interconnecting the device layer of the first substrate to the metal pad of the second substrate.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 10, 2015
    Assignee: Research Triangle Institute
    Inventors: Charles Kenneth Williams, Christopher A. Bower, Dean Michael Malta, Dorota Temple
  • Patent number: 8975729
    Abstract: A semiconductor wafer has an integrated through substrate via (TSV). The semiconductor wafer includes a substrate. A dielectric layer may be formed on a first side of the substrate. A through substrate via may extend through the dielectric layer and the substrate. The through substrate via may include a conductive material and an isolation layer. The isolation layer may at least partially surround the conductive material. The isolation layer may have a tapered portion.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Vidhya Ramachandran, Shiqun Gu
  • Patent number: 8975751
    Abstract: A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: March 10, 2015
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Cyprian Uzoh, Piyush Savalia
  • Patent number: 8970044
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 3, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: A Leam Choi, DongSam Park, YongDuk Lee
  • Patent number: 8970048
    Abstract: A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Inohara
  • Patent number: 8970027
    Abstract: One aspect of the present invention is a method of processing a substrate. In one embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electroless deposition solution and electrolessly depositing a metal matrix and co-depositing the metal particles. In another embodiment, the method comprises forming an electrical conductor on or in the substrate by providing a mixture comprising metal particles and an electrochemical plating solution and electrochemically plating a metal matrix and co-depositing the metal particles. Another aspect of the present invention is a mixture for the formation of an electrical conductor on or in a substrate. Another aspect of the present invention is an electronic device.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Fritz Redeker