Abstract: Implementations of encapsulated nanowires are disclosed.

Abstract: A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with impurities may include a combination of a pure nickel layer and a nickel layer with impurities.

Abstract: A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Abstract: A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined. The area that the connection region of the line and the bump is projected on the plane is larger than 30,000 square microns or has an extension distance larger than 500 microns.

Abstract: The present teachings provides a semiconductor device which has a semiconductor substrate, and a lower electrode including a first layer in contact with a lower surface of the semiconductor substrate, a second layer in contact with a lower surface of the first layer, and a third layer stacked at a position farther from the semiconductor substrate than the second layer, wherein the first layer is an aluminum layer containing silicon, the second layer is a layer including silicon as a primary component, and the third layer is a solder joint layer.

Abstract: A semiconductor structure including a bonding layer connecting a first semiconductor wafer layer to a second semiconductor wafer layer, the bonding layer including an electrically conductive carbonaceous component and a binder component.

Abstract: An integrated circuit includes a substrate; a sealing element spanning a periphery of the substrate that forms a protective boundary for the substrate; a plurality of copper lines spanning the substrate in at least two distinct layers contained within the protective boundary; a first conducting element disposed outside the sealing element; and one or more second conducting elements connecting at least two of the copper lines and that spans the sealing element; wherein the conducting elements are substantially non-oxidizing metals that are resistant to oxidization and that connect the copper line to the first conducting element.

Abstract: Disclosed is a substrate with a transparent conductive film, wherein an underlying layer and a transparent conductive film are arranged in this order on a transparent insulating substrate. The transparent conductive film-side surface of the underlying layer is provided with a pyramid-shaped or inverse pyramid-shaped irregular structures, and the transparent conductive film comprises a first transparent electrode layer which is formed on the underlying layer and a second transparent electrode layer which forms the outermost surface of the transparent conductive film. By forming a zinc oxide layer that serves as the second transparent electrode layer by a reduced pressure CVD method, a substrate with a transparent conductive film that is provided with an irregular structure smaller than that of the underlying layer can be obtained. The substrate with a transparent conductive film can improve the conversion efficiency of a photoelectric conversion device through an increased light trapping effect.

Abstract: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes on a wafer; a step of providing a resin later as a stress relieving layer on the wafer, avoiding the electrodes; a step of forming a chromium layer as wiring from electrodes over the resin layer; and step of forming solder balls as external electrodes on the chromium layer over the resin layer; and a step of cutting the wafer into individual semiconductor chips; in the steps of forming the chromium layer and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract: An object of the present invention is to provide, at low costs, an environmental friendly bonding material for a semiconductor, having sustained bonding reliability even when used at a temperature as high as 200° C. or higher for a long period of time, the semiconductor device having a semiconductor element, a supporting electrode body bonded to a first face of the semiconductor element via a first bonding member, and a lead electrode body bonded to a second face of the semiconductor element supported by the supporting electrode body via a second bonding member, the semiconductor device having a Ni-based plating layer and an intermetallic compound layer containing at least one of Cu6Sn5 and (Cu,Ni)6Sn5 compounds at an interface between the supporting electrode body and the first bonding member, and having a Ni-based plating layer and an intermetallic compound layer containing at least one of Cu6Sn5 and (Cu,Ni)6Sn5 compounds at an interface between the lead electrode body and the second bonding member.

Abstract: A semiconductor device includes a through electrode penetrating a semiconductor substrate, a conductor pad formed on the through electrode and made of a conductor electrically connected to the through electrode, and an interconnection layer formed on a surface of the semiconductor substrate and electrically connected to the conductor pad.

Abstract: A method for mounting a semiconductor device onto a composite substrate, including a submount and a heat sink, is described. According to one aspect of the invention, the materials for the submount and the heat sink are chosen so that the value of coefficient of thermal expansion of the semiconductor device is in between the values of coefficients of thermal expansion of the materials of the submount and the heat sink, the thickness of the submount being chosen so as to equalize thermal expansion of the semiconductor device to that of the surface of the submount the device is mounted on. According to another aspect of the invention, the semiconductor device, the submount, and the heat sink are soldered into a stack at a single step of heating, which facilitates reduction of residual post-soldering stresses.

Abstract: A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad.

Abstract: The present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend interposing an adhesive sheet therebetween, a wire-bonding step of bonding wires to the semiconductor element, and a step of sealing the semiconductor element with a sealing resin, and in which the loss elastic modulus of the adhesive sheet at 175° C. is 2000 Pa or more.

Abstract: A method of manufacturing a semiconductor device having a transition layer, including (a) forming a wiring and a die pad on a wafer, (b) forming a thin film layer on an entire surface of the wafer obtained in the step (a), (c) forming a resist layer on the thin film layer, and forming a thickening layer on a resist layer unformed section, (d) peeling the resist layer, (e) removing the thin film layer by etching, and (f) dividing the wafer to thereby form semiconductor devices.

Abstract: A method and device of nanostructured titania that is crack free. A method in accordance with the present invention comprises depositing a Ti film on a surface, depositing a masking layer on the Ti film, etching said masking layer to expose a limited region of the Ti film, the limited region being of an area less than a threshold area, oxidizing the exposed limited region of the Th.ucsbi film, and annealing the exposed limited region of the Ti film.

Abstract: A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array.

Abstract: A semiconductor apparatus having improved thermal fatigue life is provided by lowering maximum temperature on jointing members and reducing temperature change. A jointing member is placed between a semiconductor chip and a lead electrode, and a thermal stress relaxation body is arranged between the chip and a support electrode. Jointing members are placed between the thermal stress relaxation body and the chip and between the thermal stress relaxation body and the support electrode. A second thermal stress relaxation body made from a material having a thermal expansion coefficient between the coefficients of the chip and the lead electrode is located between the chip and the lead electrode. The first thermal stress relaxation body is made from a material which has a thermal expansion coefficient in between the coefficients of the chip and the support electrode, and has a thermal conductivity of 50 to 300 W/(m·° C.).

Abstract: In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed.

Abstract: A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with impurities may include a combination of a pure nickel layer and a nickel layer with impurities.

Abstract: A photodiode balanced in increased sensitivity and speed. The photodiode includes a semiconductor substrate, an active region formed on the semiconductor substrate, and a comb electrode connected to the active region. The comb electrode includes a plurality of electrode fingers, and each of the electrode fingers includes a transparent electrode contacting the active region, and an opaque electrode formed on the transparent electrode. Here, the width of the opaque electrode is set smaller than the width of the transparent electrode.

Abstract: A method for manufacturing a silicon chip package for a circuit board assembly provides a package with a silicon chip and an array of first contact pads that are provided by a first conductive material. A plurality of second contact pads are provided from a gold material having a hardness different than that of the first contact pads. The second contact pads are soldered to the first contact pads of the package. A circuit board assembly is assembled by providing a circuit board substrate with at least one socket with contact pads. The second contact pads of the package are assembled to the circuit board substrate contact pads.

Abstract: A method of optimally filling a through via within a through wafer via structure with a conductive metal such as, for example, W is provided. The inventive method includes providing a structure including a substrate having at least one aperture at least partially formed through the substrate. The at least one aperture of the structure has an aspect ratio of at least 20:1 or greater. Next, a refractory metal-containing liner such as, for example, Ti/TiN, is formed on bare sidewalls of the substrate within the at least one aperture. A conductive metal seed layer is then formed on the refractory metal-containing liner. In the invention, the conductive metal seed layer formed is enriched with silicon and has a grain size of about 5 nm or less. Next, a conductive metal nucleation layer is formed on the conductive metal seed layer. The conductive metal nucleation layer is also enriched with silicon and has a grain size of about 20 nm or greater.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface.

Abstract: The conductive line structure of a semiconductor device including a base; at least one patterned conductive layer formed over the base; a conductive line formed over the at least one patterned conductive layer; a protection layer that encompasses the top surface and sidewall of the conductive line to prevent undercut generated by etching. The structure further comprises an underlying layer under the conductive line. The underlying layer includes Ni, Cu or Pt. The conductive line includes gold or copper. The at least one patterned conductive layer includes at least Ti/Cu. The protection layer includes electro-less plating Sn, Au, Ag or Ni.

Abstract: Provided is a semiconductor package, and in particular a semiconductor package which is capable of electrically connecting to the outside without a lead.

Abstract: The invention provides a method for forming a metal silicide layer. The method comprises steps of providing a substrate and forming a nickel-noble metal layer over the substrate. A grain boundary sealing layer is formed on the nickel-noble metal layer and then an oxygen diffusion barrier layer is formed on the grain boundary sealing layer. Thereafter, a rapid thermal process is performed to transform a portion of the nickel-noble metal layer into a metal silicide layer. Finally, the oxygen diffusion barrier layer, the grain boundary sealing layer and the rest portion of the nickel-noble metal layer are removed.

Abstract: A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride layer, and a gold thin film formed on the tantalum layer.

Abstract: A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.

Abstract: Embodiments relate to a semiconductor device. In embodiments, the semiconductor device may include a semiconductor substrate having a first metal line; a pre-metal dielectric (PMD) layer over the first metal line on the semiconductor substrate; a first metal layer formed in a first contact hole in the PMD layer; a second metal layer formed in a second contact hole in the PMD layer; and a second metal line electrically connected to the first and second metal layers, respectively, over the PMD layer, wherein the first and second metal layers are located at prescribed positions and configured to be electrically connected to the first metal line.

Abstract: An under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure are provided. The under bump metallurgy structure includes an adhesion layer, a barrier layer and a wetting layer. The adhesion layer is disposed on a bonding pad of a wafer. The barrier layer is disposed on the adhesion layer. The wetting layer is disposed on the barrier layer. The adhesion layer, the barrier layer and the wetting layer are respectively made of nickel with boron, cobalt and gold.

Abstract: A method of producing a leadframe is provided, the method including the steps of providing a substrate, plating the substrate with a layer of tin, plating a layer of nickel over the layer of tin, and thereafter plating one or more protective layers over the layer of nickel. The leadframe may thereafter be heated to produce one or more intermetallic layers comprising tin, which impedes the out-diffusion of copper from a base material of the leadframe to the surface thereof.

Abstract: An adhesive film for semiconductor use of the present invention is used in a method in which, after the adhesive film for semiconductor use is laminated to one side of a metal sheet, the metal sheet is processed to give a wiring circuit, a semiconductor die is mounted and molded, and the adhesive film is then peeled off. The adhesive film includes a resin layer A formed on one side or both sides of a support film, the 90 degree peel strength between the resin layer A and the metal sheet prior to the processing of the metal sheet laminated with the adhesive film for semiconductor use to give the wiring circuit is 20 N/m or greater at 25° C., and the 90 degree peel strengths, after molding with a molding compound the wiring circuit laminated with the adhesive film for semiconductor use, between the resin layer A and the wiring circuit and between the resin layer A and the molding compound are both 1000 N/m or less at at least one point in the temperature range of 0° C. to 250° C.

Abstract: The present invention is a semiconductor device characterized by including a substrate, an insulating film consisting of a fluorine added carbon film formed on the substrate, a barrier layer consisting of a silicon nitride film and a film containing silicon, carbon, and nitride formed on the insulating film, and a hard mask layer having a film containing silicon and oxygen formed on the barrier layer, wherein the barrier layer consists of a silicon nitride film and a film containing silicon, carbon, and nitride that are laminated from the bottom in that order, and functions to prevent the fluorine in the fluorine added carbon film from moving to the hard mask layer.

Abstract: In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.

Abstract: A semiconductor device with a number of contact pads for the electrical contacting of the semiconductor device is disclosed. A padding layer, which is manufactured of a hard material, is provided at least partially below an upper layer of the contact pads.

Abstract: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.

Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.

Abstract: A semiconductor package which includes a conductive can, a semiconductor die received in the interior of the can and connected to an interior portion thereof at one of its sides, at least one interconnect structure formed on the other side of the semiconductor die, and a passivation layer disposed on the other side of the semiconductor die around the interconnect structure and extending at least to the can.

Abstract: A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.