Consisting Of Lead-in Layers Inseparably Applied To Semiconductor Body (epo) Patents (Class 257/E23.012)
  • Patent number: 9034756
    Abstract: A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Jung Tsai, Hsiang-Huan Lee, Ming Han Lee
  • Patent number: 9029903
    Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 9018750
    Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Flipchip International, LLC
    Inventors: Robert Forcier, Douglas Scott
  • Patent number: 9018742
    Abstract: An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Joachim Mahler
  • Patent number: 8952528
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: February 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Feng Chan, Chun-Tang Lin, Yi Che Lai
  • Patent number: 8723323
    Abstract: A method for fabricating an electronic device package having a column grid array is disclosed. A column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate. The column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: May 13, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Thomas J. McIntyre, Keith K. Sturcken, Christy A. Hagerty
  • Publication number: 20140117534
    Abstract: A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company. Ltd.
  • Patent number: 8709933
    Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8686562
    Abstract: According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: April 1, 2014
    Assignee: International Rectifier Corporation
    Inventor: Sadiki Jordan
  • Patent number: 8669652
    Abstract: To provide an inexpensive lead component which can be easily connected to a semiconductor chip and which has satisfactory connectability. There is provided a lead component including a base material having a connection part for connecting to a semiconductor chip, comprising: a solder part having a Zn layer made of a Zn-bonding material rolled and clad-bonded on the base material, and an Al layer made of an Al-bonding material rolled and clad-bonded on the Zn layer, in a prescribed region including the connection part on the base material; and the solder part further comprising a metal thin film composed of one kind or two kinds or more of Au, Ag, Cu, Ni, Pd, and Pt covering a surface of the Al layer.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 11, 2014
    Assignee: Hitachi Cable, Ltd.
    Inventors: Shohei Hata, Yuichi Oda, Kazuma Kuroki, Hiromitsu Kuroda
  • Publication number: 20140001471
    Abstract: A conformal shielding module comprising a substrate, at least one electronic component mounted on the substrate, and a molding compound covering the electronic component. The molding compound includes a vertical channel extending from a surface of the molding component to the electronic component, and an electrically conductive structure formed inside the vertical channel. The electrically conductive structure is electrically connected to the electronic component and includes a testing contact on the surface of the molding compound for in-circuit test of the electronic component.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicants: UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD., UNIVERSAL SCIENTIFIC INDUSTRIAL CO., LTD.
    Inventor: Kuan-Hsing LI
  • Patent number: 8604601
    Abstract: A semiconductor device of the invention includes a first wiring layer including a signal wiring line formed therein, and a second wiring layer stacked on the first wiring layer and including a power-supply plane and/or ground plane formed therein, the power-supply plane or the ground plane is not formed at least within a part of the region of the second wiring layer facing the signal wiring line of the first wiring layer.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: December 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Satoshi Isa, Mitsuaki Katagiri
  • Patent number: 8571229
    Abstract: A semiconductor device includes at least a die carried by a substrate, a plurality of bond pads disposed on the die, a plurality of conductive components, and a plurality of bond wires respectively connected between the plurality of bond pads and the plurality of conductive components. The plurality of bond pads respectively correspond to a plurality of signals, and include a first bond pad configured for transmitting/receiving a first signal and a second bond pad configured for transmitting/receiving a second signal. The plurality of conductive components include a first conductive component and a second conductive component. The first conductive component is bond-wired to the first bond pad, and the second conductive component is bond-wired to the second bond pad. The first conductive component and the second conductive component are separated by at least a third conductive component of the plurality of conductive components, and the first signal is asserted when the second signal is asserted.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: October 29, 2013
    Assignee: Mediatek Inc.
    Inventors: Chien-Sheng Chao, Tse-Chi Lin, Yin-Chao Huang
  • Publication number: 20130270704
    Abstract: A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou
  • Patent number: 8552560
    Abstract: Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 8, 2013
    Assignee: LSI Corporation
    Inventors: Hemanshu Bhatt, Dilip Vijay, Jayanthi Pallinti, Sey-Shing Sun, Hong Ying, Chiyi Kao
  • Patent number: 8546947
    Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 1, 2013
    Assignee: Megica Corporation
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
  • Publication number: 20130234330
    Abstract: In one embodiment, a method of forming a semiconductor package includes applying a film layer having through openings over a carrier and attaching a back side of a semiconductor chip to the film layer. The semiconductor chip has contacts on a front side. The method includes using a first common deposition and patterning step to form a conductive material within the openings. The conductive material contacts the contacts of the semiconductor chip. A reconfigured wafer is formed by encapsulating the semiconductor chip, the film layer, and the conductive material in an encapsulant using a second common deposition and patterning step. The reconfigured wafer is singulated to form a plurality of packages.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: Infineon Technologies AG
    Inventor: Horst Theuss
  • Patent number: 8487322
    Abstract: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding. A method for producing such a luminous body is also disclosed.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: July 16, 2013
    Assignee: Bayer Intellectual Property GmbH
    Inventors: Andrea Maier-Richter, Eckard Foltin, Michael Roppel, Peter Schibli
  • Patent number: 8471271
    Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: June 25, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 8441128
    Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: May 14, 2013
    Assignee: Infineon Technologies AG
    Inventor: Daniel Domes
  • Publication number: 20130075908
    Abstract: An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cyril Cabral, JR., Geraud Jean-Michel Dubois, Daniel C. Edelstein, Takeshi Nogami, Daniel P. Sanders
  • Publication number: 20130075909
    Abstract: A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 28, 2013
    Inventors: Jae-hwa PARK, Man-sug KANG, Hee-sook PARK, Woong-hee SOHN
  • Patent number: 8390117
    Abstract: A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode 9 is formed in a region outside of an element mounting region of a substrate 5. The projected electrode 9 includes a protruding portion that protrudes from the front face of a molding resin portion 10. The distal end of the protruding portion is a flat face 13. In addition, a portion of the projected electrode 9 whose cross section is larger than the protruding portion is positioned inside the molding resin portion 10.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: March 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshiaki Shimizu, Yuichiro Yamada, Toshiyuki Fukuda
  • Publication number: 20130043582
    Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: TESSERA, INC.
    Inventors: Belgacem Haba, Wael Zohni, Richard Dewitt Crisp
  • Publication number: 20130043603
    Abstract: The present invention relates to a method for forming a raised conductive image on a non-conductive or dielectric surface, the method comprising placing a metal coordination complex on a surface of the substrate, exposing the surface to electromagnetic radiation, reducing the exposed complex. removing unexposed complex leaving an elemental metal image, removing unexposed metal complex and then plating the resulting elemental metal image with a highly conductive material.
    Type: Application
    Filed: February 23, 2012
    Publication date: February 21, 2013
    Inventor: William Wismann
  • Patent number: 8378500
    Abstract: A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: February 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Don Choi
  • Publication number: 20130015584
    Abstract: An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.
    Type: Application
    Filed: September 24, 2012
    Publication date: January 17, 2013
    Applicant: EPISTAR CORPORATION
    Inventor: EPISTAR CORPORATION
  • Publication number: 20120319279
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, wiring lines formed above the semiconductor substrate, and an air gap formed between the adjacent wiring lines. In the semiconductor device, top surfaces and side walls of the wiring lines are covered with the diffusion prevention film, and the air gap is in contact with the interconnects via a diffusion prevention film.
    Type: Application
    Filed: January 31, 2012
    Publication date: December 20, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Atsunobu ISOBAYASHI
  • Publication number: 20120319277
    Abstract: Disclosed is a thin film transistor panel, comprising a substrate, an insulation layer and transparent conducting material. The insulation layer comprises projections at the back side not facing the substrate. A space between two adjacent projections is 1 ?m-10 ?m; the transparent conducting material is formed on the top surface and the lateral surface of the projections of the insulation layer. Otherwise, the transparent conducting material is formed on the top surface and the plane surface around the bottom of the projections or formed on the top surface, the lateral surface and the plane surface around the bottom of the projections. The present invention also discloses a manufacturing method of the thin film transistor panel.
    Type: Application
    Filed: August 11, 2011
    Publication date: December 20, 2012
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY, CO., LTD.
    Inventors: Chiu-yi Chung, Cheng-ming He
  • Publication number: 20120267751
    Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8294276
    Abstract: A semiconductor device and a fabricating method thereof are provided. In one exemplary embodiment, a plurality of semiconductor dies are mounted on a laminating member, for example, a copper clad lamination, having previously formed conductive patterns, followed by performing operations of encapsulating, forming conductive vias, forming a solder resist and sawing, thereby fabricating a chip size package in a simplified manner. Fiducial patterns are further formed on the laminating member, thereby accurately positioning the semiconductor dies at preset positions of the laminating member.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 23, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Sang Won Kim, Boo Yang Jung, Sung Kyu Kim, Min Yoo, Seung Jae Lee
  • Patent number: 8288860
    Abstract: An integrated circuit package system includes: providing a base package of an elongated rectangular-box shape containing first electrical circuitry and including: forming a rectangular contact strip on and adjacent to a first end of the base package; and forming a base contact pad on and adjacent to a second end of the base package for connection to an electrical interconnect.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: October 16, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Chee Keong Chin, Yu Feng Feng, Wen Bin Qu
  • Publication number: 20120228770
    Abstract: A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.
    Type: Application
    Filed: May 18, 2012
    Publication date: September 13, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Kaushik Chanda, Daniel C. Edelstein
  • Patent number: 8227909
    Abstract: There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: July 24, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hideaki Sakaguchi, Mitsutoshi Higashi, Yuichi Taguchi, Akinori Shiraishi, Kei Murayama
  • Publication number: 20120168752
    Abstract: The invention provides a testkey structure for testing a chip. The testkey structure includes a metal pad and a first groove, wherein the first groove is disposed on the metal pad. The first groove is located between a first signal lead and a second signal lead of the chip. According to the first groove, the first signal lead and the second signal lead could be separated from each other to prevent the first signal lead and the second signal lead from shorting.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Inventor: Kun-Tai Wu
  • Publication number: 20120146222
    Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
    Type: Application
    Filed: February 21, 2012
    Publication date: June 14, 2012
    Inventor: John Smythe
  • Publication number: 20120098133
    Abstract: The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas.
    Type: Application
    Filed: October 22, 2010
    Publication date: April 26, 2012
    Applicant: International Business Machines Corporation
    Inventors: CHIH-CHAO YANG, Hsueh-Chung Chen
  • Patent number: 8124449
    Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Andreas Schloegl
  • Patent number: 8115214
    Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: February 14, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Publication number: 20120025371
    Abstract: A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.
    Type: Application
    Filed: July 27, 2011
    Publication date: February 2, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi MATSUI, Tsuyoshi EDA, Akira MATSUMOTO, Yoshitaka KYOUGOKU, Shinji WATANABE, Hirokazu HONDA
  • Patent number: 8097943
    Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive through hole vias (THV) are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: January 17, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Guruprasad G. Badakere, Zigmund R. Camacho, Lionel Chien Hui Tay
  • Publication number: 20120007244
    Abstract: A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Inventors: Mark Harrison, Evelyn Napetschnig, Franz Stueckler
  • Publication number: 20110309481
    Abstract: A method of manufacture of an integrated circuit packaging system includes: fabricating a flip chip integrated circuit die having chip interconnects on an active side; providing a substrate for coupling the flip chip integrated circuit die by the chip interconnects; and applying a conductive underfill directly on the active side to completely fill a stand-off space surrounding the chip interconnects.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 22, 2011
    Inventors: Rui Huang, Seng Guan Chow, Heap Hoe Kuan
  • Publication number: 20110309510
    Abstract: An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.
    Type: Application
    Filed: August 31, 2011
    Publication date: December 22, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-Hun LEE, Do-Hyun KIM, Eun-Guk LEE, Chang-Oh JEONG
  • Patent number: 8076764
    Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: December 13, 2011
    Assignee: Elpida Memory Inc.
    Inventors: Junji Yamada, Hiroaki Ikeda, Kayoko Shibata, Yoshihiko Inoue, Hitoshi Miwa, Tatsuya Ijima
  • Patent number: 8058726
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device comprises a semiconductor die including a bond pad, a redistribution layer, and a solder ball. The redistribution layer is formed by sequentially plating copper and nickel, sequentially plating nickel and copper, or sequentially plating copper, nickel, and copper. The redistribution layer includes a nickel layer in order to prevent a crack from occurring in a copper layer. Further, a projection is formed in an area of the redistribution layer or a dielectric layer to which the solder ball is welded and corresponds, so that an area of the redistribution layer to which the solder ball is welded increases, thereby increasing bonding power between the solder ball and the redistribution layer.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: November 15, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Jung Gi Jin, Jong Sik Paek, Sung Su Park, Seok Bong Kim, Tae Kyung Hwang, Se Woong Cha
  • Publication number: 20110260328
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a plurality of bit lines having a uniform width on a semiconductor substrate, an active region obliquely arranged to have a predetermined angle with respect to the bit lines, a spacer arranged around the bit lines connected to a center part of the active region. A contact pad is connected to a lower part of the bit lines. The spacer is formed not only at an upper part of sidewalls of the contact pad but also at sidewalls of the bit lines. As a result, a CD of the bit line contact increases, so that a bit line contact patterning margin also increases. A bit line pattern having a uniform width is formed so that a patterning margin increases. A storage electrode contact self-alignment margin increases so that a line-type storage electrode contact margin increases.
    Type: Application
    Filed: July 5, 2011
    Publication date: October 27, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Byung Sub NAM
  • Patent number: 8039303
    Abstract: A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: October 18, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Yaojian Lin
  • Patent number: 8013441
    Abstract: One aspect of the invention relates to a power semiconductor device in lead frame technology and a method for producing the same. The power semiconductor device has a vertical current path through a power semiconductor chip. The power semiconductor chip has at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a lead frame chip island of a lead frame and the top side electrode is electrically connected to an internal lead of the lead frame via a connecting element. The connecting element has an electrically conductive film on a surface facing the top side electrode, the electrically conductive film extending from the top side electrode to the internal lead.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: September 6, 2011
    Assignee: Infineon Technologies AG
    Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober
  • Patent number: 8008776
    Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.
    Type: Grant
    Filed: February 2, 2008
    Date of Patent: August 30, 2011
    Assignee: Megica Corporation
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang