Abstract: A biosensor for measuring an electrical response from a biological sample. The biosensor includes a substrate, a passivation layer grown on a surface of the substrate, a patterned catalyst layer deposited on the passivation layer, and three electrodes grown on the patterned catalyst layer. The three electrodes include a working electrode, a counter electrode, and a reference electrode. The working electrode includes a first array of electrically conductive biocompatible nanostructures that is configured to be an attachment site for the biological sample. The counter electrode includes a second array of electrically conductive biocompatible nanostructures that is configured to acquire the electrical response from the working electrode. The reference electrode includes a third array of electrically conductive biocompatible nanostructures that is configured to adjust a specific voltage around the working and the counter electrodes.

Abstract: Disclosed is a semiconductor device that includes a semiconductor chip; bonding pads provided to the semiconductor chip; a plurality of lead terminals arranged around the semiconductor chip; a plurality of bonding wires that electrically connect the semiconductor chip with the plurality of lead terminals; and a resin encapsulant which encapsulates the semiconductor chip and the bonding wires, the semiconductor device further having an insulating material interposed at the interface between the bonding wires and the resin encapsulant, and the insulating material containing a nanometer-sized insulating particle and amorphous silica.

Abstract: An electrochemically-gated field-effect transistor includes a source electrode, a drain electrode, a gate electrode, a transistor channel and an electrolyte. The transistor channel is located between the source electrode and the drain electrode. The electrolyte completely covers the transistor channel and has a one-dimensional nanostructure and a solid polymer-based electrolyte that is employed as the electrolyte.

Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.

Abstract: A bonding structure of a ball-bonded portion is obtained by bonding a ball portion formed on a front end of a multilayer copper bonding wire. The multilayer copper bonding wire includes a core member that is mainly composed of copper, and an outer layer that is formed on the core member and is mainly composed of at least one noble metal selected from a group of Pd, Au, Ag and Pt. Further, a first concentrated portion of such noble metal(s) is formed in a ball-root region located at a boundary with the copper bonding wire in a surface region of the ball-bonded portion.

Abstract: This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surface to the second-side surface, providing a first end on the first-side surface and a second end on the second-side surface. A local isolation layer is deposited on the via's sidewall and on a portion of the first-side surface surrounding the first end. The TSV structure further comprises a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip. A majority of the microstructures has a depth of at least 1 ?m.

Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.

Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.

Abstract: A bonding structure and a copper bonding wire for semiconductor device include a ball-bonded portion formed by bonding to the aluminum electrode a ball formed on a front end of the copper bonding wire. After being heated at any temperature between 130° C. and 200° C., the ball-bonded portion exhibits a relative compound ratio R1 of 40-100%, the relative compound ratio R1 being a ratio of a thickness of a Cu—Al intermetallic compound to thicknesses of intermetallic compounds that are composed of Cu and Al and formed on a cross-sectional surface of the ball-bonded portion.

Abstract: A semiconductor package including a substrate, a semiconductor device, a protection layer, a bonding wire, and a molding compound is provided. The substrate has a contact pad and a solder mask, and the contact pad is exposed from the solder mask. The semiconductor device is disposed on the substrate. The protection layer is disposed on the contact pad. The bonding wire connects the semiconductor device to the contact pad. An end of the bonding wire penetrates the protection layer and bonds with a portion of a surface of the contact pad to form a bonding region. The protection layer covers an entire surface of the contact pad except the bonding region. The molding compound covers the semiconductor device, the contact pad, and the bonding wire.

Abstract: A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted.

Abstract: An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device includes a semiconductor chip provided on a lead frame, which are encapsulated with an encapsulating resin. Lead frames are provided in both sides of the lead frame. A portion of the lead frame is encapsulated with the encapsulating resin to function as an inner lead. The encapsulating resin is composed of a resin composition that contains substantially no halogen. Further, an exposed portion of the Al pad provided in the semiconductor chip is electrically connected to the inner lead via the AuPd wire.

Abstract: In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

Abstract: A semiconductor package comprises a bond pad formed on a first semiconductor die, a surface of the bond pad exposed through an opening in a passivation layer on the first semiconductor die; a raised conductive area formed on top of a passivation layer on a second semiconductor die; and a bond wire having a first end coupled to the bond pad via a ball bond and a second end coupled directly to a surface of the raised conductive area via a stitch bond. The raised conductive area is comprised of a plurality of metal layers, each of the metal layers comprised of a respective material and having a respective thickness. The thickness and material of at least one of the plurality of metal layers is selected such that a hardness of the raised conductive area is at least as hard as a hardness of the bond wire.

Abstract: Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

Abstract: A gold wire for semiconductor element connection having high strength and bondability. The connection has a limited amount of at least one element selected from calcium and rare earth elements, and a limited amount of at least one element selected from a group consisting of titanium, vanadium, chromium, hafnium, niobium, tungsten, and zirconium. The incorporation of a suitable amount of palladium or beryllium is preferred. The incorporation of calcium and rare earth element can improve the strength and young's modulus of a gold wire, and the incorporation of titanium and the like can reduce a deterioration in the roundness of press-bonded shape of press-bonded balls in the first bonding caused by the incorporation of calcium and rare earth elements. The bonding wire can simultaneously realize mechanical properties and bondability capable of meeting a demand for a size reduction in semiconductor and a reduction in electrode pad pitch.

Abstract: A semiconductor device includes an electrode pad provided on a semiconductor chip, the electrode pad includes aluminum (Al) of between 50% wt. and 99.9% wt. and further includes copper (Cu), a coupling ball that primarily includes Cu, the coupling ball being coupled to the electrode pad so that a CuAl2 layer, a CuAl layer, a layer including one of Cu9Al4 and Cu3Al2, and the coupling ball are vertically stacked in this order on the electrode pad, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and a junction between the electrode pad and the coupling ball.

Abstract: On embodiment is directed to a welding pad capable of receiving a ball-shaped copper wire at its end, including a first copper pad coated with a protection layer and topped with a second pad containing aluminum having dimensions smaller than those of the first pad and smaller than the ball diameter once said ball has been welded to the welding pad.

Abstract: Disclosed is a constitution formed from an oxide of an element having a smaller work function than aluminum. This oxide is comprises an oxide of vanadium (V), an oxide of an alkaline earth metal and an oxide of an alkali metal. The elements for the alkaline earth metal are comprise one or more elements out of the elements calcium (Ca), strontium (Sr) and barium (Ba) and at least contain barium. The elements for the alkali metal include at least one or more of sodium (Na), potassium (K), rubidium (Rb) and cesium (Cs). When the element vanadium is included as vanadium pentoxide (V2O5), the vanadium pentoxide content is 40-70 wt %. Thus, a glass composition for aluminum electrode wiring with an apparent work function for electrode wiring that is smaller than the work function for aluminum (Al) can be provided without the inclusion of lead.

Abstract: A semiconductor device includes an electrode pad provided on a semiconductor chip, in which the electrode pad includes aluminum (Al) as a major constituent and further including copper (Cu), a coupling ball primarily including Cu, the coupling ball is coupled to the electrode pad such that a plurality of layers of Cu and Al alloys are formed at a junction between the electrode pad and the coupling ball, and an encapsulating resin including a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and the junction between the electrode pad and the coupling ball. A dimensional area of the plurality of layers of Cu and Al alloys is equal to or larger than 50% of a dimensional area of the junction between the electrode pad and the coupling ball. The plurality of layers of Cu and Al alloys includes a CuAl2 layer, a CuAl layer formed on the CuAl2 layer, and a layer including one of Cu9Al4 and Cu3Al2 formed on the CuAl layer.

Abstract: It is an object of the present invention to provide a bonding structure and a copper bonding wire for semiconductor that are realizable at an inexpensive material cost, superior in a long-term reliability of a bonded portion bonded to an Al electrode, and suitable for use in a vehicle-mounted LSI. A ball-bonded portion is formed by bonding to the aluminum electrode a ball formed on a front end of the copper bonding wire. After being heated at any temperature between 130° C. and 200° C., the aforementioned ball-bonded portion exhibits a relative compound ratio R1 of 40-100%, the relative compound ratio R1 being a ratio of a thickness of a Cu—Al intermetallic compound to thicknesses of intermetallic compounds that are composed of Cu and Al and formed on a cross-sectional surface of the ball-bonded portion.

Abstract: A semiconductor device of the present invention includes a semiconductor element having an electrode pad; a substrate over which the semiconductor element is mounted and has an electrical bonding part; and a bonding wire electrically connecting the electrode pad to the electrical bonding part, wherein a main metal component of the electrode pad is the same or different from a main metal component of the bonding wire, and when the main metal component of the electrode pad is different from the main metal components of the bonding wire, a rate of interdiffusion of the main metal components of the bonding wire and the electrode pad at a junction of the bonding wire and the electrode pad under a post-curing temperature of an encapsulating resin is lower than that of interdiffusion of gold (Au) and aluminum (Al) at a junction of aluminum (Al) and gold (Au) under the post-curing temperature.

Abstract: A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink.

Abstract: An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit, a second circuit, at least one interconnect line and an electrostatic discharge protection circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically connected to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically connected to the second circuit. The first internal bonding pad is electrically connected to the second internal bonding pad via the bonding wire. The first internal bonding pad is electrically connected to the electrostatic discharge protection circuit via the interconnect line. The electrostatic discharge protection circuit is electrically connected to the external bonding pad which is used for electrically connecting an external package lead.

Abstract: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires.

Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad.

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract: An RFID transponder having a semiconductor die with a solderable contact area and an antenna made from a winding wire, wherein the winding wire is soldered to the contact area, and the solderable contact area is made from a nickel based alloy.

Abstract: A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip.

Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.

Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.

Abstract: One embodiment includes an encapsulated semiconductor package having a lead frame with die pad surrounded by a plurality of first and second leadfingers. A semiconductor chip including chip contact pads on its upper active surface is attached to the die pad. A plurality of first bond wires, including a first electrically conductive material, extend between the chip contact pads and the plurality of first leadfingers. A plurality of second bond wires, including a second electrically conductive material, extend between a chip contact pad and a second leadfinger. The semiconductor package further includes a plurality of electrically conducting means attached to the second leadfingers.

Abstract: An electrically conductive interconnect system has a post, extending above a supporting surface, the post including a rigid material, a coating on the rigid material, wherein the post and has a first width at the supporting surface and a second width at a distance removed from the supporting surface, and the post narrows from the first width to the second width. A method of electrically connecting a portion of a first supporting surface to a portion of a second supporting surface involves bringing a post on the first supporting surface into contact with an electrically conductive material located on the second supporting surface, softening the electrically conductive material, causing a separation distance between the first supporting surface and the second supporting distance to decrease so that a portion of the post will be surrounded by the electrically conductive material, and allowing the temperature of the electrically conductive material to decrease.

Abstract: The device of this invention includes a semiconductor die attached to a bare copper lead frame and electrically coupled to a lead by a metal wire coated with a metallic material. The device would function similarly to devices where the lead frames were coated with other metallic materials, but at lower costs because instead of plating the lead frame the wire is plated. The wire can be either gold or aluminum. When the wire is gold, the coating may be silver or other suitable metallic materials. When the wire is aluminum, the coating may be nickel, palladium, or other suitable metals.

Abstract: A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 ?m aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 ?m. Another possibility is provide an extra 0.6 ?m aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 ?m aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0.6 ?m and another barrier layer of 60 nm.

Abstract: A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts.

Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.

Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

Abstract: A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.

Abstract: The present invention aims to make possible facile removal of resin burrs without the risk of damaging resin body covering a wiring lead in a semiconductor device. In detail, the semiconductor device 10 has a structure in which a semiconductor element is mounted on the wiring lead 10, the wiring lead 10 including a metal plate with metal coating applied to the outer surface thereof. The peripheral region 15 of the wiring lead 11 is covered with an organic coating including purine skeleton compounds. The organic coating is formed through the self-assembling of functional organic compounds each having a structure in which a purine skeleton has at an end thereof a functional group having a metal bonding property.

Abstract: A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip.

Abstract: According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer contact members. First metal wirings are provided on the first upper-layer contact members. Second metal wirings are provided on the plugs. A height of a top surface of the plugs is higher than a top surface of the first metal wirings. A width of a bottom surface of the first metal wirings in a shorter-side direction is shorter than a width of a top surface of the first metal wirings. A width of a bottom surface of the second metal wirings in a shorter-side direction is shorter than a width of a top surface of the second metal wirings.

Abstract: A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer.

Abstract: A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.

Abstract: A semiconductor device includes a semiconductor chip, an electrode pad provided in the semiconductor chip, in which the electrode pad includes Al as a major constituent and further includes Cu, a coupling member coupled to the electrode pad, in which the coupling member primarily includes Cu, a plurality of layers of Cu and Al alloys formed between the electrode pad and the coupling member, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, in which the encapsulating resin encapsulates the semiconductor chip, the electrode pad, and the coupling member. The plurality of layers of Cu and Al alloys includes a CuAl2 layer formed on the electrode pad, a CuAl layer formed on the CuAl2 layer, and a layer including one of Cu9Al4 and Cu3Al2 formed on the CuAl layer.

Abstract: Hybrid semiconductor materials have an inorganic semiconductor incorporated into a hole-conductive fluorene copolymer film. Nanometer-sized particles of the inorganic semiconductor may be prepared by mixing inorganic semiconductor precursors with a steric-hindering coordinating solvent and heating the mixture with microwaves to a temperature below the boiling point of the solvent.

Abstract: A package structure and method for preventing gold bonding wires from collapsing are disclosed. The structure is especially useful for those chips whose two n×1 arrays of bonding pads are on the chip center to be packaged on a BGA substrate. According to the first preferred embodiment, two dies having a redistribution layer formed thereon are introduced outer the bonding pad array on the chip so that the gold bonding wires can be divided into two sections each to connect the bonding pads with the redistribution layer and the redistribution layer with the gold fingers on the BGA substrate. According to the second embodiment, the gold bonding wires are fixed by the epoxy strips on the chips after bonding the bonding pads to the gold fingers but before pouring liquid encapsulated epoxy into a mold.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: Gold wire for connecting a semiconductor chip basically containing praseodymium in 0.0004 mass % to 0.02 mass % in range and, considering the bonding characteristics, containing beryllium or aluminum or both in limited ranges and, considering the precipitates formed in the gold wire, further containing auxiliary additive elements of calcium, lanthanum, cerium, neodymium, and samarium in limited ranges.