Consisting Of Soldered Or Bonded Constructions (epo) Patents (Class 257/E23.023)

  • Patent number: 10043736
    Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: August 7, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Peter Wilson, Yan Huo, Zhiqiang Niu, Ming-Chen Lu
  • Patent number: 9425181
    Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.
    Type: Grant
    Filed: May 2, 2015
    Date of Patent: August 23, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Peter Wilson, Yan Huo, Zhiqiang Niu, Ming-Chen Lu
  • Patent number: 9040407
    Abstract: A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a seed for plating a conductive material, exposing the opening to an electroplating solution including the conductive material, the conductive material is not present in the alloying layer, applying an electrical potential to a cathode causing the conductive material to deposit from the electroplating solution onto the cathode exposed at the bottom of the opening and causing the opening to fill with the conductive material, the cathode includes an exposed portion of the seed layer and excludes the alloying layer, and forming a first intermetallic compound along an intersection between the alloying layer and the conductive material, the first intermetallic compound is formed as a precipitate within a solid solution of the alloying layer and the conductive material.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Patent number: 9013037
    Abstract: A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics Pte Ltd.
    Inventor: Yonggang Jin
  • Patent number: 9006905
    Abstract: A semiconductor device with a semiconductor substrate having a first surface and an opposite-facing second surface, a through electrode electrically connected to the semiconductor element and penetrating the semiconductor substrate from the first surface to the second surface, and a conductor, not electrically connected to the semiconductor element, penetrating the semiconductor substrate from the first surface to the second surface, where the through electrode and the conductor have different shapes in plan view.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 14, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Nobuyuki Nakamura
  • Patent number: 8987898
    Abstract: According to one embodiment, a semiconductor wafer comprises a plurality of solder bumps for providing device contacts formed over a functional region of the semiconductor wafer, and one or more support rings surrounding the functional region. The one or more support rings and the plurality of solder bumps are formed so as to have substantially matching heights. The presence of the one or more support rings causes the semiconductor wafer to have a substantially uniform thickness in the functional region after a thinning process is performed on the semiconductor wafer. A method for fabricating the semiconductor wafer comprises forming the plurality of solder bumps over the functional region, and forming the one or more support rings surrounding the functional region before performing the thinning process on the semiconductor wafer.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Rupert Burbidge, David Paul Jones, Amarjit Dhadda, Robert Montgomery
  • Patent number: 8987884
    Abstract: A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8975175
    Abstract: A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 10, 2015
    Assignee: SunPower Corporation
    Inventor: Thomas Pass
  • Patent number: 8970051
    Abstract: A method including forming a contact pad array on an integrated circuit substrate, the contact pad array including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads; and depositing solder on the accessible area of the contact pads. An apparatus including an integrated circuit substrate including a body having a nonplanar shape and a surface including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Hualiang Shi, Shengquan E. Ou, Sairam Agraharam, Tyler N. Osborn
  • Patent number: 8970012
    Abstract: A semiconductor device is provided, including a semiconductor substrate that includes a semiconductor; an electrode layer formed above a first surface side inside the semiconductor substrate; a conductor layer formed above the electrode layer and above the first surface of the semiconductor substrate; a hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate, the wiring layer being physically separated from the electrode layer by an insulating layer disposed therebetween.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: March 3, 2015
    Assignee: Sony Corporation
    Inventor: Masaya Nagata
  • Patent number: 8963333
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 8957522
    Abstract: According to one embodiment, the semiconductor device in the embodiment has an assembly substrate, a semiconductor chip, and a jointing layer. The semiconductor chip is joined to the assembly substrate via the jointing layer. An intervening diffusion barrier layer may be interposed between the chip and jointing layer. The jointing layer is an alloy layer mainly made of any metal selected from Sn, Zn and In or an alloy of Sn, Zn and In, and any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V or an alloy of any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V and any metal selected from Sn, Zn and In, where the alloy has a higher melting temperature than that of Sn, Zn and In or an alloy of Sn, Zn and/or In.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yo Sasaki, Daisuke Hiratsuka, Atsushi Yamamoto, Kazuya Kodani, Yuuji Hisazato, Hitoshi Matsumura
  • Patent number: 8952550
    Abstract: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Madhav Datta, Dave Emory, Subhash M. Joshi, Susanne Menezes, Doowon Suh
  • Patent number: 8951445
    Abstract: A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Brunschwiler, Javier V. Goicochea, Cyrill Kuemin, Walter H. Riess, Heiko Wolf
  • Patent number: 8937390
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: January 20, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
  • Patent number: 8916448
    Abstract: The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Mukta G. Farooq, John A. Fitzsimmons
  • Patent number: 8907489
    Abstract: A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 9, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuji Kunimoto, Naoyuki Koizumi
  • Patent number: 8896132
    Abstract: An electronic device 1 has a first semiconductor substrate 2 on which a bonding projection section 42 is projected via an insulation film 41, a second semiconductor substrate 3 that is bonded by welding the bonding projection section 42 of the first semiconductor substrate 2 via conductive bonding material, a through hole 54 that is formed to penetrate the bonding projection section 42 and the insulation film 41 in a bonding direction, and a conduction wiring section 44 that is formed by the conductive bonding material filled in the through hole 54 at a time of bonding by welding and conducts the first semiconductor substrate 2 with the second semiconductor substrate 3 to have same electric potential.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: November 25, 2014
    Assignees: Pioneer Corporation, Pioneer Micro Technology Corporation
    Inventors: Naoki Noda, Mitsuru Koarai, Toshio Yokouchi, Masahiro Ishimori
  • Patent number: 8896119
    Abstract: A semiconductor device is provided which has internal bonds which do not melt at the time of mounting on a substrate. A bonding material is used for internal bonding of the semiconductor device. The bonding material is obtained by filling the pores of a porous metal body having a mesh-like structure and covering the surface thereof with Sn or an Sn-based solder alloy.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: November 25, 2014
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Yoshitsugu Sakamoto, Hiroyuki Yamada, Yoshie Yamanaka, Tsukasa Ohnishi, Shunsaku Yoshikawa, Kenzo Tadokoro
  • Patent number: 8890338
    Abstract: A chip and a method of fabricating the chip for low cost chip identification circuitry. In one embodiment, a method of manufacturing an integrated circuit includes formation of a multi-level metallization structure including a pad level comprising programming pads. A plurality of active devices are formed on a substrate, and multiple levels of metallization are formed over the active devices, connecting some of the active devices to form programmable circuitry. The programmable circuitry is connected to pairs of programming pads on the bond pad level. Programming pads in some of the pairs are selectively connected to one another by using conductive ink deposited with maskless inkjet printing techniques. The pads are then covered with a non-conductive protective layer.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 18, 2014
    Assignee: Agere Systems, Inc.
    Inventor: Edward B. Harris
  • Patent number: 8890322
    Abstract: A semiconductor apparatus including a semiconductor substrate having a first principal surface on which an electric circuit is formed and a second principal surface opposed to the first principal surface, and a through hole that penetrates the first principal surface and the second principal surface, a multilayered wiring layer having a plurality of conductive wiring layers connected to the electric circuit and a plurality of inter-layer insulating layers having an insulating layer opening of a same size and at a same position as a through hole opening which is an opening of the first principal surface of the through hole, an electrode pad that covers the insulating layer opening connected to the conductive wiring layer and a lead-out wiring layer having a through wiring layer connected to the electrode pad formed inside the through hole and a connection wiring layer formed integral with the through wiring layer.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: November 18, 2014
    Assignee: Olympus Corporation
    Inventor: Takatoshi Igarashi
  • Patent number: 8884429
    Abstract: A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 11, 2014
    Assignee: Unimicron Technology Corporation
    Inventor: Zhao-Chong Zeng
  • Patent number: 8872340
    Abstract: A substrate for a semiconductor package includes: a first dielectric having a first surface and a second surface which faces away from the first surface and possesses waveform shaped portions, and formed with first holes penetrating the first and second surfaces; and circuit traces formed over the second surface of the first dielectric and having waveform shaped portions disposed over the waveform shaped portions of the second surface of the first dielectric. The waveform shaped portions of the second surface of the first dielectric and the waveform shaped portions of the circuit traces form a stress-resistant structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Hoon Kim
  • Patent number: 8853732
    Abstract: The invention relates to an optoelectronic component, having —a carrier (1) comprising a first main surface (Ia), —at least one optoelectronic semiconductor chip (2) having no substrate, and —a contact metallization (3a, 3b), wherein —the carrier (1) is electrically insulating, —the at least one optoelectronic semiconductor chip (2) is fastened to the first main surface (Ia) of the carrier (1) by means of a bonding material (4), particularly a solder material, —the contact metallization (3a, 3b) covers at least one area of the first main surface (Ia) free of the optoelectronic semiconductor chip (2), and —the contact metallization (3a, 3b) is electrically conductively connected to the optoelectronic semiconductor chip (2).
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: October 7, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Klaus Müller, Günter Spath, Siegfried Herrmann, Ewald Karl Michael Günther, Herbert Brunner
  • Patent number: 8841647
    Abstract: A flexible substrate includes: a flexible base substrate; a plurality of display structures on a first surface of the flexible base substrate; and a barrier coating on a second surface of the flexible base substrate to prevent contaminants from penetrating into the display structures.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: September 23, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Yong In Park, Seung Han Paek, Sang Soo Kim
  • Patent number: 8829488
    Abstract: Provided is a laminate containing a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×1018 cm3 or more.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuyoshi Furukawa, Yasuhiko Akaike, Shunji Yoshitake
  • Patent number: 8829673
    Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Cha, Chita Chuang, Yao-Chun Chuang, Hao-Juin Liu, Tsung-Hsien Chiang, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 8810043
    Abstract: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takao Nishimura, Yoshikazu Kumagaya, Akira Takashima, Kouichi Nakamura, Kazuyuki Aiba
  • Patent number: 8796851
    Abstract: The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Ming Chuang, Chun Che Huang, Shih-Chieh Chang
  • Patent number: 8791005
    Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Patent number: 8786104
    Abstract: A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: July 22, 2014
    Assignee: Infineon Technologies AG
    Inventor: Hans-Joachim Barth
  • Patent number: 8786084
    Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Jean-François Sauty
  • Patent number: 8786108
    Abstract: A package structure is provided, which includes a dielectric layer having opposing first and second surfaces, and through holes penetrating the surfaces; a strengthening layer formed on the first surface; a circuit layer formed on the second surface, and having wire bonding pads formed thereon and exposed from the through holes, and ball pads electrically connected to the wire bonding pads; a first solder mask layer formed on the first surface and the strengthening layer, and having first apertures formed therethrough for exposing the wire bonding pads; a second solder mask layer formed on the second surface and the circuit layer, and having second apertures formed therethrough for exposing the ball pads; and a semiconductor chip disposed on the first solder mask layer and electrically connected via conductive wires to the wire bonding pads exposed from the through holes. The strengthening layer ensures the steadiness of the chip to be mounted thereon without position shifting.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 22, 2014
    Assignee: Unimicron Technology Corporation
    Inventor: Kun-Chen Tsai
  • Patent number: 8786109
    Abstract: A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a plurality of first pads and second pads. The pad area is defined with a first area, a second area and a third area, wherein the first area is located between the second area and the third area. Each of the first pads and the second pads are interlaced to each other on the first area. The conductive structure comprises a plurality of conductive bumps formed on each of the first pads and the second pads respectively to electrically connect with each of the first pads and the second pads. Each of the conductive bumps has a first bump-width disposed on the first area and a second bump-width disposed on one of the second and third areas in which the first bump-width is shorter than the second bump-width.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: July 22, 2014
    Assignee: Chipmos Technologies Inc.
    Inventor: Chung-Pang Chi
  • Patent number: 8779587
    Abstract: An electronic device, comprising a semiconductor substrate having a first metal pad formed thereover, a device package substrate having a second metal pad formed thereover, and, a doped solder bump. The doped solder bump is located between and in contact with said first and second metal pads. The doped solder bump consisting of Sn, one or both of Ag and Cu, and a fourth row transition metal dopant in a concentration range from 0.35 wt. % to 2 wt. %.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: July 15, 2014
    Assignee: Agere Systems LLC
    Inventors: Mark Bachman, John W. Osenbach
  • Patent number: 8766455
    Abstract: A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: SeYoung Jeong, Sunpil Youn, Hogeon Song
  • Patent number: 8759974
    Abstract: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: June 24, 2014
    Assignee: Intel Corporation
    Inventors: Mengzhi Pang, Pilin Liu, Charavanakumara Gurumurthy
  • Patent number: 8748232
    Abstract: Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: June 10, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Arkadii V. Samoilov, Tyler Parent, Larry Y. Wang
  • Patent number: 8748305
    Abstract: A semiconductor device is provided which includes a semiconductor substrate having a plurality of microelectronic elements formed therein; an interconnect structure formed over the substrate, the interconnect structure including metal layers isolated from one another by an inter-metal dielectric, the metal layers including a topmost metal layer; dummy metal vias formed between at least two metal layers and disposed within a region of the interconnect structure; and a bonding pad formed over the topmost metal layer such that the bonding pad is aligned with the region of the interconnect structure.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8742596
    Abstract: Disclosed herein is a semiconductor device including: a first laminate having a wiring layer formed on a substrate; a second laminate having a wiring layer formed on a substrate, a principal surface of the second laminate being bonded to a principal surface of the first laminate; a functional element disposed in at least one of the first laminate and the second laminate; and an air gap penetrating an interface between the first laminate and the second laminate, the air gap being disposed on an outside of a circuit formation region including the functional element in at least one of the first laminate and the second laminate as viewed from a direction perpendicular to the principal surfaces of the first laminate and the second laminate.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventor: Takaaki Hirano
  • Patent number: 8742576
    Abstract: An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: June 3, 2014
    Assignee: Oracle International Corporation
    Inventors: Hiren D. Thacker, Hyung Suk Yang, Ivan Shubin, John E. Cunningham
  • Patent number: 8741738
    Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Hsun Chiu, Ting-Ying Chien, Ching-Hou Su, Chyi-Tsong Ni
  • Patent number: 8736027
    Abstract: A semiconductor device includes: a semiconductor substrate that includes a semiconductor; an electrode layer formed on a first surface side inside the semiconductor substrate; a frame layer laminated on the first surface of the semiconductor substrate; a conductor layer formed in an aperture portion formed by processing the semiconductor substrate and the frame layer in such a manner as to expose the electrode layer on the first surface of the semiconductor substrate; a vertical hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: May 27, 2014
    Assignee: Sony Corporation
    Inventor: Masaya Nagata
  • Patent number: 8723323
    Abstract: A method for fabricating an electronic device package having a column grid array is disclosed. A column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate. The column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: May 13, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Thomas J. McIntyre, Keith K. Sturcken, Christy A. Hagerty
  • Publication number: 20140124939
    Abstract: A method of making an electronic device having a discrete device mounted on a surface of an electronic die with both the discrete device and the die connected by heat cured conductive ink and covered with cured encapsulant including placing the discrete device on the die; and keeping the temperature of each of the discrete device and the die below about 200° C. Also disclosed is a method of electrically attaching a discrete device to a substrate that includes placing the device on the substrate, applying conductive ink that connects at least one terminal on the device to at least one contact on the substrate and curing the conductive ink. Also disclosed is an IC package with a discrete electrical device having electrical terminals; an electrical substrate having contact pads on a surface thereof; and cured conductive ink connecting at least one of the electrical terminals with at least one of the contact pads.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew David Romig, Lance Cole Wright, Leslie Edward Stark, Frank Stepniak, Sreenivasan K. Koduri
  • Patent number: 8704364
    Abstract: An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 22, 2014
    Assignee: Xilinx, Inc.
    Inventor: Bahareh Banijamali
  • Patent number: 8704352
    Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: April 22, 2014
    Inventors: Nae Hisano, Shigeo Ohashi, Yasuo Osone, Yasuhiro Naka, Hiroyuki Tenmei, Kunihiko Nishi, Hiroaki Ikeda, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama
  • Patent number: 8703543
    Abstract: A method to vertically bond a chip to a substrate is provided. The method includes forming a metal bar having a linear aspect on the substrate, forming a solder paste layer over the metal bar to form a solder bar, forming a plurality of metal pads on the substrate, and forming a solder paste layer over the plurality of metal pads to form a plurality of solder pads on the substrate. Each of the plurality of solder pads is offset from a long edge the solder bar by an offset-spacing. The chip to be vertically bonded to the substrate has a vertical-chip thickness fractionally less than the offset-spacing. The chip to be vertically bonded fits between the plurality of solder pads and the solder bar. The solder bar enables alignment of the chip to be vertically bonded.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: April 22, 2014
    Assignee: Honeywell International Inc.
    Inventors: Hong Wan, Ryan W. Rieger, Michael J. Bohlinger
  • Patent number: 8703508
    Abstract: Disclosed is a method for wafer-level testing a plurality of diced multi-chip stacked packages. Each package includes a plurality of chips with vertically electrical connections such as TSVs. Next, according to a die-on-wafer array arrangement, the multi-chip stacked packages are fixed on a transparent reconstructed wafer by a photo-sensitive adhesive, and the packages are located within the component-bonding area of the wafer. Then, the transparent reconstructed wafer carrying the multi-chip stacked packages can be loaded into a wafer tester for probing. Accordingly, the wafer testing probers in the wafer tester can be utilized to probe the testing electrodes of the stacked packages so that it is easy to integrate this wafer-level testing method especially into TSV packaging processes.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: April 22, 2014
    Assignee: Powertech Technology Inc.
    Inventors: Kai-Jun Chang, Yu-Shin Liu, Shin-Kung Chen, Kun-Chih Chan
  • Publication number: 20140103532
    Abstract: An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Inventors: Jenn Hwa Huang, Jose L. Suarez, Yun Wei