Abstract: A semiconductor device comprises: a semiconductor chip having a first electrode on one face; a circuit board having a second electrode on a mounting face; a warp suppressing layer to suppress a warp of at least the semiconductor chip; and a stress relaxing layer to relax stress arising between the semiconductor chip and the warp suppressing layer.

Abstract: A contact device for use with a power semiconductor component in a power semiconductor module or a disc-type thyristor, the module or thyristor having a molded body with a first recess disposed above the component. The contact device makes electrical contact with the auxiliary connection of the component, and is disposed within a second recess in the module or thyristor. The contact device includes a spring having a pin-like extension at a first end thereof that faces the component and a metal molded body that is arranged at the opposite end thereof and has a first connecting device formed as a flat section of the metal molded body. The flat section is arranged generally parallel to the component, and has a second connecting device for connection to a connecting cable. The connecting device may also have a multipart insulating housing for holding the contact spring and the metal molded body.

Abstract: A portable object connectable package for an electronic device comprises: semiconductor die package, having a top surface and an opposite bottom surface, and a connector body mechanically supported by the semiconductor die package. The bottom surface includes a plurality of connection elements for connecting to a printed circuit board. The connector body includes a plurality of resilient electrical connecting elements extending over the top surface for contacting with a portable object PO having a contacting area. The portable object connectable package is arranged to be coupled to a portable object positioner for removably positioning the contacting area of the portable object in contact with the plurality of resilient electrical connecting elements when the portable object is present in the portable object positioner.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: A device includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors proximate to the first surface. The first semiconductor die is configured to have a flexibility compliance greater than a first pre-determined value in a direction substantially perpendicular to a plane including the plurality of proximity connectors in order to reduce misalignment in the direction between the plurality of proximity connectors and additional proximity connectors on another device.

Abstract: A lead frame (200) for housing an integrated circuit is disclosed comprising a main member (220) and an engagement portion (230) for receiving an integrated circuit (210). The integrated circuit (210) is located at the engagement portion (230) and engaged with the lead frame through resilient engagement with the first and second engagement members (222, 223). The first and second engagement members (222,223) which depend from the main member, secure the integrated to the lead frame by engaging in resilient contact respective opposed surfaces of the integrated circuit. The integrated circuit is engaged to the lead frame by clipping into it into position between the engagement members. There is no need for a gluing process unlike conventional lead frame designs which where the integrated circuit is attached to a lead frame by gluing it onto the die paddle.

Abstract: A method of dividing an adhesive film mounted on the back surface of a wafer having a plurality of streets formed on the front surface in a lattice pattern and function elements formed in a plurality of areas sectioned by the plurality of streets, along the streets in a state where the wafer is put on the surface of a protective tape mounted on an annular frame, wherein the adhesive film is cooled and the protective tape is expanded to divide the adhesive film along the peripheries of the function elements.

Abstract: A semiconductor device includes a semiconductor element; a plate member disposed opposite to an electronic-circuit forming portion of the semiconductor element; and an elastic body arranged in a compressed state between the semiconductor element and the plate member, wherein the elastic body includes at least one first protruding portion at one end in an extension direction of the elastic body, the first protruding portion being formed opposite to the electronic-circuit forming portion of the semiconductor element, and the semiconductor element and the plate member are fastened by an adhesive agent.

Abstract: A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a semiconductor chip. Each lead frame can be located on a side surface and a bottom surface of the semiconductor package. In addition, the semiconductor device can include a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern.

Abstract: A semiconductor module including: a semiconductor chip in which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having an opening positioned corresponding to the electrode; an elastic protrusion disposed on the insulating film, a surface of the elastic protrusion opposite to the insulating film being convexly curved; an interconnect extending from over the electrode to over the elastic protrusion; an elastic substrate on which a lead is formed, the lead being in contact with part of the interconnect positioned on the elastic protrusion; and an adhesive maintaining a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the lead is formed. The elastic substrate has a first depression formed by elastic deformation.

Abstract: A semiconductor module including: a semiconductor chip, an integrated circuit being formed in the semiconductor chip; a plurality of electrodes electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having a plurality of openings positioned corresponding to the plurality of electrodes; and a long elastic protrusion extending on the insulating film. A plurality of interconnects respectively extend from over the electrodes to over the elastic protrusion, directions of the interconnects intersecting an axis AX that is parallel to the extending direction of the elastic protrusion. A plurality of leads are respectively in contact with the interconnects in an area positioned on the elastic protrusion. A cured adhesive maintains a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the leads are formed.

Abstract: The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S100); forming a barrier metal layer on the whole surface of the insulating film (S102); forming a copper layer on the whole surface of the barrier metal layer so that the copper layer is embedded in the interconnect trench (S104); removing the copper layer outside the interconnect trench by polishing under a condition that the barrier metal layer is left on the surface of the insulating film (S106); selectively forming a cap metal layer on the copper layer formed in the interconnect trench after the step of removing the copper layer by polishing (S108); and flattening the cap metal layer by polishing (S110).

Abstract: Disclosed are spring structures that provide solderless electrical connections in semiconductor die packages. An exemplary spring structure comprises a first portion adapted to make an electrical connection to a conductive region of a semiconductor die, a second portion adapted to make an electrical connection to a conductive region of a leadframe, and a third portion disposed between the first and second portions. During a molding process, the third portion is compressively strained to impart forces to the first and second portions that maintain these portions in contact with the conductive regions of the die and leadframe. After the molding material sets, the third portion remains in a state of compressive strain, and imparts forces on the first and second portions that maintain the electrical connections. The spring structure may be made of less expensive materials, and does not require cleaning, fluxing, or reflowing, thereby reducing manufacturing cost and time.

Abstract: A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet.

Abstract: Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support portion having a through hole formed therein at a side of the lower silicon layer; and a cantilever arm forming of a junction oxidation layer pattern and an upper silicon layer pattern on the SOI substrate that are supported on an upper surface of the lower silicon layer and each have a smaller hole than the through hole, a silicon oxidation layer pattern having a tip including an aperture at a vertical end, corresponding with the hole on the upper silicon layer pattern, and an optical transmission prevention layer that is formed on the silicon oxidation layer pattern and does not cover the aperture.

Abstract: A plurality of vertically spaced-apart microsprings are provided to increase microspring contact force, contact area, contact reliability, and contact yield. The microspring material is deposited, either as a single layer or as a composite of multiple sub layers, to have a tailored stress differential along its cross-section. A lower microspring may be made to push up against an upper microspring to provide increased contact force, or push down against a substrate to ensure release during manufacture. The microsprings may be provided with similar stress differentials or opposite stress differentials to obtain desired microspring profiles and functionality. Microsprings may also be physically connected at their distal ends for increased contact force. The microsprings may be formed of electrically conductive material or coated with electrically conductive material for probe card and similar applications.

Abstract: Respective attracting openings of a bonding head are disposed so as to avoid joining regions at which bump electrodes (obverse electrodes) of a semiconductor chip are joined with bump electrodes of a package substrate. Bump electrodes (reverse electrodes) that are connected to the bump electrodes are provided at a reverse side of the semiconductor chip at positions opposing the bump electrodes. Because the attracting openings do not overlap the joining regions, the bump electrodes (reverse electrodes) are not suctioned at the joining regions.

Abstract: An apparatus for connecting at least two components contains a lower die and an upper die. The lower die has the components which are to be connected, with the first component supporting the at least second component with an at least partial overlap relative to the first component. The lower die and the upper die can be moved relative to one another. The upper die carries at least two heatable plungers which are connected so as to be able to move relative to one another via a sealed pressure pad. The plungers and the pressure pad have a first flexible layer between them. A second flexible layer is arranged between the upper die and the lower die.

Abstract: An integrated circuit interconnection system is disclosed. The system can include a first integrated circuit die having a first electrode configuration and a second integrated die having the same or a substantially similar electrode configuration. The system can also include a multilayer flexible cable having a first side and a second side that has substantially parallel conductors running along the cable. At least a portion of one of the parallel conductors can be exposed on the first side and/or the second side, such that the first and second integrated circuit die can be connected to both the first side and the second side of the multilayer flexible cable. The cable can be folded to provide a dense interconnect for stacked memory configurations.

Abstract: In a pressing cap forming part of a semiconductor device carrier unit, a pressing portion of a pressure body has recesses, to each of which a bump is inserted.

Abstract: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: Resilient spring contacts for use in wafer test probing are provided that can be manufactured with a very fine pitch spacing and precisely located on a support substrate. The resilient contact structures are adapted for wire bonding to an electrical circuit on a space transformer substrate. The support substrates with attached spring contacts can be manufactured together in large numbers and diced up and tested before attachment to a space transformer substrate to improve yield. The resilient spring contacts are manufactured using photolithographic techniques to form the contacts on a release layer, before the spring contacts are epoxied to the support substrate and the release layer removed. The support substrate can be transparent to allow alignment of the contacts and testing of optical components beneath. The support substrate can include a ground plane provided beneath the spring contacts for improved impedance matching.

Abstract: A tightly packed three-dimensional electronic system or subsystem comprising multiple stacks of semiconductor elements is described. The system is repairable because the elements connect together using re-workable flip chip connectors; each flip chip connector comprises a conductive spring element on one side and a corresponding well filled with solder on the other side. The spring elements relieve stresses at the interfaces and allow the component stacks to remain flat; they also provide vertical compliance for easing assembly of elements that have been imperfectly thinned or planarized. Semiconductor integration platforms may be used to integrate active and passive devices, multi-layer interconnections, through wafer connections, I/O plugs, and terminals for attachment of other semiconductor elements or cables.

Abstract: An electronic device includes: a semiconductor chip that includes an integrated circuit, a plurality of electrodes electrically connected to the integrated circuit, and a passivation film formed in a manner that at least a portion of each of the plurality of electrodes is exposed; a resin layer that is formed on the passivation film; a plurality of wirings, each of the plurality of wirings extending from a top surface of each of the plurality of electrodes to a top surface of the resin layer and electrically connected to each of the plurality of electrodes, respectively; a wiring substrate that has a wiring pattern opposing to and electrically connected to portions of the plurality of wirings above the resin layer; and a hardened adhesive resin that is placed between the semiconductor chip and the wiring substrate, wherein the adhesive resin internally has a residual stress that is generated by contraction at the time of hardening the adhesive resin, and a portion of the adhesive resin is disposed between a p

Abstract: One embodiment of the present invention provides an integrated circuit module. This module includes a semiconductor die with an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The module uses a flexible cable to deliver electrical power to the active face of the semiconductor die from a power distribution board located above the active face of the semiconductor die. This flexible cable provides electrical power to the semiconductor die without interfering with the alignment and heat removal functions of the module.

Abstract: A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology.

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers.

Abstract: The present invention relates to a donor laminate for transfer of a conductive layer comprising at least one electronically conductive polymer on to a receiver, wherein the receiver is a component of a device. The present invention also relates to methods pertinent to such transfers.

Abstract: The flexible package (100) has between a first (1) and a second side (2) a semiconductor device (20) with a thinned back substrate (10) and an interconnect structure. Contact means (31,33) for external contact and a first resin layer (52) are present at the first side (2) of the package (100), which contact means (31,33) are coupled to the interconnect structure. At the second side (2) the semiconductor device (20) is at least substantially covered with a second resin layer (12). The contact means (31,33) are present on the first resin layer (52) and are coupled to the interconnect structure with redistribution tracks (32,34) extending through the first resin layer (52). A passivation layer (55) covers the first resin layer (52) and the redistribution tracks (32,34) at least substantially.

Abstract: A novel method for providing bump structures that can be formed by conventional stud bump bonding techniques is disclosed. The bumps can be arranged in a buttressed configuration that allows for substantial lateral and vertical contact loads, and substantial heights. A side-by-side configuration may be used to build a stacked bump contact that is substantially taller and stronger than is possible under current techniques. Other arrangements can be selected to optimize the load bearing capacity in any direction or combination of directions.

Abstract: A microdevice (20) having a hermetically sealed cavity (22) to house a microstructure (26). The microdevice (20) comprises a substrate (30), a cap (40), an isolation layer (70), at least one conductive island (60), and an isolation trench (50). The substrate (30) has a top side (32) with a plurality of conductive traces (36) formed thereon. The conductive traces (36) provide electrical connection to the microstructure (26). The cap (40) has a base portion (42) and a sidewall (44). The sidewall (44) extends outwardly from the base portion (42) to define a recess (46) in the cap (40). The isolation layer (70) is attached between the sidewall (44) of the cap (40) and the plurality of conductive traces (36). The conductive island (60) is attached to at least one of the plurality of conductive traces (36). The isolation trench (50) is positioned between the cap (40) and the conductive island (60) and may be unfilled or at least partially filled with an electrically isolating material.

Abstract: A compliant interconnect is described that is useful for coupling semiconductor dies to other components. In one embodiment, the interconnect includes a base to couple to a first component and an arch extending from and integral with the base to couple to a second component. The interconnect may be formed by coating a substrate with photoresist, exposing the photoresist with a defined pattern, developing the photoresist, baking the photoresist at a first temperature for a first amount of time to reflow the photoresist, and baking the photoresist at a second higher temperature for a second amount of time to reflow the photoresist.

Abstract: Forming a packaged device having a semiconductor device having a first major surface and a second major surface includes forming an encapsulating layer over the second major surface of the semiconductor device and around sides of the semiconductor device and leaving the first major surface of the first semiconductor device exposed. A first insulating layer is formed over the first major surface. A plurality of vias are formed in the first insulating layer. A plurality of contacts are formed to the semiconductor device through the first plurality of vias, wherein each of the plurality of contacts has a surface above the first insulating layer. A supporting layer is formed over the first insulating layer leaving an opening over the first plurality of contacts wherein the opening has a sidewall surrounding the plurality of contacts.

Abstract: An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.

Abstract: An article of manufacture and system, as well as fabrication methods therefore, may include a plurality of lands disposed on a surface of a substrate wherein the lands are oriented at an angle to the surface of the substrate and further wherein the substrate is formed of conductive layers that are formed such that a non-conductive layer does not interpose between the conductive layers and their coupling.

Abstract: A method of forming an interconnection element. In one embodiment, the interconnection element includes a first structure and a second structure coupled to the first structure. The second structure coupled with the first material has a spring constant greater than the spring constant of the first structure alone. In one embodiment, the interconnection element is adapted to be coupled to an electronic component tracked as a conductive path from the electronic component. In one embodiment, the method includes forming a first (interconnection) structure coupled to a substrate to define a shape suitable as an interconnection in an integrated circuit environment and then coupling, such as by coating, a second (interconnection) structure to the first (interconnection) structure to form an interconnection element. Collectively, the first (interconnection) structure and the second (interconnection) structure have a spring constant greater than a spring constant of the first (interconnection) structure.

Abstract: A mounting member of a semiconductor device according to the present invention includes a wiring substrate to input and/or output actuating signals to a semiconductor device, a power supplying conductor plate to supply actuating power to the semiconductor device, and the GND conductor plate. The wiring substrate, the power supplying conductor plate, and the GND conductor plate are laminated with insulation films between respective layers. Input/output signals as well as minute driving current is supplied from wiring substrate, and the large main driving current is supplied through the power supplying conductor plate as well as the GND conductor plate.

Abstract: Introduced is a power semiconductor module preferably a disk cell with a power semiconductor element arranged in the interior of the housing. In a preferred embodiment, the disk cell has two load and at least one auxiliary connection and the auxiliary connection extends from the power semiconductor element and ends at a corresponding exterior connection element. The exterior connection element of the auxiliary connection penetrates the housing and is a pen-type metal preform in the interior.

Abstract: A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact portion and a base portion. The contact portion, which generally comprises a coil-type compression spring, is configured to engage and resiliently bias against a lead element of the IC device. The spring contact is disposed in a mating aperture formed in the substrate. The base portion of the spring contact is configured to secure the spring contact within the mating aperture and to establish electrical contact with the substrate. A plurality of such spring contacts and mating apertures may be arranged on the substrate in an array corresponding to the pin-out of the IC device. A clamping element secures the IC device to the substrate and biases the IC device against the spring contacts.

Abstract: A connecting element for electrically connecting a semiconductor chip and a superordinate circuit board includes an elastic metal strip that is bent forming two metal limbs with flattened limb ends, thus forming a base between the metal limbs which is suitable for contacting and providing electrical connectivity to a plurality of contact pads of a superordinate circuit board. At least one of the two limb ends is electrically connected to the contact areas of a semiconductor chip, while the other limb end is elastically supported on the top side of the semiconductor chip, thereby enabling the connecting element to be self supporting.

Abstract: A semiconductor package has a semiconductor device chip and a flexible substrate having a thermoplastic insulating resin layer. An electrode provided on the flexible substrate is connected to a predetermined electrode of the semiconductor device chip and sealed by the thermoplastic insulating resin layer. The flexible substrate is bent and provided with electrodes on the electrode-bearing and other surfaces. The flexible substrate has multi-layered wirings. Grooves or thin layer portions having a different number of wiring layers are formed at bends of the flexible substrate or regions including the bends, thereby creating a cavity at a portion in which a semiconductor device is packaged. Then, the flexible substrate is bent at predetermined positions to form a semiconductor package which does not depend on the outer dimensions of the semiconductor device chip.

Abstract: A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.

Abstract: A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact portion and a base portion. The contact portion, which generally comprises a coil-type compression spring, is configured to engage and resiliently bias against a lead element of the IC device. The spring contact is disposed in a mating aperture formed in the substrate. The base portion of the spring contact is configured to secure the spring contact within the mating aperture and to establish electrical contact with the substrate. A plurality of such spring contacts and mating apertures may be arranged on the substrate in an array corresponding to the pin-out of the IC device. A clamping element secures the IC device to the substrate and biases the IC device against the spring contacts.

Abstract: A semiconductor stacking structure has a semiconductor device. A flexible substrate is coupled to a bottom surface of the semiconductor device. The flexible substrate is folded over on at least two sides to form flap portions. The flap portions are coupled to an upper surface of the first semiconductor device and covers only a portion of the upper surface of the semiconductor device.

Abstract: Methods are provided to form wirings for tile-shaped elements, structures of wirings for tile-shaped elements, and electronic equipment, with which highly reliable electrical wirings having minute wiring patterns can be formed. In wiring forming method for a tile-shaped element, which is used, when a circuit device is formed by connecting a tile-shaped element having at least an electrode and a tile configuration to a final substrate having at least an electrode, to form an electrical wiring that electrically connects the electrode of the tile-shaped element to the electrode of the final substrate, liquid material including electro conductive material is applied to at least a part of a wiring region that is a region where the electrical wiring is formed on at least one of surfaces of the final substrate and the tile-shaped element.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, then electrically connecting a conductive trace that includes a pillar and a routing line to the pad, and then press-fitting the pillar into an opening in a ground plane, thereby electrically connecting the ground plane and the pad.

Abstract: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first surface of the support structure with the microelectronic component so that the support structure overlies the surface of the component with the posts extending away from the component and electrically connecting the posts to the contacts of the microelectronic component.

Abstract: In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.