Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. Also provided is a second interposer substrate including a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method includes connecting a passive electrical device to at least one of the first and second interposer substrates. The first interposer substrate is joined to the second interposer substrate such that the passive electrical device is provided between the first and second interposer substrates and the wiring plane is provided as an interface wiring plane between the first and second bulk materials.

Abstract: A circuit board structure includes a substrate, a first build-up structure layer, first and second external circuit layers, at least one first conductive via, and second conductive vias. The first build-up structure layer is disposed on a first circuit layer of the substrate. The first external circuit layer is disposed on the first build-up structure layer. The second external circuit layer is disposed on a second circuit layer and a portion of a third dielectric layer of the substrate. The first conductive via is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias surround the first conductive via, and the first external circuit layer, the second conductive vias, the first circuit layer, the outer conductive layer, and the second external circuit layer define a first ground path. The first ground path surrounds the signal path.

Abstract: A through electrode substrate includes a substrate provided with a through hole, a through electrode positioned in the through hole, and a first wiring structure including at least a first wiring layer positioned on a first surface of the substrate, and a second wiring layer positioned on the first wiring layer. The first wiring layer and the second wiring layer respectively have an insulation layer and an electroconductive layer. A first insulation layer of the first wiring layer includes at least an organic layer. At least one wiring layer of the first wiring structure includes an inorganic layer having insulation properties, the inorganic layer being positioned to a first side of the organic layer of the first insulation layer of the first wiring layer.

Abstract: A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.

Abstract: A printed circuit board (PCB), comprising a first layer, the first layer comprising a first dielectric material substantially exclusively. The PCB also comprises a second layer, the second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to first region. The first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg). The second dielectric material has a second dielectric constant, a second CTE and a second Tg. The first dielectric constant is greater than the second dielectric constant. The first CTE is substantially equal to the second CTE; and the first Tg and the second Tg are greater than 150° C.

Abstract: In one example, a semiconductor device comprises a substrate comprising a top side and a bottom side, a dielectric structure, and a conductive structure, wherein the conductive structure comprises a first terminal exposed from the dielectric structure, an electronic component over the top side of the substrate, and an encapsulant over the top side of the substrate and covering a lateral side of the electronic component. The dielectric structure comprises a first pattern base and first pattern wall that extends from the first pattern base and is adjacent to the first terminal, and the first terminal is bounded by the first pattern wall. Other examples and related methods are also disclosed herein.

Abstract: A safety system for a needle probe card for test machines for high-voltage and high-current testing of power semiconductor electronic devices is provided. The needle probe card has a plurality of needles adapted to be placed in contact with a device under test (DUT), each needle being configured to allow a flow of electric current. The safety system has a control unit capable of determining the electric current flowing in every single needle, and a plurality of switching devices configured to selectively interrupt the electric current flowing in the needles. At least one switching device is associated with each needle of the needle probe card. The control unit is configured to drive every single switching device to selectively interrupt the flow of electric current in a corresponding needle.

Abstract: A die package structure and a method for fabricating the same are provided. The method includes: fixing a first die on a package base; aligning first hollow pads of a flexible printed circuit board with first pads of the first die, and fixing the flexible printed circuit board; soldering the first hollow pads to the first pads; fixing a second die on the flexible printed circuit board to overlap with the first die; folding the flexible printed circuit board, such that second hollow pads of the flexible printed circuit board are aligned with second pads of the second die, and signal test pads of the flexible printed circuit board are exposed; fixing the flexible printed circuit board on the second die; soldering the second hollow pads to the second pads; soldering metal wires to the signal test soldering pads; and soldering package pins to the metal wires.

Abstract: A semiconductor device assembly is provided. The assembly includes a first package element and a second package element disposed over the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface-mounted to the first package element and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad. The first height is about equal to a sum of the solder joint thickness and the second height.

Abstract: A package structure is provided. The package structure includes a first redistribution structure and an interposer over the first redistribution structure. The interposer includes a through via electrically connected to the first redistribution structure and a conductive pillar over the through via. The package structure also includes a first molding compound layer surrounding the interposer. The package structure further includes a second redistribution structure over the first molding compound layer and electrically connected to the conductive pillar. The package structure also includes a semiconductor die over and electrically connected to the second redistribution structure.

Abstract: An electronic apparatus includes: a hard substrate having a first surface with a first wiring layer terminal, a second surface positioned on a back side of the first surface, and an end surface having a second wiring layer terminal and being continuous with the first surface and the second surface; and a flexible substrate having a third surface with a third wiring layer terminal and opposing the first surface of the hard substrate, and a fourth surface having a fourth wiring layer terminal and positioned on a back side of the third surface. The first wiring layer terminal and the fourth wiring layer terminal are electrically connected by solder. The second wiring layer terminal and the third wiring layer terminal are electrically connected by solder.

Abstract: An electronic package comprises an integrated circuit (IC) configured to receive a power input signal and to deliver a regulated power output signal. A multilayer electrical routing structure is attached to the IC and is configured to couple the electronic package to an external circuit. The multilayer routing structure has one or more electrical conductors on each of at least two layers which are configured to route the power input signal from the external circuit to the IC and to route the regulated power output signal from the IC to the external circuit. The one or more electrical conductors form an integrated inductive device having a respective portion disposed on each of the at least two layers and the power output signal is coupled to the external circuit through the integrated inductive device.

Abstract: A stacked semiconductor device having hybrid metallic structures and associated systems and methods are disclosed herein. The stacked semiconductor device can include a first semiconductor die and a second semiconductor die. The first semiconductor die can include a top surface, a first bond site at the top surface and a second bond site at the first surface spaced apart from the first bond site. The second semiconductor die can include a lower surface facing the top surface of the first semiconductor die, a third bond site at the lower surface, and a fourth bond site at the lower surface. The third bond site includes a conductive structure bonded to the first bond site by a metal-metal bond. The fourth bond site at the lower surface includes a solder ball bonded to the second bond site.

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

Abstract: A power device assembly includes a heat-generating device, one or more porous bonding layers, and one or more cap layers. The one or more porous bonding layers are formed on a surface of the heat-generating device and define a plurality of embedded vapor channels. The one or more cap layers are engaged with a porous bonding layer of the one or more porous bonding layers opposite the heat-generating device. The one or more cap layer comprise a plurality of liquid feed channels for feeding cooling fluid to the heat-generating device via the porous bonding layer.

Abstract: A semiconductor package structure includes first via structures formed through a core substrate. The structure also includes an interposer embedded in the core substrate between the first via structures. The interposer includes second via structures formed through an interposer substrate. The structure also includes a first redistribution layer structure formed over the core substrate. The structure also includes a second redistribution layer structure formed under the core substrate. The structure also includes a first encapsulating layer formed between a sidewall of the interposer and a sidewall of the core substrate.

Abstract: A wiring board according to the present disclosure includes a core insulating layer, a first laminated body located on an upper surface of the core insulating layer, and a second laminated body located on a lower surface of the core insulating layer. Each of the first laminated body and the second laminated body has a structure in which at least four electrical conductor layers and at least three build-up insulating layers are alternately located. The electrical conductor layers include two types, that are a first electrical conductor layer and a second electrical conductor layer. In the electrical conductor layers in the first laminated body, at least a first outermost layer and a first innermost layer are the first electrical conductor layers, and a first intermediate layer located farther from the core insulating layer than the first innermost layer includes at least two or more of the second electrical conductor layers.

Abstract: A transistor package having four terminals includes a semiconductor transistor chip and a semiconductor diode chip. The semiconductor transistor chip includes a control electrode and a first load electrode on a first surface and a second load electrode on a second surface opposite the first surface. The semiconductor diode chip includes a first diode electrode on a first surface and a second diode electrode on a second surface opposite the first surface. The transistor package includes a first terminal electrically connected to the control electrode, a second terminal electrically connected to the first diode electrode, a third terminal electrically connected to the first load electrode and a fourth terminal electrically connected to the second load electrode. At least the first terminal, the second terminal and the third terminal protrude from one side of transistor package. The first terminal is arranged between the second terminal and the third terminal.

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one (ALO) second level on top of or above the second metal layer; performing a lithography step on the second level; forming ALO third level on top of or above the ALO second level; performing processing steps to form first memory cells within the ALO second level and second memory cells within the ALO third level, first memory cells include ALO second transistor, second memory cells include ALO third transistor, first metal layer thickness is at least 50% greater than the second metal layer thickness, ALO first transistor controls power delivery to ALO second transistor; then dicing using a laser system.

Abstract: A semiconductor package includes a package substrate, an interposer, a semiconductor chip between the package substrate and the interposer, a plurality of conductive connectors between the package substrate and the interposer, and a capacitor stack structure between the package substrate and the interposer, he capacitor stack structure including a first capacitor connected to the package substrate, and a second capacitor connected to the interposer.

Abstract: According to one embodiment, a sensor includes a first sensor part. The first sensor part includes a first electrode, a first counter electrode, and a first intermediate layer located between the first electrode and the first counter electrode. The first counter electrode includes a first electrode side surface. The first electrode side surface crosses a first cross direction. The first cross direction crosses a first direction from the first electrode toward the first counter electrode. The first intermediate layer includes a first intermediate layer side surface. The first intermediate layer side surface crosses the first cross direction. The first intermediate layer side surface is recessed when referenced to the first electrode side surface.

Abstract: Memory devices are disclosed. A memory device may include a first row of power supply pads and a first row of input/output (DQ) pads. The memory device may further include a row of vias, wherein the first row of DQ pads is positioned at least partially between the row of vias and the first row of power supply pads. The memory device may also include a number of conductors, wherein each via of the row of vias is coupled, via an associated conductor of the number of conductors, to either a power supply pad of the first row of power supply pads or a DQ pad of the first row of DQ pads. Methods of forming an interface region of a memory device, and electronic systems are also disclosed.

Abstract: A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.

Abstract: A semiconductor device has a substrate and a plurality of bond wires is disposed in a pattern across on the substrate. The pattern of bond wires can be a plurality of rows of bond wires. A plurality of electrical components is disposed over the substrate as an SIP module. An encapsulant is deposited over the substrate, electrical components, and bond wire. An opening is formed in the encapsulant extending to the bond wire. The opening can be a trench extending across the bond wires disposed on the substrate, or a plurality of openings individually exposing each of a plurality of bond wires. A conductive material is disposed in the opening. A shielding layer is formed over the encapsulant and in contact with the conductive material. The shielding layer, conductive material, and bond wires reduce the effects of EMI, RFI, and other inter-device interference.

Abstract: An LED device includes a substrate, a conductive layer, an LED chip, and a discharge element. The substrate has upper and lower surfaces and four edges interconnected to one another and surrounding the upper surface. The conductive layer is formed on the upper surface, and has first and second regions electrically separated by a trench. The trench has a first segment inclined relative to each edge of the substrate by a predetermined angle ranging between 0 and 90 degrees, and a second segment connected to the first segment. The LED chip is disposed across the first segment, and the discharge element is disposed across the second segment, both interconnecting the first and second regions.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

Abstract: The present disclosure relates to an interposer. The interposer includes: a support body formed of a ceramic material, a connection electrode configured to the top surface and bottom surface of the support body, and a shielding member disposed at an outer surface of the support body. At least a part of the support body is disposed along the edge of a substrate, and electrically connects the substrate and a substrate. The interposer is formed of a ceramic material and thus make it possible to implement a fine pattern, to improve dimensional stability by preventing the bending deformation of ceramic green sheets, and to raise the reliability of signal transmission. Therefore, the interposer can contribute to implementing high performance of an electronic device and reducing the size of the electronic device.

Abstract: An electronic package is provided. The electronic package includes a power regulating component, an electronic component, and a circuit structure. The circuit structure separates the power regulating component and the electronic component. The circuit structure is configured to provide a first power to the power regulating component. The power regulating component is configured to provide a second power to the electronic component through the circuit structure.

Abstract: A packaging substrate can include a first surface and a second opposing surface, the first surface including a first mounting region of a first electronic module region and the second opposing surface including a first electrical contacts region of the first electronic module region. The packaging substrate can include a saw street region with at least a portion that surrounds the first electronic module region, and a saw street feature formed on the second opposing surface within at least a portion of the saw street region, the saw street feature being a solder mask layer over a metal layer.

Abstract: Described is an apparatus comprising a semiconductor interconnect substrate and an interface. The semiconductor interconnect substrate may be electrically coupled to one or more components mounted thereon. The interface may be operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip disposed over the package substrate, and an integrated device located below and bonded to the lower surface of the semiconductor chip. The semiconductor chip has a lower surface facing the package substrate and is electrically connected to the package substrate through conductive structures. The integrated device is laterally surrounded by the conductive structures, and the integrated device and the conductive structures are located within boundaries of the semiconductor chip when viewed in a direction perpendicular to the lower surface of the semiconductor chip.

Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.

Abstract: Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a carrier, an element, and a first electronic component. The element is disposed on the carrier. The first electronic component is disposed above the element. The element is configured to adjust a first bandwidth of a first signal transmitted from the first electronic component.

Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

Abstract: A semiconductor module circuit structure, including an insulating circuit substrate having an insulating plate, and a circuit pattern formed on a top face of the insulating plate, and a semiconductor element disposed on a top face of the circuit pattern. The circuit pattern includes a first straight part extending in a first direction, a second straight part extending in a second direction different from the first direction, and a corner part connecting the first and second straight parts. A wiring member is formed on a top surface of the first straight part along the first direction, the wiring member being formed off-center at the first straight part to be closer to an outer periphery of the circuit pattern.

Abstract: An electronic device is provided. The electronic device includes a first carrier having a first surface, an interposer disposed over the first surface of the first carrier, wherein the interposer has a first thickness and a second thickness in a direction substantially perpendicular to the first surface of the first carrier; and a plurality of electrical connections between the first carrier and the interposer and configured to compensate a difference between the first thickness and the second thickness of the interposer.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

Abstract: A multi-chip isolation (ISO) device package includes a leadframe including leads, an interposer substrate including a top copper layer and a bottom metal layer, with a dielectric layer in-between. A first IC die and a second IC die include circuitry including a transmitter or a receiver, and first and second bond pads are both attached top side up in the package. A laminate transformer is attached to the top copper layer positioned lateral to the IC die. Bondwires wirebond the first bond pads to first pads on the laminate transformer and to a first group of the leads or the lead terminals, and bondwires wirebond the second bond pads to second pads on the laminate transformer and to a second group of the leads or the lead terminals. A mold compound provides encapsulation.

Abstract: Provided is a small-sized circuit board fixing structure capable of enabling a circuit board on a base to be easily replaced. A circuit board fixing structure configured to fix a circuit board onto a surface of a base includes a wire pattern formed on a surface of the circuit board, a first through hole penetrating from a front surface to a rear surface of the circuit board, a second through hole penetrating from a front surface to a rear surface of the base so as to communicate with the first through hole, an electrode penetratively inserted into the second through hole, and a fixing member engaged with the electrode mounted on the surface of the circuit board and configured to fix the circuit board to the base, in which when the fixing member and the electrode are engaged, the wire pattern and the electrode are electrically connected through the fixing member.

Abstract: In various embodiments, a passive electronic component is disclosed. The passive electronic component can have a first surface and a second surface opposite the first surface. The passive electronic component can include a nonconductive material and a capacitor embedded within the nonconductive material. The capacitor can have a first electrode, a second electrode, and a dielectric material disposed between the first and second electrodes. The first electrode can comprise a first conductive layer and a plurality of conductive fibers extending from and electrically connected to the first conductive layer. A first conductive via can extend through the passive electronic component from the first surface to the second surface, with the first conductive via electrically connected to the first electrode.

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

Abstract: A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.

Abstract: A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall, and a second annular retaining wall. The conductive through hole penetrates through the third dielectric layer, a second dielectric layer, and the fourth dielectric layer. The conductive through hole is electrically connected to the first external circuit layer and the second external circuit layer. The first annular retaining wall is disposed in the third dielectric layer, surrounds the conductive through hole, and is electrically connected to the first external circuit layer and the first inner circuit layer. The second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive through hole, and connects to the second external circuit layer and the second inner circuit layer electrically.

Abstract: A wiring design method and a wiring structure for a package substrate in a flip chip, and a flip chip. The wiring design method includes: arranging bump pads in an array of rows and columns, wherein the bump pads are configured to bond with conductive bumps on a flip chip die, and the bump pads comprise signal pads and non-signal pads; providing the non-signal pad with a via hole; and using a layer of wiring to lead a subset of the signal pads out of an orthographic projection region of the flip chip die on the package substrate, wherein the subset of the signal pads is configured to carry all functional signals required by design specifications of the flip chip die for the array of the bump pads.

Abstract: In a described example, an apparatus includes: a semiconductor die having a device side surface; bond pads on the semiconductor die on the device side surface; post connects having a proximate end on the bond pads and extending from the bond pads to a distal end, the diameter of the post connects at the proximate end being the same as the diameter of the post connects at the distal end; polyimide material covering sides of the post connects and covering at least a portion of the bond pads; and solder bumps on the distal end of the post connects.

Abstract: A composite capacitor that includes a plurality of capacitors and an insulating section. The plurality of capacitors are stacked on each other. The insulating section covers peripheral surfaces of the plurality of capacitors about a central axis of the plurality of capacitors, the stacking direction of the plurality of capacitors being a direction of the central axis. Each of the plurality of capacitors includes a support electrode layer, plural columnar conductors, a dielectric layer, and a counter electrode layer. Each of the plural columnar conductors has a nano-size outer diameter. The plurality of capacitors include a first capacitor and a second capacitor connected in parallel with the first capacitor.

Abstract: A soldering structure configured for preventing solder overflow during soldering and a power module, may include a component to be soldered; and a metal layer having a bonding area, to which the component to be soldered is bonded by solder, and a groove portion formed around the bonding area.