For Integrated Circuit Devices, E.g., Power Bus, Number Of Leads (epo) Patents (Class 257/E23.079)
  • Patent number: 10636780
    Abstract: Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical conductive vias in the package by depositing conductive traces on multiple wafers or panes, then laminating these substrates into a stack, thereby embedding the conductive traces. The laminated stack is sliced to dimensions of an interposer or electronic package. A side of the sliced stack is then used as the top of the interposer or package, rendering some of the horizontally laid traces into vertical conductive vias. The interposer or package can be finished or developed by adding redistribution layers on the top and bottom surfaces, and active and passive components. Electronic components can also be embedded in the laminated stack. Some of the stack layers can be active dies, such as memory controllers, memory storage arrays, and processors, to form a memory subsystem or self-contained computing device.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: April 28, 2020
    Assignee: Invensas Corporation
    Inventor: Nader Gamini
  • Patent number: 10496778
    Abstract: A method for increasing the decoupling capacitance in a microelectronic circuit. The method comprises producing a circuit design of the microelectronic circuit, analyzing the produced circuit design, and subsequently filling gaps in the circuit design by cells with decoupling capacitor.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 3, 2019
    Assignee: TDK—Micronas GmbH
    Inventors: Nathalie Schwarz, Jens Mayer
  • Patent number: 10492309
    Abstract: A printed circuit board includes a circuit substrate and a plurality of buffering circuits. The circuit substrate includes a substrate layer, and first and second circuit layers formed on either side of the substrate layer. The first circuit layer comprises a plurality of first conductive circuits. The second circuit layer comprises a plurality of second conductive circuits. A line width of each of the plurality of first conductive circuits is greater than a line width of each of the plurality of second conductive circuits. The plurality of buffering circuits electrically connect the first circuit layer to the second circuit layer and a line width of each of the plurality of buffering circuits is greater than the line width of each of the plurality of second conductive circuits.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: November 26, 2019
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Rih-Sin Jian, Xiao-Wei Kang, LI Yang
  • Patent number: 10485105
    Abstract: A substrate including a through hole only in one of a direction from a top surface to a bottom surface of the substrate or a direction from a bottom surface to a top surface of the substrate, a protruding portion of a metal layer protruding toward the through hole being removed, and a plating layer on an inner surface of the substrate on at least the through hole.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Sam Lee, Won Joong Kim
  • Patent number: 10470346
    Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component with contact terminals and conducting lines in a first wiring layer. There is also a dielectric between the component and the first wiring layer such that the component is embedded in the dielectric. Contact elements provide electrical connection between at least some of the contact terminals and at least some of the conducting lines. The electronic module also comprises a second wiring layer inside the dielectric. The second wiring layer comprises a conducting pattern that is at least partly located between the component and the first wiring layer and provides EMI protection between the component and the conducting lines.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: November 5, 2019
    Assignee: GE Embedded Electronics Oy
    Inventor: Risto Tuominen
  • Patent number: 10361158
    Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10331828
    Abstract: Systems and methods for a cloud computing engineering application that can provide new interaction, visualization and interaction techniques along with advertising messaging and business social networking are disclosed.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: June 25, 2019
    Assignee: Xendee Corporation
    Inventors: Adib Nasle, Scott K. Mitchell
  • Patent number: 10163868
    Abstract: A semiconductor device includes an insulating substrate having an insulating plate and a circuit plate; a semiconductor chip having a front surface provided with a gate electrode and a source electrode, and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate, and including a first metal layer and a second metal layer; a first conductive post having two ends electrically and mechanically connected to the gate electrode and the first metal layer; a second conductive post having two ends electrically and mechanically connected to the source electrode and the second metal layer; and a circuit impedance reducing element electrically connected between the gate electrode and the source electrode through the first conductive post and the second conductive post.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: December 25, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masafumi Horio, Yoshinari Ikeda, Hideyo Nakamura, Hayato Nakano
  • Patent number: 10162234
    Abstract: The present invention relates to a display panel and a display module, the display panel comprises a display region and a non-display region, and boundaries between the display region and the non-display region comprise at least one arc structure. The technical effects of the present invention are that it is beneficial to design a display module with an arc and narrow frame, which greatly reduces the range of the frame, increases the area that can be displayed, it is more consistent with the natural display contour of the human eye's physiology, with more comfortable, natural and fantastic display effect.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: December 25, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenqi Li, Wei Qin
  • Patent number: 9922959
    Abstract: A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: March 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Seok-Bo Shim, Seok-Cheol Yoon
  • Patent number: 9806733
    Abstract: An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ld.
    Inventor: Martin Kinyua
  • Patent number: 9761521
    Abstract: Various embodiments provide for flexible and robust power grid connectivity in a server on a chip environment. The power grid has three parallel conductors, (e.g., wires) which represent two power polarities. The outside two wires can be of a first polarity (e.g. Vdd), while the middle wire is of a second polarity (e.g., Vss). The polarities of the wires can also be switched, as long as the two outside wires have the same polarity, while the inside wire has a different polarity. Power pins from modules adjacent to the set of three wires make connections to the nearest wire of the matching polarity. In this way, every power pin on the modules can be connected to the power grid without need for special alignment or custom power pins.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: September 12, 2017
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Arun Jangity, Srini Gbalakrishnan, Tai Chong
  • Patent number: 9698111
    Abstract: A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 4, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Tsuguto Maruko
  • Patent number: 9557372
    Abstract: In one embodiment, an automated test equipment (ATE) system includes a tester having a tester electronics module, an application specific electronics module, and a tester-to-device under test (DUT) interface mount. The tester electronics module has a first electronics interface configured to electrically connect to a tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module has a second electronics interface and a third electronics interface. The second and third electronics interfaces are configured to electrically connect to the tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module is configured to communicate with the tester electronics module via the second electronics interface, and with at least one DUT via the third electronics interface.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: January 31, 2017
    Assignee: ADVANTEST CORPORATION
    Inventors: Edmundo De La Puente, Ken Hanh Duc Lai
  • Patent number: 9418873
    Abstract: A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.
    Type: Grant
    Filed: August 24, 2014
    Date of Patent: August 16, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shailesh Kumar, Vikas Garg, Sumit Varshney, Chetan Verma
  • Patent number: 9035455
    Abstract: A semiconductor device includes a semiconductor chip, a wiring formed on the semiconductor chip, a passivation film coating the wiring and having an opening for partially exposing the wiring from the passivation film an interposing film formed on a portion of the wiring and facing the opening, and a post bump raisedly formed on the interposing film and with a peripheral edge portion thereof protruding away from the opening more than a peripheral edge of the interposing film in a direction parallel to a surface of the passivation film.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: May 19, 2015
    Assignee: ROHM CO., LTD.
    Inventor: Katsumi Sameshima
  • Patent number: 9029977
    Abstract: The power conversion apparatus includes semiconductor modules and a circuit board on which a control circuit is formed. Each semiconductor module includes signal terminals electrically connected to the circuit board. The signal terminals of each semiconductor module are arranged in a line so as to form a terminal row along a first direction. The semiconductor modules are grouped into upper arm semiconductor modules and lower arm semiconductor modules each connected to a corresponding one of the upper arm semiconductor module. Upper arm terminal rows as the terminal rows of the upper arm semiconductor modules and lower arm terminal rows as the terminal rows of the lower arm semiconductor modules are arranged in a staggered manner along a second direction perpendicular to the first direction and to a third direction in which the signal terminals of the semiconductor modules project, the first, second and third directions being perpendicular to one another.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 12, 2015
    Assignee: Denso Corporation
    Inventor: Hiroshi Inamura
  • Patent number: 9029903
    Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 9000583
    Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Wael Zohni, Richard Dewitt Crisp
  • Patent number: 8987884
    Abstract: A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8963313
    Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 24, 2015
    Assignee: Raytheon Company
    Inventors: Sankerlingam Rajendran, Monte R. Sanchez, Susan M. Eshelman, Douglas R. Gentry, Thomas A. Hanft
  • Patent number: 8952472
    Abstract: The present invention provides a semiconductor device capable of changing the setting of the internal operation mode without increasing the number of terminals of the semiconductor device. The semiconductor device includes a transmitting cell, a receiving cell, a semiconductor chip including a transmitting antenna and a receiving antenna, and a conductor. The transmitting antenna is connected to the transmitting cell, and the receiving antenna is connected to the receiving cell. The conductor is provided close to the transmitting antenna and the receiving antenna. Close proximity wireless communication is used between the transmitting cell and the receiving cell.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: February 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Daisaku Kitagawa, Takeshi Nakayama, Masahiro Ishii
  • Patent number: 8952537
    Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 10, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Feng Chan, Mu-Hsuan Chan, Chun-Tang Lin, Yi-Che Lai
  • Patent number: 8941241
    Abstract: A semiconductor device includes at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines. First contact pads may be coupled to the respective ends of the conductive lines of two of the 4 conductive line groups in a first direction, and second contact pads may be coupled to the respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dae Sung Eom
  • Patent number: 8928153
    Abstract: A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: January 6, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Richard Dewitt Crisp, Wael Zohni
  • Patent number: 8884436
    Abstract: A semiconductor device includes first pads having centers offset in a first direction, wherein the first pads are arranged in a second direction crossing the first direction; second pads separated in the first direction from the first pads and arranged in the second direction, wherein centers of the second pads are offset in the first direction; first gate lines coupled to the first pads, respectively; and second gate lines coupled to the second pads, respectively.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 11, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyun Jo Yang
  • Patent number: 8885383
    Abstract: A flash memory is disclosed. A core array stores data. A peripheral circuit accesses the data stored in the core array to generate read data. A off-chip driver (OCD) processes the read data to generate output data. An interconnect structure is electrically connected to the core array, the peripheral circuit, and the OCD and includes three conductive layers. The conductive layers are electrically connected to each other. An uppermost conductive layer is formed over the interconnect structure, electrically connected to the interconnect structure, and includes a first power pad and first power tracks. The first power pad is electrically connected to a power pin via a first bonding wire to receive an operation voltage. The first power tracks are electrically connected between the first power pad and the interconnect structure to transmit the operation voltage to at least one of the core array, the peripheral circuit and the OCD.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: November 11, 2014
    Assignee: Winbond Electronics Corp.
    Inventors: Jun-Lin Yeh, Ting-Kuo Yen
  • Patent number: 8876225
    Abstract: The invention achieves a further downsizing of an actuator control unit. The actuator control unit has a control circuit controlling an actuator, and a bus bar electrically connected to the control circuit and arranged such as to be partially embedded in an inner portion of a resin case and be partially exposed to an outer portion of the resin case. It is preferable to have a projection portion extending in a wiring direction of the bus bar between two bus bars wired adjacently, having a greater height than an embedded plane of the bus bar in the resin case, and made of an insulating material.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: November 4, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Daisuke Yasukawa, Hirofumi Watanabe
  • Patent number: 8860204
    Abstract: There is provided a semiconductor device including: plural bit cells each including the same circuit; plural electrodes supplied with power from outside, wherein each of the respective plural electrodes is mounted above the same circuit within the plural bit cells. Further, there is provided a semiconductor package including: the semiconductor device; a substrate mounted with the semiconductor device; an external input terminal formed on the substrate; an external output terminal formed on the substrate; an input wiring pattern connecting the semiconductor device mounted above the substrate and the external input terminal; an output wiring pattern connecting the semiconductor device mounted above the substrate and the external output terminal; and plural power supply lines, arranged without contact with each other on the same face of the substrate, and connecting the plural electrodes mounted to the semiconductor device to the corresponding electrode from the plural external power input electrodes.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: October 14, 2014
    Assignee: OKI Semiconductor Co., Ltd.
    Inventor: Koji Higuchi
  • Patent number: 8841766
    Abstract: Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chun-Chieh Wang, Chung-Shi Liu
  • Patent number: 8835218
    Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: September 16, 2014
    Assignee: Aprolase Development Co., LLC
    Inventors: Keith Gann, W. Eric Boyd
  • Patent number: 8810022
    Abstract: A semiconductor package includes a plurality of electrical connectors, a semiconductor die having core logic, at least two pairs of core logic input-power and output-power pads, and a plurality of input/output signal pads that carry signals to and from the core logic. Each pad of the semiconductor die has an electrical connector of the plurality of electrical connectors extending therefrom. The semiconductor package also includes a package substrate having at least two pairs of input-power and output-power contact pads, a plurality of input/output signal contact pads, a first metal redistribution layer, and a second metal redistribution layer. The first metal redistribution layer provides a first electrical potential to each of the input-power contact pads, and the second metal redistribution layer provides a second electrical potential to each of the output-power contact pads. Each contact pad has an electrical connector of the plurality of electrical connectors extending therefrom.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: August 19, 2014
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8810007
    Abstract: A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: August 19, 2014
    Assignees: Shinko Electric Industries Co., Ltd., Taiyo Yuden Co., Ltd.
    Inventors: Akihito Takano, Masahiro Sunohara, Hideaki Sakaguchi, Mitsutoshi Higashi, Kenichi Ota, Yuichi Sasajima
  • Patent number: 8791560
    Abstract: A GaN die having a plurality of parallel alternating and closely spaced source and drain strips is contacted by parallel coplanar comb-shaped fingers of source and drain pads. A plurality of enlarged area coplanar spaced gate pads having respective fingers contacting the gate contact of the die. The pads may be elements of a lead frame, or conductive areas on an insulation substrate. Other semiconductor die can be mounted on the pads and connected in predetermined circuit arrangements with the GaN die.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: July 29, 2014
    Assignee: International Rectifier Corporation
    Inventors: Kunzhong Hu, Chuan Cheah
  • Patent number: 8786071
    Abstract: A pad for a line which supplies an electric power potential is disposed on a semiconductor integrated circuit and a pad which is not electrically connected to any other electric circuit is disposed on a semiconductor integrated circuit board, and the two pads are connected through a bonding wire. An LC resonant circuit is configured with ease using a floating capacitance C of the pad which is in an electrically open state and which is disposed in a vacant region and an inductance value L of the bonding wire which is disposed in a three-dimensional manner. High-frequency noise is filtered and high-density implementation is realized.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshitaka Kawase
  • Patent number: 8786094
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Min Fu, Wen-Hao Chen, Dian-Hau Chen
  • Patent number: 8779574
    Abstract: A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a plurality of semiconductor components and a current trace line that is coupled to a first semiconductor component. Further, the semiconductor die comprises a current routing line that is coupled with the current trace line. The current routing line includes a plurality of non-metallic slots that extend through the current routing line.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: July 15, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: John R. Agness, Mingying Gu
  • Patent number: 8766427
    Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 1, 2014
    Assignee: NXP, B.V.
    Inventor: Marnix Bernard Willemsen
  • Patent number: 8749034
    Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Chuan Cheah
  • Patent number: 8741742
    Abstract: The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: June 3, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Patent number: 8716855
    Abstract: An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-An Chi, Mark Shane Peng, Yun-Han Lee
  • Patent number: 8704364
    Abstract: An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 22, 2014
    Assignee: Xilinx, Inc.
    Inventor: Bahareh Banijamali
  • Patent number: 8692369
    Abstract: There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: April 8, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kikuo Utsuno
  • Patent number: 8680690
    Abstract: In one embodiment, a device includes a first IC having a differential signal driver and a first isolation circuit configured to provide differential signals transmitted by the differential signal driver to a first pair of bond pads of the first IC. First and second bond wires are configured to provide differential signals from the first pair of bond pads to a second pair of bond pad included in a second IC. The second IC includes a second isolation circuit configured to provide differential signals from the second pair of bond pads to a differential receiver circuit of the second IC. The bond wires are specifically arranged such that a distance between the first and second bond wires varies by at least 10% as measured at two points along a length of the first bond wire.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: March 25, 2014
    Assignee: NXP B.V.
    Inventors: Peter Steeneken, Rameswor Shrestha, Martijn Bredius
  • Patent number: 8674501
    Abstract: A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventor: Yasuhide Sosogi
  • Patent number: 8659144
    Abstract: A semiconductor package includes a plurality of electrical connectors, a semiconductor die having core logic, at least two pairs of core logic input-power and output-power pads, and a plurality of input/output signal pads that carry signals to and from the core logic. Each pad of the semiconductor die has an electrical connector of the plurality of electrical connectors extending therefrom. The semiconductor package also includes a package substrate having at least two pairs of input-power and output-power contact pads, a plurality of input/output signal contact pads, a first metal redistribution layer, and a second metal redistribution layer. The first metal redistribution layer provides a first electrical potential to each of the input-power contact pads, and the second metal redistribution layer provides a second electrical potential to each of the output-power contact pads. Each contact pad has an electrical connector of the plurality of electrical connectors extending therefrom.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: February 25, 2014
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8648477
    Abstract: A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: February 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-han Kim
  • Publication number: 20140035151
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Hidekazu Yoshida, Jongwook Kye, Qi Xiang, Mahbub Rashed
  • Patent number: 8643173
    Abstract: Jet-impingement, two-phase cooling apparatuses and power electronics modules having a target surface with single- and two-phase surface enhancement features are disclosed. In one embodiment, a cooling apparatus includes a jet plate surface and a target layer. The jet plate surface includes a jet orifice having a jet orifice geometry, wherein the jet orifice is configured to generate an impingement jet of a coolant fluid. The target layer has a target surface, single-phase surface enhancement features, and two-phase surface enhancement features. The target surface is configured to receive the impingement jet, and the single-phase surface enhancement features and the two-phase enhancement features are arranged on the target surface according to the jet orifice geometry.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: February 4, 2014
    Assignees: Toyota Motor Engineering & Manufacturing North America, Inc., Purdue Research Foundation
    Inventors: Matthew Joseph Rau, Ercan Mehmet Dede, Shailesh N. Joshi, Suresh V. Garimella
  • Patent number: 8637972
    Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: January 28, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Chih-Chin Liao, Ning Ye, Cheemen Yu, Jack Chang Chien, Hem Takiar