Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a conductive adhesive layer over the first pad. The conductive adhesive layer is in direct contact with the first pad. The chip package structure includes a nickel layer over the conductive adhesive layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip. The conductive bump includes gold.

Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

Abstract: A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.

Abstract: A semiconductor device includes a first integrated circuit and a second integrated circuit disposed on a semiconductor substrate and spaced apart from each other. A wiring structure is disposed on the semiconductor substrate and electrically connects the first integrated circuit and the second integrated circuit. A first TSV area and a second TSV area are disposed between the first integrated circuit and the second integrated circuit The first and second TSV areas include a plurality of first and second TSV structures penetrating through the semiconductor substrate, respectively. The wiring structure passes between the first TSV area and the second TSV area.

Abstract: A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices. The power module further including a base plate and a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module.

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

Abstract: An antenna apparatus in a packaged electronic device includes: an antenna assembly with a conductive antenna, and an insulator; a conductive feed line extending on or in a substrate; a conductive layer with an aperture on or in the substrate between the conductive feed line and an exposed portion of the conductive antenna; and a support structure mounted to a portion of the substrate and to a portion of the antenna assembly to support the antenna assembly and to provide an air gap between the exposed portion of the conductive antenna and the aperture.

Abstract: A light emitting device including a mounting board, one or more light emitting elements, a light transmissive member, and a light reflective member. The light emitting element(s) are mounted on the mounting board, and each include an upper surface. The light transmissive member is bonded to the upper surface of each of the light emitting element(s). The light transmissive member has an upper surface and a lower surface, and allows light from the light emitting element(s) to be incident on the lower surface of the light transmissive member and to be output from the upper surface of the light transmissive member. The light reflective member covers surfaces of the light transmissive member and lateral surfaces of the light emitting element(s) and exposes the upper surface of the light transmissive member. At least a first portion of the mounting board is exposed from the light reflective member in a plan view.

Abstract: A package structure, and a RDL structure are provided. The package structure incudes a die and a RDL structure electrically connected to the die. The RDL structure includes a first redistribution layer, a second redistribution layer and a third redistribution layer. The first redistribution layer includes a first ground plate. The second redistribution layer includes a second ground plate and a signal trace. The signal trace is laterally spaced from the second ground plate. The third redistribution layer includes a third ground plate. The third redistribution layer and the first redistribution layer are disposed on opposite sides of the second redistribution layer. The signal trace is staggered with at least one of the first ground plate and the third ground plate in a direction perpendicular to a top surface of the signal trace.

Abstract: A semiconductor device includes a semiconductor package including an encapsulant body of electrically insulating encapsulant material, a semiconductor die encapsulated by the encapsulant body, and two or more leads that are each electrically connected to the semiconductor die, and an ESD protection element that is electrically connected between the two or more leads, and the ESD protection element is configured to be electrically disconnected from the two or more leads by an external stimulus applied to ESD protection element that is non-destructive to the semiconductor package.

Abstract: A bottom side interposer provides a structurally balanced chip carrier module to reduce thermal warp and increase package robustness. The bottom side interposer is attached to the bottom of a chip carrier which carries semiconductor chips on the top side of the chip carrier. The top side of the chip carrier typically includes a top side interposer between the semiconductor chips and the chip carrier. The bottom side interposer has a coefficient of thermal expansion (CTE) that is similar to the chips and top side interposer, or tailored to have a CTE intermediate to the chips and the chip carrier. Pads on the bottom side interposer may be plated or fitted with solder balls to complete the module so the module can be connected to a printed circuit board.

Abstract: An electronic device includes: a board that includes an insulating film, a wiring layer and a via provided in the insulating film, and a plurality of power source pads and a plurality of ground pads which are provided in the insulating film so as to surround a capacitor region in which a capacitor is provided and to which a plurality of bumps is coupled; and an electronic component that is mounted at the board, and is electrically coupled to the plurality of power source pads and the plurality of ground pads through the wiring layer and the via. Further, a method for supporting design of the electronic device is provided.

Abstract: A mixed pitch method of placing pads in a ball grid array (BGA) package having a BGA substrate and a plurality of connectors arranged in an array and connected via the pads to the BGA substrate. Selected pairs of the pads are placed on the BGA substrate at a distance defined by a first pitch P1. Ground pads are placed on the BGA substrate at a distance from the selected pairs of pads defined by a second pitch P2, wherein P2=M*P1 and M is greater than one. The selected pairs of the pads on the BGA substrate are also placed at a distance from other selected pairs of the pads defined by the second pitch P2.

Abstract: A light emitting device includes a substrate, a light emitting element, a driving element, and a capacitor layer. The light emitting element and the driving element are provided on the substrate. The driving element drives the light emitting element. The capacitor layer is provided in the substrate and supplies electric current to the light emitting element via the driving element.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

Abstract: An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness.

Abstract: A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

Abstract: Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.

Abstract: Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.

Abstract: A semiconductor power module including an insulating substrate having one surface and another surface, an output side terminal arranged at a one surface side of the insulating substrate, a first power supply terminal arranged at the one surface side of the insulating substrate, a second power supply terminal to which a voltage of a magnitude different from a voltage applied to the first power supply terminal is to be applied, and arranged at another surface side of the insulating substrate so as to face the first power supply terminal across the insulating substrate, a first switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the first power supply terminal, and a second switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the second power supply terminal.

Abstract: A PCB having a first surface and a second surface includes a trench extending through the PCB, a plurality of conductive traces on one or more sidewalls of the trench. The plurality of conductive traces extends through the PCB and may be arranged in pairs across from one another along at least a portion of the length of the trench. A first set of conductive contacts are arranged in a first zig-zag pattern around a perimeter of the trench. A second set of conductive contacts are arranged in a second zig-zag pattern around the perimeter of the trench. In some cases, the first and second zig-zag patterns are arranged with respect to one another around the perimeter of the trench in an alternating fashion. A chip package is also disclosed having a pin arrangement that couples to the corresponding arrangement of conductive contacts on the PCB.

Abstract: For example, an apparatus may include a Printed Circuit Board (PCB) including a Ball Grid Array (BGA) on a first side of the PCB, the BGA configured to connect a Surface Mounted Device (SMD) to the PCB; an antenna disposed on a second side of the PCB opposite to the first side, the antenna to communicate a Radio Frequency (RF) signal of the SMD; and an RF transition to transit the RF signal between the BGA and the antenna, the RF transition including a plurality of signal buried-vias; a first plurality of microvias configured to transit the RF signal between the plurality of signal buried-vias and a ball of the BGA, the first plurality of microvias are rotationally misaligned with respect to the plurality of signal buried-vias; and a second plurality of microvias configured to transit the RF signal between the plurality of signal buried-vias and the antenna.

Abstract: A package structure includes a first die, a second die, a bonding die, a gap fill structure and conductive vias. The bonding die includes a bonding dielectric layer and bonding pads. The bonding dielectric layer is bonded to a first dielectric layer of the first die and a second dielectric layer of the second die. The bonding pads are embedded in the bonding dielectric layer and electrically bonded to a first conductive pad of the first die and a second conductive pad of the second die. The gap fill structure is disposed on the first die and the second die, and laterally surrounds the bonding die. The conductive vias penetrates through the gap fill structure to electrically connect to the first die and the second die.

Abstract: A circuit pattern of a power line and a circuit pattern of a signal line are disposed in a first layer of a laminated circuit board device, a circuit pattern of the signal line to be protected is disposed in a second layer, and a circuit pattern of a power line is disposed in a third layer. The shapes of the first circuit pattern of the power line of the first layer and the second circuit pattern of the power line of the third layer are substantially matched with each other with respect to a portion of the second layer facing the circuit pattern of the signal line. The direction of the current of the first circuit pattern coincides with the direction of the current of the second circuit pattern.

Abstract: In one embodiment, an apparatus generally comprises a printed circuit board comprising a first side, a second side, and a plurality of power vias extending from the first side to the second side, the first side configured for receiving an application specific integrated circuit (ASIC), and a power delivery board mounted on the second side of the printed circuit board and comprising a power plane interconnected with power vias in the power delivery board to electrically couple voltage regulator modules and the ASIC. The voltage regulator modules are mounted on the second side of the printed circuit board.

Abstract: A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.

Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.

Abstract: An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.

Abstract: The multiplexer includes a plurality of IDT electrodes on a substrate, an insulating cover located on the substrate so as to configure one or more spaces above the plurality of IDT electrodes, an antenna terminal, transmission terminal, and reception terminal which are all located on the substrate and pass through the cover, and a reinforcing layer which is located on the cover and is made of metal. By the plurality of IDT electrodes, a transmission filter located in a signal path connecting the antenna terminal and the transmission terminal and a receiving filter located in a signal path connecting the antenna terminal and the reception terminal. The reinforcing layer includes a first area part facing the transmission filter and a second area part which faces the receiving filter and is separated from the first area part.

Abstract: An apparatus is provided that includes a die stack having a first die and a second die disposed above a substrate, and a capacitor die disposed in the die stack between the first die and the second die. The capacitor die includes a plurality of integrated circuit capacitors that are configured to be selectively coupled together to form a desired capacitor value coupled to at least one of the first die and the second die.

Abstract: A semiconductor package including a molded power delivery module arranged between a package substrate and a semiconductor chip and including a plurality of input conductive structures and a plurality of reference conductive structures, wherein the input conductive structures alternate between the plurality of reference conductive structures, wherein the input conductive structure is electrically coupled with a chip input voltage terminal and a package input voltage terminal, wherein each of the plurality of reference conductive structures are electrically coupled with a semiconductor chip reference terminal and a package reference terminal.

Abstract: The present invention provides a semiconductor device for reducing parasitic inductance. The semiconductor device of the present invention includes: a semiconductor chip, including a front surface and a hack surface, and including a source pad, a drain pad and a gate pad on the front surface; a die pad, disposed under the semiconductor chip and bonded to the hack surface of the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin, sealing the semiconductor chip, the die pad and each of the leads. At least one via for external connection is formed in the semiconductor chip to connect to the source pad, and the via for external connection is disposed on a circumferential portion of the semiconductor chip in perspective view.

Abstract: An integrated power control assembly configured as an inverter for a motor is mounted directly on an axial end of the motor. The integrated power control assembly includes one or more power plates, one or more cooling plates coaxially disposed on and thermally connected to the one or more power plates, and one or more circuit boards circumferentially disposed around the one or more power plates. An individual power plate has a power card having one or more switching semiconductor devices corresponding to individual phases of the motor. The individual power card is electrically coupled to the motor through one or more busbars. An individual circuit board is electrically coupled to an individual power card corresponding to an individual phase of the motor. The individual circuit board has a first surface electrically coupled to the one or more power plates and a second surface opposite to the first surface.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

Abstract: The power converter A1 includes a semiconductor device B1, and a substrate H on which the semiconductor device B1 is mounted, where the semiconductor device B1 includes a control chip constituting a primary control circuit, a semiconductor chip constituting a secondary power circuit, and a transmission circuit for electrically insulating the primary control circuit and the secondary power circuit and for signal transmission between the primary control circuit and the secondary power circuit. The substrate H has a conductive portion K. The power converter A1 includes a connecting terminal T1 disposed on the substrate H and electrically connected to the conductive portion K. The power converter A1 includes a conductive path D1 that is at least partially formed by the conductive portion K of the substrate H, and that electrically connects the primary control circuit and the connecting terminal T1. Such a configuration contributes to downsizing the power converter A1.

Abstract: A semiconductor package may include a semiconductor chip mounted on a package substrate, and capacitors. The capacitors may be disposed between the package substrate and the first semiconductor chip, and the capacitors may support the first semiconductor chip.

Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Abstract: A chip package module is provided. The chip package module includes a package substrate, a chip, and a conductive connector assembly. The chip having a first surface and a second surface opposite thereto is disposed on the package substrate. The first surface is divided into a first region, a second region, and a third region, and the second region is located between the first and third regions. The chip includes a flip-chip pad group disposed in the first region, a wire-bonding pad group disposed in the third region, and a signal pad group disposed in the second region. The conductive connector assembly is electrically connected between the chip and the package substrate. One of the flip-chip pad group and the wire-bonding pad group is electrically and physically connected to the conductive connector assembly, and the other one is not physically connected to the conductive connector assembly.

Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.

Abstract: A system comprises: a contactor having a first surface, a second surface, a first hole, a second hole parallel to the first hole, and a third hole parallel to the first hole; a first signal pin held in the first hole of the contactor, extending to at least the second surface of the contactor, and extending to at least the first surface of the contactor; a first short ground pin held in the second hole of the contactor, extending to at least the second surface of the contactor, and extending within the first surface of the contactor; and a ground pin held in the third hole of the contactor, extending to at least the second surface of the contactor, and extending to at least the first surface of the contactor.

Abstract: A semiconductor device includes a semiconductor chip having first, second and third pads, first and second external terminals to which a power supply potential or a reference potential is supplied, first and second wires connecting the first and second external terminals and the first and second pads, and a third wire connecting the second external terminal and the third pad. The semiconductor chip further includes a first internal wiring connected to the first and second pads, a second internal wiring connected to the third pad, and a detection circuit. The detection circuit includes: a current source for passing a current through the first and second internal wirings; first and second resistive elements connected between the current source and the first and second internal wirings; and an amplifier circuit for amplifying a relative potential difference generated between the first and second resistive elements and outputting a detection signal.

Abstract: Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical conductive vias in the package by depositing conductive traces on multiple wafers or panes, then laminating these substrates into a stack, thereby embedding the conductive traces. The laminated stack is sliced to dimensions of an interposer or electronic package. A side of the sliced stack is then used as the top of the interposer or package, rendering some of the horizontally laid traces into vertical conductive vias. The interposer or package can be finished or developed by adding redistribution layers on the top and bottom surfaces, and active and passive components. Electronic components can also be embedded in the laminated stack. Some of the stack layers can be active dies, such as memory controllers, memory storage arrays, and processors, to form a memory subsystem or self-contained computing device.

Abstract: A method for increasing the decoupling capacitance in a microelectronic circuit. The method comprises producing a circuit design of the microelectronic circuit, analyzing the produced circuit design, and subsequently filling gaps in the circuit design by cells with decoupling capacitor.

Abstract: A printed circuit board includes a circuit substrate and a plurality of buffering circuits. The circuit substrate includes a substrate layer, and first and second circuit layers formed on either side of the substrate layer. The first circuit layer comprises a plurality of first conductive circuits. The second circuit layer comprises a plurality of second conductive circuits. A line width of each of the plurality of first conductive circuits is greater than a line width of each of the plurality of second conductive circuits. The plurality of buffering circuits electrically connect the first circuit layer to the second circuit layer and a line width of each of the plurality of buffering circuits is greater than the line width of each of the plurality of second conductive circuits.

Abstract: A substrate including a through hole only in one of a direction from a top surface to a bottom surface of the substrate or a direction from a bottom surface to a top surface of the substrate, a protruding portion of a metal layer protruding toward the through hole being removed, and a plating layer on an inner surface of the substrate on at least the through hole.

Abstract: An electronic module with EMI protection is disclosed. The electronic module comprises a component with contact terminals and conducting lines in a first wiring layer. There is also a dielectric between the component and the first wiring layer such that the component is embedded in the dielectric. Contact elements provide electrical connection between at least some of the contact terminals and at least some of the conducting lines. The electronic module also comprises a second wiring layer inside the dielectric. The second wiring layer comprises a conducting pattern that is at least partly located between the component and the first wiring layer and provides EMI protection between the component and the conducting lines.

Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.