Cooling Arrangements Using Peltier Effect (epo) Patents (Class 257/E23.082)
  • Patent number: 11289756
    Abstract: An apparatus includes an anode of a cell for a battery, a cathode of the cell, an anode thermoelectric device, and a cathode thermoelectric device. The anode thermoelectric device may be operably coupled to the anode of the cell, and the anode thermoelectric device may be connected in electrical series with the anode of the cell. The cathode thermoelectric device may be operably coupled to the cathode of the cell, and the cathode thermoelectric device being connected in electrical series with the cathode of the cell. The cathode thermoelectric device and the anode thermoelectric device may operate as a heat pump system configured to remove heat from the cathode and provide heat to the anode in response to the cell being discharged, and remove heat from the anode and provide heat to the cathode in response to the cell being charged.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 29, 2022
    Assignee: The Johns Hopkins University
    Inventors: Rama Venkatasubramanian, Geza Dezsi
  • Patent number: 11258225
    Abstract: Provided is a laser oscillator including: one or more heat generating parts disposed in a housing; a piping system through which cooling water flows to the one or more heat generating parts; a water cooling type dehumidifier that dehumidifies air inside the housing using the cooling water; and an air cooling type dehumidifier that includes a Peltier element attached with a cooling fin and a radiating fin and includes a cooling water plate configured to cool the radiating fin with the cooling water, wherein the air cooling type dehumidifier starts to dehumidify the air inside the housing using the cooling fin while the cooling water is not flowing and dehumidifies the air inside the housing by cooling the radiating fin using the cooling water plate when the cooling water is flowing.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: February 22, 2022
    Assignee: Fanuc Corporation
    Inventors: Yoshiki Mihara, Akihiko Nishio
  • Patent number: 11257402
    Abstract: In one embodiment, a foldable display module includes a foldable OLED display panel; a heat conduction unit and a heat dissipation unit sequentially disposed on the OLED display panel in a direction away from a light exit side of the OLED display panel; and a plurality of semiconductor sinks located between the heat conduction unit and the heat dissipation unit, wherein the heat conduction unit is adhered to a side of the OLED display panel away from the light exit side and is configured to conduct heat from the OLED display panel; the semiconductor sinks are disposed on the heat conduction unit; the heat dissipation unit covers the semiconductor sinks and the heat conduction unit; and the semiconductor sinks are configured to absorb heat from the heat conduction unit and dissipate the heat through the heat dissipation unit, in response to a direct-current voltage applied to the semiconductor sinks.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: February 22, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yudan Shui, Xuan Luo, Zhengmao Yu, Yanping Ren
  • Patent number: 11169583
    Abstract: The present disclosure, in various aspects, describes technologies and techniques for a controller of a data storage device to mitigate temperature increases in the data storage device. In one example, the controller receives a command for a memory operation, analyzes the command to determine whether execution of the command with thermal throttling would have a negative impact on a user experience, and activates, if performing the thermal throttling would have the negative impact on the user experience, one or more thermoelectric cooler (TEC) devices while refraining from performing the thermal throttling. In another example, the controller monitors a temperature of one or more regions of the data storage device, determines whether the temperature exceeds a threshold temperature, activates one or more TEC devices to mitigate the temperature when the temperature exceeds the threshold temperature, and deactivates any activated TEC devices when the temperature no longer exceeds the threshold temperature.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: November 9, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vladimir Karalnik, Judah Gamliel Hahn
  • Patent number: 10856055
    Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a cooling system for network connections. An example system includes a networking cage assembly that receives a networking cable and a water block that circulates water. The system includes a thermal unit that includes a thermal medium. The thermal medium defines a static end that thermally engages the water block and a dynamic end opposite the static end that is disposed within the networking cage assembly. In an operational configuration in which the networking cable is received by the networking cage assembly, a portion of the dynamic end thermally engages the networking cable so as to dissipate heat from the networking cable to the thermal medium, the thermal medium conducts the heat from the dynamic end to the static end, and the static end dissipates heat from the thermal medium via thermal engagement with the water block.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 1, 2020
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Oren Weltsch, Alex Kremenetsky, Alexei Berkovich, Kfir Katz
  • Patent number: 10765042
    Abstract: An integrated capacitor and power module include a power module, an intermediate cold plate, and a capacitor module. The intermediate cold plate has a first side attached to the power module and a second side opposite the first side. The capacitor module is attached to a second side of the intermediate cold plate. The capacitor module includes a plurality of metalized film capacitor cells supported by a metal plate and a base cold plate with a layer of thermal interface material between the metal plate and the base cold plate. A fluid circulation system is operatively connected to the intermediate cold plate to circulate a fluid through the cold plate. The capacitor module includes a housing, a plurality of capacitor cells and first and second busbars. Alternating cell arrays have a P-end and an N-end that are inverted relative to each other.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: September 1, 2020
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Fan Wang, Lihua Chen, Joseph Sherman Kimmel
  • Patent number: 10580715
    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: March 3, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
  • Patent number: 10319665
    Abstract: A cooler for cooling a semiconductor module to be secured to a base, the cooler including: a cooler body that includes a refrigerant flow path surrounded by a first wall part having a first through-hole, a second wall part that is arranged facing the first wall part and that includes a connection region which is to be connected to the base at a position opposing the first through-hole, and a side wall part for connecting the periphery of the first wall part and the periphery of the second wall part; and a lid for closing off the first through-hole.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Ryo Maruyama
  • Patent number: 9773717
    Abstract: A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more first conductors connected to a first electrical connection on the semiconductor device, the first conductor comprising a first material having a positive Seebeck coefficient; and one or more second conductors connected to a second electrical connection on the semiconductor device, the second conductor comprising a second material having a negative Seebeck coefficient. The first conductor and the second conductor conduct electrical current through the semiconductor device and conduct heat away from the semiconductor device.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siyuranga O. Koswatta, Sungjae Lee, Lan Luo, Scott K. Springer, Richard A. Wachnik
  • Patent number: 8952480
    Abstract: An electronic device may include a temperature sensing semiconductor substrate, that may include a thermal sensor at an upper surface thereof, and a cooling semiconductor substrate having an upper surface coupled to a lower surface of the temperature sensing semiconductor substrate. The cooling semiconductor substrate may include a Peltier cooler. At least one of the temperature sensing semiconductor substrate and the cooling semiconductor substrate may have a cavity therein beneath the thermopile and aligned therewith.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventor: PraveenKumar Radhakrishnan
  • Patent number: 8659903
    Abstract: A device has a passive cooling device having a surface, at least one active cooling device on the surface of the passive cooling device, and a thermal switch coupled to the passive cooling device, the switch having a first position that connects the active cooling device to a path of high thermal conductivity and a second position that connects the passive cooling device to the path of high thermal conductivity.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 25, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventor: David Eric Schwartz
  • Patent number: 8598636
    Abstract: The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: December 3, 2013
    Assignee: Peking University
    Inventors: Ru Huang, Xin Huang, Shoubin Xue, Yujie Ai
  • Publication number: 20130001655
    Abstract: The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal.
    Type: Application
    Filed: August 17, 2011
    Publication date: January 3, 2013
    Inventors: Ru Huang, Xin Huang, Shoubin Xue, Yujie Ai
  • Patent number: 8264055
    Abstract: A CMOS thermoelectric refrigerator made of an NMOS transistor and PMOS transistor connected in series through a cold terminal is disclosed. Active areas of the NMOS and PMOS transistors are less than 300 nanometers wide, to reduce thermal conduction between the cold terminal and the IC substrate. Drain nodes of the NMOS and PMOS transistors are connected through hot terminals to a biasing circuit. The drain node of the NMOS transistor is biased positive with respect to the drain node of the PMOS transistor, to extract hot electrons and hot holes from the cold terminal. Biases on the drain nodes and gates of the NMOS and PMOS transistors may be adjusted to optimize the efficiency of the CMOS thermoelectric refrigerator or maximize the thermal power of the CMOS thermoelectric refrigerator. The cold terminal may be configured to cool a selected component in the IC, such as a transistor.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: September 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Henry Litzmann Edwards
  • Patent number: 8232127
    Abstract: A thermo-electric semiconductor device is provided. The thermo-electric semiconductor device includes: a first electrode layer; a spacer layer formed on the first electrode layer and having a plurality of pillars with a uniform height, the plurality of pillars thermally grown and protruded on a surface of the spacer layer; and a second electrode layer formed over the spacer layer in such a manner as to contact tops of the protruded pillars.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: July 31, 2012
    Assignees: Hanvision Co., Ltd., Lumiense Photonics Inc.
    Inventor: Robert Hannebauer
  • Patent number: 8159152
    Abstract: A high-power light-emitting diode (LED) lamp has a plurality of units. Each unit includes an LED die and a thermo-electric cooling device coupled to the LED die. A power source supplies a fixed current to the thermo-electric cooling device wherein the fixed current is based on heat generated by the LED die in normal operation. Accordingly, the unit operates without a controller.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: April 17, 2012
    Inventor: Nader Salessi
  • Patent number: 8058724
    Abstract: Various semiconductor chip thermal management systems and methods are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate and coupling a diamond heat spreader that has a thermoelectric cooler to the semiconductor chip. A vapor chamber is coupled to the diamond heat spreader.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: November 15, 2011
    Assignee: ATI Technologies ULC
    Inventor: Gamal Refai-Ahmed
  • Publication number: 20110135015
    Abstract: An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length corresponding to the height such that the devices are sealed within the cover when the cover is attached to a surface.
    Type: Application
    Filed: November 1, 2010
    Publication date: June 9, 2011
    Inventors: Gregory M. Chrysler, Tony A. Opheim
  • Patent number: 7943977
    Abstract: An apparatus that can effectively operate in high temperatures including a CMOS image sensor, a thermoelectric semiconductor formed under the CMOS image sensor for selectively cooling the image sensor and a heat sink formed under the thermoelectric semiconductor.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: May 17, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chang-Hun Han
  • Patent number: 7928459
    Abstract: The present invention relates to a light emitting diode package, and provides a light emitting diode package employing a thermoelectric element therein. The light emitting diode package of the present invention is constructed such that the thermoelectric element is coupled to a housing or formed of a substrate itself so as to directly dissipate heat generated from a light emitting chip. Thus, the heat generated from the light emitting chip can be efficiently dissipated from the interior of the package to the outside, without an additional heat dissipation means. In addition, an external heat sink may be coupled to the thermoelectric element to more efficiently dissipate the heat from the light emitting chip.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: April 19, 2011
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Bang Hyun Kim, Kwang Il Park
  • Patent number: 7915620
    Abstract: Disclosed is a light-emitting device. The light-emitting device includes an EL layer and a heat dissipation layer. The EL layer includes a first semiconductor layer, a second semiconductor layer, and an active layer, the first semiconductor layer having a first conductivity type that is one of n type and p type, the second semiconductor layer having a second conductivity type that is opposite to the first conductivity type, the active layer being provided between the first semiconductor layer and the second semiconductor layer. The heat dissipation layer has the first conductivity type and is bonded to a side of the EL layer closer to the second semiconductor layer than the first semiconductor layer.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: March 29, 2011
    Assignee: Sony Corporation
    Inventors: Yuichi Ishida, Kazuaki Yazawa, Norikazu Nakayama
  • Patent number: 7851905
    Abstract: A microelectronic package comprises a substrate (110, 310), a die (320) supported by the substrate, an interconnect feature (130, 230, 330) connecting the die and the substrate to each other, and a thermoelectric cooler (140, 170, 240, 340) adjacent to the interconnect feature.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: December 14, 2010
    Assignee: Intel Corporation
    Inventors: Gregory M. Chrysler, Ravi V. Mahajan, Chia-Pin Chiu
  • Patent number: 7851815
    Abstract: A light-emitting element, in particular a light-emitting diode, having at least one light-emitting chip crystal, in particular a semiconductor crystal, is described. At least free surfaces of the light-emitting chip crystal are covered with an inert material—liquid fluid—which is in direct contact with the light-emitting chip crystal.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: December 14, 2010
    Assignee: Noctron Holding S.A.
    Inventor: Georg Diamantidis
  • Patent number: 7800194
    Abstract: A photodetector, comprises a first section comprising at least one p-n junction that converts photon energy into a separate charge carrier and hole carrier; and another section of semiconductors of opposing conductivity type connected electrically in series and thermally in parallel in a heat dissipating and electric generating relationship to the cell to augment generation of electric energy of the first section.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: September 21, 2010
    Inventor: Philip D. Freedman
  • Patent number: 7759789
    Abstract: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kai Di Feng, Alvin Jose Joseph, Donald J. Papae, Xiaojin Wei
  • Patent number: 7751191
    Abstract: A cooling system that promotes cooling of a device including a heat source therein is provided, the cooling system includes: a cooling unit that absorbs, upstream from the heat source, heat from intake air that the device takes in from an outside to cool the heat source and dissipates the heat to an outside of a flow path of the intake air; and a fluid control unit that lets fluid flow toward the cooling unit so as to discharge the heat absorbed by the cooling unit from the intake air to an outside of the cooling unit.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kohichi Kakikawa, Yohichi Matsui, Hiroyuki Takenoshita
  • Publication number: 20090321909
    Abstract: Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.
    Type: Application
    Filed: June 27, 2008
    Publication date: December 31, 2009
    Applicant: QUALCOMM INCORPORATED
    Inventors: Shiqun Gu, Matthew Nowak, Thomas R. Toms
  • Patent number: 7626261
    Abstract: A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and a coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: December 1, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joong-Hyun Baek, Hee-Jin Lee
  • Patent number: 7608849
    Abstract: The present invention provides a non-volatile switching element having a novel structure that operates at a high speed and enables high integration, and an integrated circuit that includes such non-volatile switching elements. The switching element includes: a switching film formed on a substrate, made of a material causing a 10 times or greater change in electric resistance with a temperature change within a range of ±80 K from a predetermined temperature; a Peltier element causing the switching film to have the temperature change; a heat conducting/electric insulating film provided between the switching film and the Peltier element, to conduct heat from the Peltier element; and a pair of electrodes connected to the switching film.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: October 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro Ino, Masato Koyama
  • Patent number: 7589417
    Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: September 15, 2009
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Gregory M. Chrysler, Steven N. Towle, Anna M. George, legal representative
  • Patent number: 7569929
    Abstract: A semiconductor device is disclosed that includes a circuit board, a semiconductor element, a heat sink, and a stress relaxation member. The circuit board includes an insulated substrate, a metal circuit joined to one side of the insulated substrate, and a metal plate joined to the other side of the insulated substrate. The semiconductor element is joined to the metal circuit. The heat sink radiates heat generated in the semiconductor element. The stress relaxation member thermally joins the heat sink to the metal plate. The stress relaxation member is formed of a material having a high thermal conductivity. The stress relaxation member includes recesses, which curve inward from the peripheral portion of the stress relaxation member, to form stress relaxation spaces at the peripheral portion of the stress relaxation member.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: August 4, 2009
    Assignees: Kabushiki Kaisha Toyota Jidoshokki, Showa Denko K.K.
    Inventors: Shogo Mori, Keiji Toh, Shinobu Tamura, Shinobu Yamauchi
  • Publication number: 20090179323
    Abstract: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 16, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai Di Feng, Alvin Jose Joseph, Donald J. Papae, Xiaojin Wei
  • Patent number: 7525191
    Abstract: A semiconductor light source device, for enabling to cool LED elements driven with short pulses, effectively, and also being cheaply producible without increasing the number of pats thereof, comprising a plural number of light emitting diode chips 202 on a heat diffusion plate 201, and Peltier elements 208, as being thermoelectric cooling elements, for cooling the plural number of light emitting diode chips 202, wherein a pair of members 208(n) and 2008(p), building up the Peltier element for cooling each the light emitting diode chip, are electrically connected on each of the light emitting diode chip through bumps 207, so as to form said light emitting diode chip and the Peltier element as a unit on the heat diffusion plate, respectively, and thereby moving heat generation within each of the light emitting diode chips, directly, into the heat diffusion plate and/or a heat radiation plate.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: April 28, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Norio Nakazato, Kimihiko Sudo
  • Patent number: 7518148
    Abstract: An organic device package that provides full fault tolerance against both electrical shorts and electrical opens is presented. An organic device package comprising a plurality of groups of organic electronic elements electrically coupled in series, where at least one of the plurality of groups of organic electronic elements comprises a plurality of sub-groups of organic electronic elements electrically coupled in parallel, and where at least one of the plurality of sub-groups of organic electronic elements comprises a plurality of organic electronic elements electrically coupled in series. Further, various embodiments are contemplated where a plurality of series blocks and parallel blocks may be nested to provide a grid network having increased flexibility and fault tolerance.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: April 14, 2009
    Assignee: General Electric Company
    Inventors: Jie Liu, Anil Raj Duggal
  • Publication number: 20090079063
    Abstract: A microelectronic package comprises a substrate (110, 310), a die (320) supported by the substrate, an interconnect feature (130, 230, 330) connecting the die and the substrate to each other, and a thermoelectric cooler (140, 170, 240, 340) adjacent to the interconnect feature.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventors: Gregory M. Chrysler, Ravi V. Mahajan, Chia-Pin Chiu
  • Publication number: 20090071525
    Abstract: An apparatus includes a thermoelectric cooler adjacent to a surface of a device substrate and including a first set of one or more metal electrodes, a second set of one or more metal electrodes, and one or more semiconductor members. Each member includes a material different from the device substrate and physically joins a corresponding one electrode of the first set to a corresponding one electrode of the second set. The electrodes and at least one member are configured to transport heat to or from a thermal load in a direction parallel to the surface of the device substrate.
    Type: Application
    Filed: September 17, 2007
    Publication date: March 19, 2009
    Applicant: Lucent Technologies, Inc.
    Inventors: Marc Scott Hodes, Shankar Krishnan
  • Publication number: 20090072385
    Abstract: An electronic assembly may include a packaging substrate, an integrated circuit (IC) semiconductor chip, a plurality of metal interconnection structures, and a thermoelectric heat pump. The integrated circuit (IC) semiconductor chip may have an active side including input/output pads thereon and a back side opposite the active side, and the IC semiconductor chip may be arranged with the active side facing the first surface of the packaging substrate. The plurality of metal interconnection structures may be between the active side of the IC semiconductor chip and the first surface of the packaging substrate, and the plurality of metal interconnection structures may provide mechanical connection between the active side of the IC semiconductor chip and the first surface of the packaging substrate. The thermoelectric heat pump may be coupled to the packaging substrate with the thermoelectric heat pump being configured to actively pump heat between the IC semiconductor chip and the packaging substrate.
    Type: Application
    Filed: January 18, 2008
    Publication date: March 19, 2009
    Inventors: Randall G. Alley, Philip A. Deane, David A. Koester, Thomas Peter Schneider, Jesko Von Windheim
  • Patent number: 7466553
    Abstract: Liquid cooling systems and apparatus are presented. A number of embodiments are presented. In each embodiment, a heat transfer system capable of thermally coupling to heat generating components and adapted to transfer heat from the heat generating components is implemented. A variety of embodiments of the heat transfer system are presented. For example, several embodiments of a heat transfer system including electron-conducting material is presented. In one embodiment of the present invention, the electron conducting material operates under the peltier principal.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: December 16, 2008
    Assignee: QNX Cooling Systems, Inc.
    Inventor: Brian A. Hamman
  • Publication number: 20080230106
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a first plurality of openings through a first surface of a substrate, forming a p-type TFTEC material within the first plurality of openings, forming a second plurality of openings substantially adjacent to the first plurality of openings through the first surface of the substrate, and then forming an n-type TFTEC material within the second plurality of openings.
    Type: Application
    Filed: April 18, 2008
    Publication date: September 25, 2008
    Inventor: Rajashree Baskaran
  • Publication number: 20080212625
    Abstract: Disclosed is a semiconductor apparatus comprising an N-type material which cools a silicon semiconductor using the current flowing through the silicon semiconductor.
    Type: Application
    Filed: January 14, 2008
    Publication date: September 4, 2008
    Applicant: Kabusiki Kaisha Y.Y.L.
    Inventors: Sataro YAMAGUCHI, Yoichi Okamoto
  • Patent number: 7402910
    Abstract: A solder, in particular a thin-film solder, for joining microelectromechanical components, wherein the solder is a eutectic mixture of gold and bismuth. Components and devices joined by a solder of this type are also disclosed, in addition to processes for producing such components or devices.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: July 22, 2008
    Assignees: Micropelt GmbH, Fraunhofer Gesellschaft zur Forderung der angewandten Forschung e.V.
    Inventors: Harald Böttner, Axel Schubert, Martin Jaegle
  • Patent number: 7388286
    Abstract: A semiconductor package comprising a semiconductor chip and a first heat spreader adhered to the upper surface of the semiconductor chip is provided. The first heat spreader comprises a flat metal plate and a plurality of metal balls adhered to the flat metal plate. A method of fabricating the semiconductor chip package is also provided.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: June 17, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-uk Kim, Yun-hyeok Im
  • Patent number: 7352063
    Abstract: A semiconductor device has a semiconductor chip having first and second surfaces; a sealing resin formed over the first surface; and a cooling structure having a first conductive layer formed on the first surface, an n-type semiconductor formed on the first conductive layer and having one end thereof being exposed from the sealing resin, a p-type semiconductor formed on the first conductive layer and having one end thereof being exposed from the sealing resin, a second conductive layer contacting the exposed end of the n-type semiconductor, a third conductive layer contacting the exposed end of the p-type semiconductor, a first electrode pad integrally formed with the second conductive layer, a second electrode pad integrally formed with the third conductive layer, and spherical electrodes formed at the first and second electrode pads, respectively.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: April 1, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takashi Noguchi
  • Patent number: 7304380
    Abstract: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: December 4, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. Farrar, Leonard Forbes, Kie Y. Ahn, Joseph E. Geusic, Arup Bhattacharyya, Alan R. Reinberg
  • Patent number: 7282798
    Abstract: A method and structure for heat transport, cooling, sensing and power generation is described. A photonic bandgap structure (3) is employed to enhance emissive heat transport from heat sources such as integrated circuits (2) to heat spreaders (4). The photonic bandgap structure (3) is also employed to convert heat to electric power by enhanced emission absorption and to cool and sense radiation, such as infra-red radiation. These concepts may be applied to both heat loss and heat absorption, and may be applied to heat transport and absorption enhancement in a single device.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: October 16, 2007
    Assignee: Research Triangle Institute
    Inventor: Rama Venkatasubramanian
  • Patent number: 7279787
    Abstract: A microelectronic complex including a body of semi-conductor material containing an integrated circuit, and a plurality of contact pads on the body for receiving signal conducting members for connection to an external substrate. The contact pads allow signals to be exchanged between the integrated circuit and the external substrate via the signal conducting members. A majority of the contact pads are disposed on the body of the microelectronic complex according to a configuration whereby the stress effects on the signal conducting members caused by thermal expansion mismatch between the microelectronic complex and the external substrate are minimized. In a specific configuration, a majority of the contact pads form a cluster circumscribing a predetermined area of the microelectronic complex body, whereby the cluster is characterized by a minimum inter-pad distance among the majority of contact pads on the body of the microelectronic complex.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: October 9, 2007
    Inventors: Richard S. Norman, David Chamberlain
  • Patent number: 7268019
    Abstract: Embodiments of methods and apparatus for high temperature operation of electronics according to the invention are disclosed. One embodiment of the invention generally includes an integrated circuit package having a substrate. A plurality of integrated circuits are coupled to a surface of the substrate. A lid is positioned above the substrate facing the surface. One or more pieces of compliant and thermally conductive material are compressed between at least one of the integrated circuits and the lid. The lid defines in part an enclosed volume containing the compliant and thermally conductive material.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: September 11, 2007
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Christopher Golla, Roger L. Schultz, James Masino
  • Patent number: 7224059
    Abstract: Embodiments of the present invention provide a method, apparatus and system for absorbing heat from an active side of a die by a plurality of cold conductive elements embedded in said die, and releasing said absorbed heat by a plurality of hot conductive elements embedded in a substrate connected to said die.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Ryo Shimada, Shinichi Sakamoto
  • Patent number: 7218523
    Abstract: Liquid cooling systems and apparatus are presented. A number of embodiments are presented. In each embodiment, a heat transfer system capable of engaging a processor and adapted to transfer heat from the processor is implemented. A variety of embodiments of the heat transfer system are presented. For example, several embodiments of a heat transfer system including electron-conducting material is presented. In one embodiment of the present invention, the electron conducting material operates under the peltier principal.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: May 15, 2007
    Assignee: QNX Cooling Systems Inc
    Inventor: Brian A. Hamman
  • Patent number: RE41801
    Abstract: A termoelectric thermoelectric device and method for manufacturing the thermoelectric device.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: October 5, 2010
    Assignee: Nextreme Thermal Solutions, Inc.
    Inventor: Rama Venkatasubramanian