Arrangements For Cooling, Heating, Ventilating Or Temperature Compensation; Temperature-sensing Arrangements (epo) Patents (Class 257/E23.08)
  • Patent number: 10458856
    Abstract: The present invention relates to integrated circuits. More specifically, embodiments of the present invention provide methods and systems for determining temperatures of an integrated circuit using an one-point calibration technique, where temperature is determined by a single temperature measurement and calculation using known electrical characteristics of the integrated circuit.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 29, 2019
    Assignee: INPHI CORPORATION
    Inventors: Sadettin Cirit, Karthik S. Gopalakrishnan
  • Patent number: 10361709
    Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: July 23, 2019
    Assignee: Cirrus Logic, Inc.
    Inventor: John P. Lesso
  • Patent number: 10331911
    Abstract: An electromagnetic radiation (EMR) receiver is located upon a printed circuit board (PCB) glass security layer. EMR flux is transmitted by the glass security layer and received by the EMR receiver. When the PCB is subject to a tamper event the EMR transmitted by glass security layer is increased. A monitoring device that monitors the flux or interference pattern of the EMR received by the EMR receiver detects a change in flux or interference pattern and passes a tamper signal to one or more computer system devices to respond to the tamper event. For example, one or more cryptographic adapter card or computer system functions or secured crypto components may be disabled.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joseph Kuczynski, Phillip V. Mann, Kevin M. O'Connell
  • Patent number: 10290555
    Abstract: A semiconductor device comprises a power device, a sensor which measures a physical state of the power device to transmit a signal according to the physical state, and a main electrode terminal through which a main current of the power device flows. The semiconductor device further comprises a sensor signal terminal connected to the sensor for receiving a signal from the sensor, a driving terminal which receives driving power for driving the power device, and an open bottomed case which houses the power device, the sensor, the main electrode terminal, the sensor signal terminal and the driving terminal. The first and second terminals electrically conduct with each other to form a double structure. Also, the sensor signal terminal and the driving terminal each have a first terminal and a second terminal which are not embedded within the case.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 14, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Motonobu Joko, Rei Yoneyama
  • Patent number: 10251320
    Abstract: Disclosed is a managing device for cooling an inverter. The managing device for cooling an inverter includes a fan controller configured to provide an electric current flowing in a cooling fan; and a controller configured to determine whether the current flowing in the cooling fan is out of a preset range, and, when the current is out of the preset range, configured to control the cooling fan with a control voltage different from an operating voltage of the cooling fan.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 2, 2019
    Assignee: LSIS CO., LTD.
    Inventors: Chun-Suk Yang, Tae-Suk Bae
  • Patent number: 10075066
    Abstract: An internal voltage generation circuit may be provided. The internal voltage generation circuit may include a first internal voltage generation circuit configured to provide a reference internal voltage to either an internal voltage control circuit or a node at which an output internal voltage is generated. The internal voltage generation circuit may include a second internal voltage generation circuit configured to change a level of the output internal voltage. The internal voltage generation circuit may include an internal voltage control circuit configured to compare the reference internal voltage with the output internal voltage and control the first and second internal voltage generation circuits to change the level of the output internal voltage according to a comparison.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: September 11, 2018
    Assignee: SK hynix Inc.
    Inventors: Kyung Hoon Kim, Jee Yeon Keh
  • Patent number: 10031180
    Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Anand Haridass, Arun Joseph, Charles R. Lefurgy, Spandana V. Rachamalla
  • Patent number: 9871153
    Abstract: A temperature-controlled photodetector sub-system is described. The temperature control element allows the operation of the photodetector at a desired temperature. The temperature control element can be a heater or a cooler. In some cases, the photodetector is a germanium photodetector. In some cases a temperature measuring device is provided. In some cases, a control circuit is used to control the temperature of the germanium photodetector within a temperature range, or at a temperature of interest. An advantage provided by the apparatus described is the operation of the photodetector so that the responsivity of the germanium detector can be held at essentially a constant value.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: January 16, 2018
    Assignee: Elenion Technologies, Inc.
    Inventors: Ari Novack, Ruizhi Shi, Jean Claude Labarrie
  • Patent number: 9768754
    Abstract: The present invention discloses a control circuit for a gate driver circuit, an operating method thereof and a display device comprising the control circuit, the control circuit includes: a detection circuit, a power supply and a charge pump circuit, wherein, the detection circuit is used to generate a digital control signal corresponding to an ambient temperature based on the ambient temperature of the gate driver circuit, the power supply is used to supply an initial voltage to a pump charge circuit and the pump charge circuit is used to adjust the initial voltage based on the digital control signal to generate a driving voltage, and output the driving voltage to the gate driver circuit. By enabling the driving voltage to be dynamically adjustable, the power consumption of the gate driver circuit is reduced, and the life of the thin film transistor in the gate driver circuit is lengthened.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: September 19, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Qian Wang
  • Patent number: 9671293
    Abstract: A temperature detection circuit and a temperature measurement circuit capable of detecting and measuring temperatures precisely are disclosed. The temperature detection circuit includes n temperature detectors (n is an integer of 2 or more), each of the temperature detectors being configured to output a detection signal of high level when a temperature of an object reaches a first value, and a temperature determination part configured to determine whether or not the temperature of the object has reached a second value based on a count of high-level detection signals.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: June 6, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kazuhiro Kamiya, Kimitoshi Niratsuka
  • Patent number: 9625986
    Abstract: According to one embodiment, a semiconductor device includes: an integrated circuit that has a plurality of power consumption modes different in power consumption; a temperature detection circuit that detects temperature of the integrated circuit; a counter that measures time taken for temperature change in the integrated circuit; and a state machine that causes a state transition to take place in the integrated circuit based on the temperature detected by the temperature detection circuit and the time measured by the counter, wherein the integrated circuit selects the power consumption mode based on the state subjected to transition by the state machine.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: April 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Kurosawa, Shuuji Matsumoto
  • Patent number: 9628689
    Abstract: This image pickup element unit is provided with: an image pickup element substrate having mounted thereon an image pickup element that converts inputted light into electric signals; and a temperature adjusting member for adjusting the temperature of the image pickup element. The image pickup element unit is configured such that: the temperature adjusting member is configured to have a recessed section, and include a left-side member, a right-side member, an upper-side member, a lower-side member, and a rear-side member of the recessed section; the image pickup element is disposed to be surrounded by the left-side member, the right-side member, the upper-side member, the lower-side member, and the rear-side member; and the image pickup element unit is attached to the image pickup element substrate by having the rear-side member therebetween.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 18, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Shigeo Nakada, Hiromu Matsumoto, Makoto Inagaki, Hiroyuki Mori
  • Patent number: 9484930
    Abstract: Methods, systems, and computer program products for initializing one or more components of a system, the system comprising an integrated circuit that comprises at least one processor, are disclosed. A method includes initializing at least one component of the system, determining a temperature of the integrated circuit using a temperature sensing device embedded on the integrated circuit, comparing the determined temperature to a predetermined suitable temperature operating range of at least one additional component to yield a comparison result, and initializing the at least one additional component based on the comparison result. The at least one additional component may be initialized on the condition that the determined temperature of the integrated circuit is within the predetermined suitable temperature operating range of the at least one additional component.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: November 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Giang Chau Nguyen, James Mitchell Rakes, Robert Michael Dinkjian
  • Patent number: 9397134
    Abstract: Methods and devices configured to provide selective heat transfer of a temperature-sensitive circuit are provided. In an example, a device comprises a thinned base substrate including an integrated circuit (e.g., back side illuminated (BSI) image sensor comprising a detector array area and a peripheral circuitry area). The device also comprises a supporting substrate comprising one or more thermoelectric structures. The supporting substrate may be coupled to the base substrate such that the one or more thermoelectric structures are aligned with the detector array area, and the thermoelectric structures may be configured to transfer heat away from the detector array area, while a reduced cross-section of a thinned base substrate may be configured to substantially reduce lateral heat flow across the base substrate and enable selective heat transfer.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: July 19, 2016
    Assignee: Google Inc.
    Inventor: Roman Lewkow
  • Patent number: 9040338
    Abstract: Method of manufacturing sinterable electrical components for jointly sintering with active components, the components in planar shape being provided with at least one planar lower face meant for sintering, and an electrical contact area on the face opposite to the sintering face being available in the form of a metallic contact face, whose upper side is contactable by means of a commonly known method of the group: wire bonding or soldering or sintering or pressure contacting, the component being a temperature sensor, whose lower face is provided with a sinterable metallization on a ceramic body, said ceramic body having two electrical contact faces for continued electrical connection.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: May 26, 2015
    Assignee: Danfoss Silicon Power GmbH
    Inventor: Ronald Eisele
  • Patent number: 9041195
    Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventor: Mattias E. Dahlstrom
  • Patent number: 9035337
    Abstract: An object is to provide a light-emitting module in which a light-emitting element suffering a short-circuit failure does not cause wasteful electric power consumption. Another object is to provide a light-emitting panel in which a light-emitting element suffering a short-circuit failure does not allow the reliability of an adjacent light-emitting element to lower. Focusing on heat generated by a light-emitting element suffering a short-circuit failure, provided is a structure in which electric power is supplied to a light-emitting element through a positive temperature coefficient thermistor (PTC thermistor) thermally coupled with the light-emitting element.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaaki Hiroki, Satoshi Seo, Yasuo Nakamura
  • Patent number: 9029989
    Abstract: A semiconductor package includes a substrate, a ground circuit supported by the substrate, at least one semiconductor chip disposed on the substrate and a carbon-containing heat-dissipating part disposed on the substrate and electrically connected to the ground circuit. The heat-dissipating part may include carbon fibers and/or carbon cloth.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Soojeoung Park
  • Patent number: 9030004
    Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Tae Park, Kang-Wook Lee, Young-Don Choi, Yun-Sang Lee
  • Patent number: 8994161
    Abstract: Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate nearly to an upper surface of the filler layer. In some embodiments of electronic packages, the through contacts separated from the heat sink by a trench cut into the upper surface of the filler layer, the through contacts intersecting one wall of the trench and the heat sink intersecting the other wall of the trench an electronic semiconductor package. A method of forming the package and a lead frame are also disclosed.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Michael Ahr, Bakuri Lanchava
  • Patent number: 8975663
    Abstract: There is provided a semiconductor device such that it is possible to average the temperatures of a plurality of semiconductor chips simply by providing gate resistors. The semiconductor device includes a semiconductor module wherein a plurality of circuit substrates on which are mounted one or more semiconductor chips having a gate terminal and a gate resistor connected to the gate terminal are disposed in parallel, wherein the disposition distance of the gate resistor from the semiconductor chip is set based on the temperature of the semiconductor chip.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: March 10, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yujin Okamoto
  • Patent number: 8970030
    Abstract: The invention relates to an electronic module and to a method for producing same, comprising a mold body (2), a first circuit carrier (3; 13) having a first inner face (3a; 13a), on which electronic components (5) are arranged, and a first outer face (3b; 13b), a second circuit carrier (4; 14) having a second inner face (4a; 14a), on which electronic components (5) are arranged, and a second outer face (4b; 14b), and at least one spring device (6, 7; 16) which connects the inner faces (3a, 14a; 13a, 14a), or surfaces of electronic components (5) arranged thereon, of the first and second circuit carriers (3, 4; 13, 14), wherein the first and second outer faces (3a, 4a; 13a, 14a) are exposed towards the outside of the electronic module in order to emit heat directly to the outside, and wherein the first and second outer faces (3a, 4a; 13a, 14a) are parallel to each other.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 3, 2015
    Assignee: Robert Bosch GmbH
    Inventor: Matthias Keil
  • Patent number: 8963321
    Abstract: A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Andreas Lenniger, Andre Uhlemann, Olaf Hohlfeld
  • Patent number: 8941232
    Abstract: The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Yi-Jen Lai, Chun-Jen Chen, Perre Kao
  • Patent number: 8941233
    Abstract: Integrated circuit (IC) packages with an inter-die thermal spreader are disclosed. A disclosed IC package includes a plurality of stacked dies disposed on a package substrate. A heat spreader is disposed on a top die of the plurality of stacked dies. The IC package further includes a thermal spreader layer disposed adjacent to at least one die of the plurality of stacked dies. The thermal spreader layer may extend out of a periphery of the plurality of stacked dies and may be attached to the heat spreader through a support member.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: January 27, 2015
    Assignee: Altera Corporation
    Inventors: Tony Ngai, Arifur Rahman
  • Patent number: 8937383
    Abstract: The semiconductor package as well as a method for making it and using it is disclosed. The semiconductor package comprises a semiconductor chip having at least one heat-generating semiconductor device and a volumetrically expandable chamber disposed to sealingly surround the semiconductor chip, the volumetrically expandable chamber filled entirely with a non-electrically conductive liquid in contact with the semiconductor device and circulated within the volumetrically expandable chamber at least in part by the generated heat of the at least one semiconductor device to cool the at least one semiconductor device.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: January 20, 2015
    Assignee: The Boeing Company
    Inventors: Andrew G. Laquer, Ernest E. Bunch
  • Patent number: 8936763
    Abstract: The invention is directed to apparatus and chips comprising a large scale chemical field effect transistor arrays that include an array of sample-retaining regions capable of retaining a chemical or biological sample from a sample fluid for analysis. In one aspect such transistor arrays have a pitch of 10 ?m or less and each sample-retaining region is positioned on at least one chemical field effect transistor which is configured to generate at least one output signal related to a characteristic of a chemical or biological sample in such sample-retaining region.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: January 20, 2015
    Assignee: Life Technologies Corporation
    Inventors: Jonathan Rothberg, James Bustillo, Mark Milgrew, Jonathan Schultz, David Marran, Todd Rearick, Kim Johnson
  • Patent number: 8933560
    Abstract: A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takumi Ihara, Masami Mouri
  • Patent number: 8933484
    Abstract: A heat transfer member is disposed between a semiconductor element and an electrode plate. The heat transfer member comprises a metal portion extending between a first face at the semiconductor element side and a second face at the plate electrode side, and a ceramic portion surrounding the metal portion. An area of the first face is less than an area of the second face in the metal portion.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: January 13, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Makoto Imai, Atsushi Tanida, Takashi Asada, Masanori Usui, Tomoyuki Shoji
  • Patent number: 8916964
    Abstract: A semiconductor device and a method of producing the same, wherein a joining member and a joined member are bonded by means of brazing in a way such that no voids are left inside the joining layer. The semiconductor device comprises a joined member and a joining member which is joined to the joined member by means of brazing. The joined member is provided with a through hole which is open on the joining surface with the joining member, and a path communicating with the through hole is provided on at least one of the joining surface of the joining member with the joined member or the joining surface of the member with the joining member.
    Type: Grant
    Filed: November 27, 2009
    Date of Patent: December 23, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Yasuji Taketsuna, Eisaku Kakiuchi, Katsuhiko Tatebe, Masahiro Morino, Tomohiro Takenaga
  • Patent number: 8896113
    Abstract: According to one embodiment, the base plate includes first and a second faces that are opposed to each other; the second face has a contoured rear surface, and the first area is set in the center of the plate. There is a second area with via holes in the peripheral areas of the center part. Also, the thickness of the second area is less than the thickness of the first area.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eitaro Miyake
  • Patent number: 8872328
    Abstract: An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: October 28, 2014
    Assignee: General Electric Company
    Inventors: Eladio Clemente Delgado, John Stanley Glaser, Brian Lynn Rowden
  • Patent number: 8866183
    Abstract: An LED module includes: a package having electrodes provided on the outer surface of opposing sidewalls, and a light-emitting element connected to the electrodes and mounted on the package; a base member having a copper metal; an insulating layer stacked on the surface of the base member and having an insulating material; and a conductive wiring pattern connected to the electrodes by soldering and formed on the surface of the insulating layer. The insulating layer has a through-hole formed by removing a part of the section where the package is positioned, and a heat dissipation unit formed by soldering between the back surface of the package and the base member, which face one another with the through-hole interposed therebetween.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: October 21, 2014
    Assignee: Panasonic Industrial Devices Sunx Co., Ltd.
    Inventors: Sachio Higuchi, Takashi Tanaka, Mitunori Mizoguti, Tsuyoshi Inui, Atsuo Fukuda
  • Patent number: 8860211
    Abstract: A semiconductor device includes an insulation layer, a first semiconductor element and a second semiconductor element which are disposed within the insulation layer, a frame which has higher thermal conductivity than the insulation layer and surrounds the first semiconductor element and the second semiconductor element via the insulation layer, and a wiring layer which is disposed over the insulation layer and includes an electrode which electrically connects the first semiconductor element and the second semiconductor element.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventor: Junichi Kon
  • Patent number: 8847222
    Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive feature disposed between the stress line and the feed line. The test structure includes a temperature adjuster proximate at least the conductive feature, and at least one feedback device coupled to the temperature adjuster and at least the conductive feature.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: September 30, 2014
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Walter
  • Patent number: 8841768
    Abstract: A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: September 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Carsten Von Koblinski, Michael Knabl, Ursula Meyer, Francisco Javier Santos Rodriguez, Alexander Breymesser, Andre Brockmeier
  • Patent number: 8836104
    Abstract: Various stress relief structures are provided for effectively reducing thermal stress on a semiconductor chip in a chip package. Trenches on a metal substrate are created in groups in two-dimension, where each trench is opened from top or bottom surface of the metal substrate and in various shapes. The metal substrate is partitioned into many smaller substrates depending on the number of trench groups and partitions, and is attached to a semiconductor chip for stress relief. In an alternative embodiment, a plurality of cylindrical metal structures are used together with a metal substrate in a chip package for the purpose of heat removal and thermal stress relief on a semiconductor chip. In another alternative embodiment, a metal foam is used together with a semiconductor chip to create a chip package. In another alternative embodiment, a semiconductor chip is sandwiched between a heat sink and a circuit board by solder bumps directly with underfill on the circuit board.
    Type: Grant
    Filed: March 3, 2012
    Date of Patent: September 16, 2014
    Inventor: Ho-Yuan Yu
  • Patent number: 8836110
    Abstract: A packaged semiconductor device includes a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sheila F. Chopin, Varughese Mathew
  • Patent number: 8829534
    Abstract: Provided is a power semiconductor device including: a power semiconductor element; a metal block as a first metal block that is connected to the power semiconductor element through an upper surface electrode pattern as a first upper surface electrode pattern selectively formed on an upper surface of the power semiconductor element; and a mold resin filled so as to cover the power semiconductor element and the metal block, wherein an upper surface of the metal block is exposed from a surface of the mold resin.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: September 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masao Kikuchi
  • Patent number: 8823153
    Abstract: Disclosed herein is a semiconductor package. The semiconductor package includes: semiconductor elements, a first heat dissipation substrate formed under the semiconductor elements, a first lead frame electrically connecting the lower portions of the semiconductor elements to an upper portion of the first heat dissipation substrate, a second heat dissipation substrate formed over the semiconductor elements, and a second lead frame having a protrusion formed to be protruded from a lower surface thereof and electrically connecting the upper portions of the semiconductor elements to a lower portion of the second heat dissipation substrate.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: September 2, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hoon Kim, Seog Moon Choi
  • Patent number: 8804300
    Abstract: A pump having: a cavity formed inside an insulating substrate, the upper part of the substrate being situated near the cavity having an edge; a conductive layer covering the inside of the cavity up to the edge and optionally covering the edge itself; a flexible membrane made of a conductive material placed above the cavity and resting against the edge; a dielectric layer covering the conductive layer or the membrane whereby insulating the portions of the conductive layer and of the membrane that are near one another; at least one aeration line formed in the insulating substrate that opens into the cavity via an opening in the conductive layer, and; terminals for applying a voltage between the conductive layer and the membrane.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: August 12, 2014
    Assignee: STMicroelectronics S.A.
    Inventor: Guillaume Bouche
  • Patent number: 8796840
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 5, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8766328
    Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: July 1, 2014
    Assignee: Life Technologies Corporation
    Inventors: Jonathan M. Rothberg, Wolfgang Hinz, Kim L. Johnson, James Bustillo
  • Patent number: 8766327
    Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: July 1, 2014
    Assignee: Life Technologies Corporation
    Inventor: Mark Milgrew
  • Patent number: 8753924
    Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Cooper Wainerdi, Luigi Colombo, John Paul Tellkamp, Robert Reid Doering
  • Patent number: 8748947
    Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 10, 2014
    Assignee: Life Technologies Corporation
    Inventor: Mark Milgrew
  • Patent number: 8742469
    Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 3, 2014
    Assignee: Life Technologies Corporation
    Inventor: Mark Milgrew
  • Patent number: 8742472
    Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: June 3, 2014
    Assignee: Life Technologies Corporation
    Inventors: Jonathan M. Rothberg, Wolfgang Hinz, Kim L. Johnson, James Bustillo
  • Patent number: 8736077
    Abstract: Disclosed herein is a semiconductor package substrate including a base substrate, a mounting member mounted on an upper portion of the base substrate, and an adhesive layer formed between the base substrate and the mounting member, wherein the adhesive layer includes a thermally conductive adhesive and a ductile adhesive formed at the outer circumference of the thermally conductive adhesive.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Man Kim, Young Hoon Kwak, Kyu Hwan Oh, Seog Moon Choi, Tae Hoon Kim
  • Patent number: 8729632
    Abstract: A semiconductor structure comprising a semiconductor unit, a first conductive structure, a first conductive plug, and a second conductive structure is provided. The semiconductor unit has a substrate on a first side of the semiconductor unit. The substrate has at least a hole. The first conductive plug is in the hole and the hole may be full of the conductive plug. The first conductive structure is on the surface of the semiconductor unit. The surface is at the first side of the semiconductor unit. The second conductive structure is on a surface at a second side of the substrate of the semiconductor unit.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: May 20, 2014
    Assignee: Niko Semiconductor Co., Ltd.
    Inventors: Hsiu Wen Hsu, Chih Cheng Hsieh